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tegra: set AHB clock rate early 

Avoids glitches in later starup phases.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Lucas Stach 2014-02-17 21:27:40 +01:00 committed by Sascha Hauer
parent 6350676e55
commit 880869e55f
2 changed files with 7 additions and 0 deletions
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4
arch/arm/mach-tegra/include/mach/tegra20-car.h
View File

@ -112,6 +112,10 @@
#define CRC_SUPER_SDIV_DIVISOR_SHIFT 0
#define CRC_SUPER_SDIV_DIVISOR_MASK (0xff << CRC_SUPER_SDIV_DIVISOR_SHIFT)
#define CRC_CLK_SYSTEM_RATE 0x030
#define CRC_CLK_SYSTEM_RATE_AHB_SHIFT 4
#define CRC_CLK_SYSTEM_RATE_APB_SHIFT 0
#define CRC_CLK_CPU_CMPLX 0x04c
#define CRC_CLK_CPU_CMPLX_CPU3_CLK_STP (1 << 11)
#define CRC_CLK_CPU_CMPLX_CPU2_CLK_STP (1 << 10)

3
arch/arm/mach-tegra/tegra_avp_init.c
View File

@ -149,6 +149,9 @@ static void start_cpu0_clocks(void)
TEGRA_CLK_RESET_BASE + CRC_SCLK_BURST_POLICY);
writel(CRC_SUPER_SDIV_ENB, TEGRA_CLK_RESET_BASE + CRC_SUPER_SCLK_DIV);
writel(1 << CRC_CLK_SYSTEM_RATE_AHB_SHIFT,
TEGRA_CLK_RESET_BASE + CRC_CLK_SYSTEM_RATE);
/* deassert clock stop for cpu 0 */
reg = readl(TEGRA_CLK_RESET_BASE + CRC_CLK_CPU_CMPLX);
reg &= ~CRC_CLK_CPU_CMPLX_CPU0_CLK_STP;