MACH SAMSUNG/S3C: Prepare watchdog unit to be shared in the S3C family
Signed-off-by: Juergen Beisert <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -76,16 +76,20 @@ uint32_t s3c24x0_get_memory_size(void)
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return size;
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}
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#define S3C_WTCON (S3C_WATCHDOG_BASE)
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#define S3C_WTDAT (S3C_WATCHDOG_BASE + 0x04)
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#define S3C_WTCNT (S3C_WATCHDOG_BASE + 0x08)
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void __noreturn reset_cpu(unsigned long addr)
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{
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/* Disable watchdog */
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writew(0x0000, WTCON);
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writew(0x0000, S3C_WTCON);
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/* Initialize watchdog timer count register */
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writew(0x0001, WTCNT);
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writew(0x0001, S3C_WTCNT);
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/* Enable watchdog timer; assert reset at timer timeout */
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writew(0x0021, WTCON);
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writew(0x0021, S3C_WTCON);
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/* loop forever and wait for reset to happen */
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while(1)
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@ -31,7 +31,7 @@
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#define S3C24X0_UART_BASE 0x50000000
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#define S3C_TIMER_BASE 0x51000000
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#define S3C2410_USB_DEVICE_BASE 0x52000140
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#define S3C24X0_WATCHDOG_BASE 0x53000000
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#define S3C_WATCHDOG_BASE 0x53000000
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#define S3C2410_I2C_BASE 0x54000000
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#define S3C2410_I2S_BASE 0x55000000
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#define S3C24X0_GPIO_BASE 0x56000000
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@ -41,11 +41,6 @@
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#define S3C2410_SDI_BASE 0x5A000000
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/* Watchdog (direct access) */
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#define WTCON (S3C24X0_WATCHDOG_BASE)
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#define WTDAT (S3C24X0_WATCHDOG_BASE + 0x04)
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#define WTCNT (S3C24X0_WATCHDOG_BASE + 0x08)
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/*
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* if we are booting from NAND, its internal SRAM occures at
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* a different address than without this feature
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@ -29,7 +29,7 @@
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.globl s3c24x0_disable_wd
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s3c24x0_disable_wd:
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ldr r0, =S3C24X0_WATCHDOG_BASE
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ldr r0, =S3C_WATCHDOG_BASE
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mov r1, #0x0
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str r1, [r0]
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mov pc, lr
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