ARM: beaglebone: Clean up lowlevel code
Using here now the initialisiation functions in am33xx_generic. Signed-off-by: Teresa Gámez <t.gamez@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Teresa Gámez
Sascha Hauer
parent
0f13bd99b7
commit
88659d9c4a
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@ -13,211 +13,59 @@
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#include <mach/am33xx-generic.h>
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#include <mach/wdt.h>
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/* UART Defines */
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#define UART_SYSCFG_OFFSET (0x54)
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#define UART_SYSSTS_OFFSET (0x58)
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#define UART_RESET (0x1 << 1)
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#define UART_CLK_RUNNING_MASK 0x1
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#define UART_SMART_IDLE_EN (0x1 << 0x3)
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/* AM335X EMIF Register values */
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#define EMIF_SDMGT 0x80000000
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#define EMIF_SDRAM 0x00004650
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#define EMIF_PHYCFG 0x2
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#define DDR_PHY_RESET (0x1 << 10)
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#define DDR_FUNCTIONAL_MODE_EN 0x1
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#define DDR_PHY_READY (0x1 << 2)
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#define VTP_CTRL_READY (0x1 << 5)
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#define VTP_CTRL_ENABLE (0x1 << 6)
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#define VTP_CTRL_LOCK_EN (0x1 << 4)
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#define VTP_CTRL_START_EN (0x1)
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#define DDR2_RATIO 0x80 /* for mDDR */
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#define CMD_FORCE 0x00 /* common #def */
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#define CMD_DELAY 0x00
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#define EMIF_READ_LATENCY 0x05
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#define EMIF_TIM1 0x0666B3D6
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#define EMIF_TIM2 0x143731DA
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#define EMIF_TIM3 0x00000347
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#define EMIF_SDCFG 0x43805332
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#define EMIF_SDREF 0x0000081a
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#define DDR2_DLL_LOCK_DIFF 0x0
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#define DDR2_RD_DQS 0x12
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#define DDR2_PHY_FIFO_WE 0x80
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#define DDR2_INVERT_CLKOUT 0x00
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#define DDR2_WR_DQS 0x00
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#define DDR2_PHY_WRLVL 0x00
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#define DDR2_PHY_GATELVL 0x00
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#define DDR2_PHY_WR_DATA 0x40
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#define PHY_RANK0_DELAY 0x01
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#define PHY_DLL_LOCK_DIFF 0x0
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#define DDR_IOCTRL_VALUE 0x18B
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static void beaglebone_data_macro_config(int dataMacroNum)
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{
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u32 BaseAddrOffset = 0x00;
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static const struct am33xx_cmd_control ddr2_cmd_ctrl = {
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.slave_ratio0 = 0x80,
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.dll_lock_diff0 = 0x0,
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.invert_clkout0 = 0x0,
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.slave_ratio1 = 0x80,
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.dll_lock_diff1 = 0x0,
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.invert_clkout1 = 0x0,
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.slave_ratio2 = 0x80,
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.dll_lock_diff2 = 0x0,
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.invert_clkout2 = 0x0,
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};
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if (dataMacroNum == 1)
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BaseAddrOffset = 0xA4;
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__raw_writel(((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
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|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
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(AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
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__raw_writel(DDR2_RD_DQS>>2,
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(AM33XX_DATA0_RD_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
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__raw_writel(((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
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|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
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(AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
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__raw_writel(DDR2_WR_DQS>>2,
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(AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
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__raw_writel(((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
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|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
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(AM33XX_DATA0_WRLVL_INIT_RATIO_0 + BaseAddrOffset));
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__raw_writel(DDR2_PHY_WRLVL>>2,
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(AM33XX_DATA0_WRLVL_INIT_RATIO_1 + BaseAddrOffset));
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__raw_writel(((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
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|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
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(AM33XX_DATA0_GATELVL_INIT_RATIO_0 + BaseAddrOffset));
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__raw_writel(DDR2_PHY_GATELVL>>2,
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(AM33XX_DATA0_GATELVL_INIT_RATIO_1 + BaseAddrOffset));
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__raw_writel(((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
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|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
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(AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + BaseAddrOffset));
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__raw_writel(DDR2_PHY_FIFO_WE>>2,
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(AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1 + BaseAddrOffset));
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__raw_writel(((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
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|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
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(AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset));
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__raw_writel(DDR2_PHY_WR_DATA>>2,
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(AM33XX_DATA0_WR_DATA_SLAVE_RATIO_1 + BaseAddrOffset));
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__raw_writel(PHY_DLL_LOCK_DIFF,
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(AM33XX_DATA0_DLL_LOCK_DIFF_0 + BaseAddrOffset));
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}
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static void beaglebone_cmd_macro_config(void)
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{
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__raw_writel(DDR2_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0);
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__raw_writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0);
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__raw_writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0);
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__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0);
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__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0);
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__raw_writel(DDR2_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0);
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__raw_writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0);
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__raw_writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0);
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__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0);
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__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0);
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__raw_writel(DDR2_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0);
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__raw_writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0);
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__raw_writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0);
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__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0);
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__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0);
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}
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static void beaglebone_config_vtp(void)
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{
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__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE,
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AM33XX_VTP0_CTRL_REG);
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__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN),
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AM33XX_VTP0_CTRL_REG);
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__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN,
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AM33XX_VTP0_CTRL_REG);
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/* Poll for READY */
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while ((__raw_readl(AM33XX_VTP0_CTRL_REG) & VTP_CTRL_READY) != VTP_CTRL_READY);
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}
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static void beaglebone_config_emif_ddr2(void)
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{
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u32 i;
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/*Program EMIF0 CFG Registers*/
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__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1));
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__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW));
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__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2));
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__raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1));
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__raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW));
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__raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2));
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__raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW));
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__raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3));
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__raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW));
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__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
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__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
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/* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
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__raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
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__raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
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__raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
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for (i = 0; i < 5000; i++) {
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}
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/* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
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__raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
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__raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
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__raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
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__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
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__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
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}
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static void beaglebone_config_ddr(void)
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{
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enable_ddr_clocks();
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beaglebone_config_vtp();
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beaglebone_cmd_macro_config();
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beaglebone_data_macro_config(0);
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beaglebone_data_macro_config(1);
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__raw_writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0);
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__raw_writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0);
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__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL);
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__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL);
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__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL);
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__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL);
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__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL);
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__raw_writel(__raw_readl(AM33XX_DDR_IO_CTRL) & 0xefffffff, AM33XX_DDR_IO_CTRL);
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__raw_writel(__raw_readl(AM33XX_DDR_CKE_CTRL) | 0x00000001, AM33XX_DDR_CKE_CTRL);
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beaglebone_config_emif_ddr2();
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}
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/*
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* early system init of muxing and clocks.
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*/
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void beaglebone_sram_init(void)
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{
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u32 regVal, uart_base;
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/* Setup the PLLs and the clocks for the peripherals */
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pll_init(MPUPLL_M_500, 24);
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beaglebone_config_ddr();
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/* UART softreset */
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uart_base = AM33XX_UART0_BASE;
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regVal = __raw_readl(uart_base + UART_SYSCFG_OFFSET);
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regVal |= UART_RESET;
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__raw_writel(regVal, (uart_base + UART_SYSCFG_OFFSET) );
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while ((__raw_readl(uart_base + UART_SYSSTS_OFFSET) &
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UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK);
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/* Disable smart idle */
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regVal = __raw_readl((uart_base + UART_SYSCFG_OFFSET));
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regVal |= UART_SMART_IDLE_EN;
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__raw_writel(regVal, (uart_base + UART_SYSCFG_OFFSET));
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}
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static const struct am33xx_emif_regs ddr2_regs = {
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.emif_read_latency = 0x5,
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.emif_tim1 = 0x0666B3D6,
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.emif_tim2 = 0x143731DA,
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.emif_tim3 = 0x00000347,
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.sdram_config = 0x43805332,
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.sdram_config2 = 0x43805332,
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.sdram_ref_ctrl = 0x0000081a,
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};
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static const struct am33xx_ddr_data ddr2_data = {
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.rd_slave_ratio0 = (DDR2_RD_DQS << 30) | (DDR2_RD_DQS << 20) |
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(DDR2_RD_DQS << 10) | (DDR2_RD_DQS << 0),
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.wr_dqs_slave_ratio0 = (DDR2_WR_DQS << 30) | (DDR2_WR_DQS << 20) |
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(DDR2_WR_DQS << 10) | (DDR2_WR_DQS << 0),
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.wrlvl_init_ratio0 = (DDR2_PHY_WRLVL << 30) |
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(DDR2_PHY_WRLVL << 20) |
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(DDR2_PHY_WRLVL << 10) |
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(DDR2_PHY_WRLVL << 0),
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.gatelvl_init_ratio0 = (DDR2_PHY_GATELVL << 30) |
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(DDR2_PHY_GATELVL << 20) |
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(DDR2_PHY_GATELVL << 10) |
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(DDR2_PHY_GATELVL << 0),
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.fifo_we_slave_ratio0 = (DDR2_PHY_FIFO_WE << 30) |
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(DDR2_PHY_FIFO_WE << 20) |
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(DDR2_PHY_FIFO_WE << 10) |
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(DDR2_PHY_FIFO_WE << 0),
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.wr_slave_ratio0 = (DDR2_PHY_WR_DATA << 30) |
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(DDR2_PHY_WR_DATA << 20) |
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(DDR2_PHY_WR_DATA << 10) |
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(DDR2_PHY_WR_DATA << 0),
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.use_rank0_delay = 0x01,
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.dll_lock_diff0 = 0x0,
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};
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/**
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* @brief The basic entry point for board initialization.
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@ -230,8 +78,6 @@ void beaglebone_sram_init(void)
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*/
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static int beaglebone_board_init(void)
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{
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int in_sdram = running_in_sdram();
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/* WDT1 is already running when the bootloader gets control
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* Disable it to avoid "random" resets
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*/
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@ -240,11 +86,13 @@ static int beaglebone_board_init(void)
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__raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
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while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
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/* Dont reconfigure SDRAM while running in SDRAM! */
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if (!in_sdram)
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beaglebone_sram_init();
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if (running_in_sdram())
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return 0;
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pll_init(MPUPLL_M_500, 24);
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am335x_sdram_init(0x18B, &ddr2_cmd_ctrl, &ddr2_regs, &ddr2_data);
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/* Enable pin mux */
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am33xx_enable_uart0_pin_mux();
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return 0;
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