diff --git a/arch/arm/boards/archosg9/lowlevel.c b/arch/arm/boards/archosg9/lowlevel.c
index 033469396..49c1541a4 100644
--- a/arch/arm/boards/archosg9/lowlevel.c
+++ b/arch/arm/boards/archosg9/lowlevel.c
@@ -48,8 +48,7 @@ static noinline void archosg9_init_lowlevel(void)
 
 	set_muxconf_regs();
 
-	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
-	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
+	omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1380);
 
 	/* Enable all clocks */
 	omap4_enable_all_clocks();
diff --git a/arch/arm/boards/panda/lowlevel.c b/arch/arm/boards/panda/lowlevel.c
index ed1dc6f5f..5d3490f82 100644
--- a/arch/arm/boards/panda/lowlevel.c
+++ b/arch/arm/boards/panda/lowlevel.c
@@ -52,6 +52,7 @@ static void noinline panda_init_lowlevel(void)
 	struct dpll_param per = OMAP4_PER_DPLL_PARAM_38M4;
 	struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_38M4;
 	struct dpll_param usb = OMAP4_USB_DPLL_PARAM_38M4;
+	unsigned int rev = omap4_revision();
 
 	writel(CM_SYS_CLKSEL_38M4, CM_SYS_CLKSEL);
 
@@ -69,8 +70,10 @@ static void noinline panda_init_lowlevel(void)
 
 	omap4_ddr_init(&ddr_regs_400_mhz_2cs, &core);
 
-	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
-	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
+	if (rev < OMAP4460_ES1_0)
+		omap4430_scale_vcores();
+	else
+		omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1210);
 }
 
 void barebox_arm_reset_vector(void)
diff --git a/arch/arm/boards/pcm049/lowlevel.c b/arch/arm/boards/pcm049/lowlevel.c
index 8bcecb14b..6b12fa40a 100644
--- a/arch/arm/boards/pcm049/lowlevel.c
+++ b/arch/arm/boards/pcm049/lowlevel.c
@@ -67,6 +67,7 @@ static void noinline pcm049_init_lowlevel(void)
 	struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2;
 	struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2;
 	struct dpll_param usb = OMAP4_USB_DPLL_PARAM_19M2;
+	unsigned int rev = omap4_revision();
 
 	set_muxconf_regs();
 
@@ -77,12 +78,15 @@ static void noinline pcm049_init_lowlevel(void)
 #endif
 
 	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
-	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
+	if (rev < OMAP4460_ES1_0)
+		omap4430_scale_vcores();
+	else
+		omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1320);
 
 	writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL);
 
 	/* Configure all DPLL's at 100% OPP */
-	if (omap4_revision() < OMAP4460_ES1_0)
+	if (rev < OMAP4460_ES1_0)
 		omap4_configure_mpu_dpll(&mpu44xx);
 	else
 		omap4_configure_mpu_dpll(&mpu4460);
diff --git a/arch/arm/boards/phycard-a-xl2/lowlevel.c b/arch/arm/boards/phycard-a-xl2/lowlevel.c
index 07505ffbc..010171a04 100644
--- a/arch/arm/boards/phycard-a-xl2/lowlevel.c
+++ b/arch/arm/boards/phycard-a-xl2/lowlevel.c
@@ -52,18 +52,21 @@ static noinline void pcaaxl2_init_lowlevel(void)
 	struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2;
 	struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2;
 	struct dpll_param usb = OMAP4_USB_DPLL_PARAM_19M2;
+	unsigned int rev = omap4_revision();
 
 	set_muxconf_regs();
 
 	omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
 
-	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
-	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
+	if (rev < OMAP4460_ES1_0)
+		omap4430_scale_vcores();
+	else
+		omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1320);
 
 	writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL);
 
 	/* Configure all DPLL's at 100% OPP */
-	if (omap4_revision() < OMAP4460_ES1_0)
+	if (rev < OMAP4460_ES1_0)
 		omap4_configure_mpu_dpll(&mpu44xx);
 	else
 		omap4_configure_mpu_dpll(&mpu4460);
diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h
index 666e72155..336415c16 100644
--- a/arch/arm/mach-omap/include/mach/omap4-silicon.h
+++ b/arch/arm/mach-omap/include/mach/omap4-silicon.h
@@ -230,7 +230,8 @@ struct dpll_param;
 void omap4_ddr_init(const struct ddr_regs *, const struct dpll_param *);
 void omap4_power_i2c_send(u32);
 unsigned int omap4_revision(void);
-noinline int omap4_scale_vcores(unsigned vsel0_pin);
+int omap4430_scale_vcores(void);
+int omap4460_scale_vcores(unsigned vsel0_pin, unsigned volt_mv);
 void omap4_set_warmboot_order(u32 *device_list);
 
 #endif
diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
index 3d6ec25c9..a21f156e5 100644
--- a/arch/arm/mach-omap/omap4_generic.c
+++ b/arch/arm/mach-omap/omap4_generic.c
@@ -537,11 +537,9 @@ static void __iomem *omap4_get_gpio_base(unsigned gpio)
 
 #define I2C_SLAVE 0x12
 
-noinline int omap4_scale_vcores(unsigned vsel0_pin)
+noinline int omap4430_scale_vcores(void)
 {
-	void __iomem *base;
 	unsigned int rev = omap4_revision();
-	u32 val = 0;
 
 	/* For VC bypass only VCOREx_CGF_FORCE  is necessary and
 	 * VCOREx_CFG_VOLTAGE  changes can be discarded
@@ -549,50 +547,16 @@ noinline int omap4_scale_vcores(unsigned vsel0_pin)
 	writel(0, OMAP44XX_PRM_VC_CFG_I2C_MODE);
 	writel(0x6026, OMAP44XX_PRM_VC_CFG_I2C_CLK);
 
-	/* TPS - supplies vdd_mpu on 4460 */
-	if (rev >= OMAP4460_ES1_0) {
-		/*
-		 * Setup SET1 and SET0 with right values so that kernel
-		 * can use either of them based on its needs.
-		 */
-		omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET0, 1430);
-		omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET1, 1430);
-
-		/*
-		 * Select SET1 in TPS62361:
-		 * VSEL1 is grounded on board. So the following selects
-		 * VSEL1 = 0 and VSEL0 = 1
-		 */
-		base = omap4_get_gpio_base(vsel0_pin);
-
-		val = 1 << (vsel0_pin & GPIO_MASK);
-		writel(val, base + 0x190);
-
-		val =  readl(base + 0x134);
-		val &= ~(1 << (vsel0_pin & GPIO_MASK));
-		writel(val, base + 0x134);
-
-		val = 1 << (vsel0_pin & GPIO_MASK);
-		writel(val, base + 0x194);
-	}
-
-	/* set VCORE1 force VSEL */
-	/*
+	/* set VCORE1 force VSEL
 	 * 4430 : supplies vdd_mpu
 	 * Setting a high voltage for Nitro mode as smart reflex is not enabled.
 	 * We use the maximum possible value in the AVS range because the next
 	 * higher voltage in the discrete range (code >= 0b111010) is way too
 	 * high
-	 *
-	 * 4460 : supplies vdd_core
-	 *
 	 */
-	if (rev < OMAP4460_ES1_0)
-		/* 0x55: i2c addr, 3A: ~ 1430 mvolts*/
-		omap4_power_i2c_send((0x3A55 << 8) | I2C_SLAVE);
-	else
-		/* 0x55: i2c addr, 28: ~ 1200 mvolts*/
-		omap4_power_i2c_send((0x2855 << 8) | I2C_SLAVE);
+
+	/* 0x55: i2c addr, 3A: ~ 1430 mvolts*/
+	omap4_power_i2c_send((0x3A55 << 8) | I2C_SLAVE);
 
 	/* FIXME: set VCORE2 force VSEL, Check the reset value */
 	omap4_power_i2c_send((0x295B << 8) | I2C_SLAVE);
@@ -605,12 +569,60 @@ noinline int omap4_scale_vcores(unsigned vsel0_pin)
 	case OMAP4430_ES2_1:
 		omap4_power_i2c_send((0x2A61 << 8) | I2C_SLAVE);
 		break;
-	/* > OMAP4460_ES1_0 : VCORE3 not connected */
 	}
 
 	return 0;
 }
 
+noinline int omap4460_scale_vcores(unsigned vsel0_pin, unsigned volt_mv)
+{
+	void __iomem *base;
+	u32 val = 0;
+
+	/* For VC bypass only VCOREx_CGF_FORCE  is necessary and
+	 * VCOREx_CFG_VOLTAGE  changes can be discarded
+	 */
+	writel(0, OMAP44XX_PRM_VC_CFG_I2C_MODE);
+	writel(0x6026, OMAP44XX_PRM_VC_CFG_I2C_CLK);
+
+	/* TPS - supplies vdd_mpu on 4460
+	 * Setup SET1 and SET0 with right values so that kernel
+	 * can use either of them based on its needs.
+	 */
+
+	omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET0, volt_mv);
+	omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt_mv);
+
+	/*
+	 * Select SET1 in TPS62361:
+	 * VSEL1 is grounded on board. So the following selects
+	 * VSEL1 = 0 and VSEL0 = 1
+	 */
+	base = omap4_get_gpio_base(vsel0_pin);
+
+	val = 1 << (vsel0_pin & GPIO_MASK);
+	writel(val, base + 0x190);
+
+	val =  readl(base + 0x134);
+	val &= ~(1 << (vsel0_pin & GPIO_MASK));
+	writel(val, base + 0x134);
+
+	val = 1 << (vsel0_pin & GPIO_MASK);
+	writel(val, base + 0x194);
+
+	/* set VCORE1 force VSEL
+	 * 4460 : supplies vdd_core
+	 */
+
+	/* 0x55: i2c addr, 28: ~ 1200 mvolts*/
+	omap4_power_i2c_send((0x2855 << 8) | I2C_SLAVE);
+
+	/* FIXME: set VCORE2 force VSEL, Check the reset value */
+	omap4_power_i2c_send((0x295B << 8) | I2C_SLAVE);
+
+	return 0;
+}
+
 void omap4_do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
 {
 	int i;