Add Barco Streaming Video Card (SVC) and Sample Compress Network (SCN) board
Patch by Marc Leeman, 04 Mar 2005
This commit is contained in:
Wolfgang Denk
parent
716c1dcb41
commit
8e6f1a8ec2
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@ -2,6 +2,9 @@
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Changes for U-Boot 1.1.4:
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======================================================================
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* Add Barco Streaming Video Card (SVC) and Sample Compress Network (SCN) board
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Patch by Marc Leeman, 04 Mar 2005
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* OMAP242x H4 board update
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- fix for ES2 differences.
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- switch to using the cfi_flash driver.
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5
CREDITS
5
CREDITS
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@ -255,6 +255,11 @@ N: Thomas Lange
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E: thomas@corelatus.se
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D: Support for GTH and dbau1x00 boards; lots of PCMCIA fixes
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N: Marc Leeman
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E: marc.leeman@barco.com
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D: Support for Barco Streaming Video Card (SVC) and Sample Compress Network (SCN)
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W: www.barco.com
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N: The LEOX team
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E: team@leox.org
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D: Support for LEOX boards, DS164x RTC
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10
MAKEALL
10
MAKEALL
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@ -88,11 +88,11 @@ LIST_8220=" \
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#########################################################################
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LIST_824x=" \
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A3000 BMW CPC45 CU824 \
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debris eXalion HIDDEN_DRAGON MOUSSE \
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MUSENKI MVBLUE OXC PN62 \
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Sandpoint8240 Sandpoint8245 SL8245 utx8245 \
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sbc8240 \
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A3000 barco BMW CPC45 \
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CU824 debris eXalion HIDDEN_DRAGON \
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MOUSSE MUSENKI MVBLUE OXC \
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PN62 Sandpoint8240 Sandpoint8245 sbc8240 \
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SL8245 utx8245 \
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"
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#########################################################################
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3
Makefile
3
Makefile
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@ -929,6 +929,9 @@ xtract_82xx = $(subst _BIGFLASH,,$(subst _ROMBOOT,,$(subst _L2,,$(subst _266MHz,
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A3000_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc824x a3000
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barco_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc824x barco
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BMW_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc824x bmw
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@ -0,0 +1,40 @@
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#
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# (C) Copyright 2000
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o flash.o
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$(LIB): .depend $(OBJS)
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$(AR) crv $@ $(OBJS)
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#########################################################################
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.depend: Makefile $(OBJS:.o=.c)
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$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
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sinclude .depend
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#########################################################################
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@ -0,0 +1,11 @@
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This port of U-Boot is tuned to run on a range of Barco Control Rooms
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Streaming Video Solutions, including:
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- Streaming Video Card (SVC)
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- Sample Compress Network (SCN)
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For more information, see http://www.barcocontrolrooms.com/
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Code and configuration are originally based on the Sandpoint board
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Marc Leeman <marc.leeman@barco.com>
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@ -0,0 +1,340 @@
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/********************************************************************
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*
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* Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
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*
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* $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/barco.c,v $
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* $Revision: 1.4 $
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* $Author: mleeman $
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* $Date: 2005/03/02 16:40:20 $
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*
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* Last ChangeLog Entry
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* $Log: barco.c,v $
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* Revision 1.4 2005/03/02 16:40:20 mleeman
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* remove empty labels (3.4 complains)
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*
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* Revision 1.3 2005/02/21 12:48:58 mleeman
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* update of copyright years (feedback wd)
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*
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* Revision 1.2 2005/02/21 10:10:53 mleeman
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* - split up switch statement to a function call (Linux kernel coding guidelines)
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* ( feedback wd)
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*
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* Revision 1.1 2005/02/14 09:31:07 mleeman
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* renaming of files
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*
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* Revision 1.1 2005/02/14 09:23:46 mleeman
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* - moved 'barcohydra' directory to a more generic barco; since we will be
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* supporting and adding multiple boards
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*
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* Revision 1.3 2005/02/10 13:57:32 mleeman
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* fixed flash corruption: I should exit from the moment I find the correct value
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*
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* Revision 1.2 2005/02/09 12:56:23 mleeman
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* add generic header to track changes in sources
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*
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*
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*******************************************************************/
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/*
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* (C) Copyright 2004
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* Marc Leeman <marc.leeman@barco.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc824x.h>
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#include <pci.h>
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#include <malloc.h>
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#include <command.h>
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#include "config.h"
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#include "barco_svc.h"
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#define TRY_WORKING (3)
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#define BOOT_DEFAULT (2)
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#define BOOT_WORKING (1)
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int checkboard (void)
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{
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/*TODO: Check processor type */
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puts ( "Board: Streaming Video Card for Hydra systems "
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#ifdef CONFIG_MPC8240
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"8240"
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#endif
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#ifdef CONFIG_MPC8245
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"8245"
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#endif
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" Unity ##Test not implemented yet##\n");
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return 0;
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}
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long int initdram (int board_type)
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{
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long size;
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long new_bank0_end;
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long mear1;
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long emear1;
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size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
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new_bank0_end = size - 1;
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mear1 = mpc824x_mpc107_getreg(MEAR1);
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emear1 = mpc824x_mpc107_getreg(EMEAR1);
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mear1 = (mear1 & 0xFFFFFF00) |
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((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
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emear1 = (emear1 & 0xFFFFFF00) |
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((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
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mpc824x_mpc107_setreg(MEAR1, mear1);
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mpc824x_mpc107_setreg(EMEAR1, emear1);
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return (size);
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}
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/*
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* Initialize PCI Devices, report devices found.
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*/
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#ifndef CONFIG_PCI_PNP
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static struct pci_config_table pci_barcohydra_config_table[] = {
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
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pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
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pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
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PCI_ENET1_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
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{ }
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};
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#endif
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struct pci_controller hose = {
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#ifndef CONFIG_PCI_PNP
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config_table: pci_barcohydra_config_table,
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#endif
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};
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void pci_init_board(void)
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{
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pci_mpc824x_init(&hose);
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}
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int write_flash(char *addr, char value)
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{
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char *adr = (char *)0xFF800000;
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int cnt = 0;
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char status,oldstatus;
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*(adr+0x55) = 0xAA;
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udelay(1);
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*(adr+0xAA) = 0x55;
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udelay(1);
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*(adr+0x55) = 0xA0;
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udelay(1);
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*addr = value;
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status = *addr;
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do{
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oldstatus = status;
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status = *addr;
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if ((oldstatus & 0x40) == (status & 0x40)){
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return 4;
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}
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cnt++;
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if (cnt > 10000){
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return 2;
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}
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}while( (status & 0x20) == 0 );
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oldstatus = *addr;
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status = *addr;
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if ((oldstatus & 0x40) == (status & 0x40)) return 0;
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else {
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*(adr+0x55) = 0xF0;
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return 1;
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}
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}
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unsigned update_flash(unsigned char* buf){
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switch((*buf) & 0x3){
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case TRY_WORKING:
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printf("found 3 and converted it to 2\n");
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write_flash(buf, (*buf) & 0xFE);
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*((unsigned char *)0xFF800000) = 0xF0;
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udelay(100);
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printf("buf [%#010x] %#010x\n",buf,(*buf));
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case BOOT_WORKING :
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return BOOT_WORKING;
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}
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return BOOT_DEFAULT;
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}
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unsigned scan_flash(void)
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{
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char section[] = "kernel";
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ulong sp;
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int cfgFileLen = (CFG_FLASH_ERASE_SECTOR_LENGTH >> 1);
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int sectionPtr = 0;
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int foundItem = 0; /* 0: None, 1: section found, 2: "=" found */
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int bufPtr;
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unsigned char *buf;
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buf = (unsigned char*)(CFG_FLASH_RANGE_BASE + CFG_FLASH_RANGE_SIZE \
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- CFG_FLASH_ERASE_SECTOR_LENGTH);
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for(bufPtr = 0; bufPtr < cfgFileLen; ++bufPtr){
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if ((buf[bufPtr]==0xFF) && (*(int*)(buf+bufPtr)==0xFFFFFFFF)) {
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return BOOT_DEFAULT;
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}
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switch(foundItem)
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{
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/* This is the scanning loop, we try to find a particular
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* quoted value
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*/
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case 0:
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if((section[sectionPtr] == 0)){
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++foundItem;
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}
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else if(buf[bufPtr] == section[sectionPtr]){
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++sectionPtr;
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}
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else {
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sectionPtr = 0;
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}
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break;
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case 1:
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++foundItem;
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break;
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case 2:
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++foundItem;
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break;
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case 3:
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default:
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return update_flash(buf[bufPtr - 1]);
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}
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}
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printf("Failed to read %s\n",section);
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return BOOT_DEFAULT;
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}
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TSBootInfo* find_boot_info(void)
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{
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unsigned bootimage = scan_flash();
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TSBootInfo* info = (TSBootInfo*)malloc(sizeof(TSBootInfo));
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switch(bootimage){
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case TRY_WORKING:
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info->address = CFG_WORKING_KERNEL_ADDRESS;
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break;
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case BOOT_WORKING :
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info->address = CFG_WORKING_KERNEL_ADDRESS;
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break;
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case BOOT_DEFAULT:
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default:
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info->address= CFG_DEFAULT_KERNEL_ADDRESS;
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}
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info->size = *((unsigned int *)(info->address ));
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return info;
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}
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void barcobcd_boot(void)
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{
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TSBootInfo* start;
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char *bootm_args[2];
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char *buf;
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int cnt;
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buf = (char *)(0x00800000);
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/* make certain there are enough chars to print the command line here!
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*/
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bootm_args[0]=(char *)malloc(16*sizeof(char));
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bootm_args[1]=(char *)malloc(16*sizeof(char));
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start = find_boot_info();
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printf("Booting kernel at address %#10x with size %#10x\n",
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start->address, start->size);
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/* give length of the kernel image to bootm */
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sprintf(bootm_args[0],"%x",start->size);
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/* give address of the kernel image to bootm */
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sprintf(bootm_args[1],"%x",buf);
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printf("flash address: %#10x\n",start->address+8);
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printf("buf address: %#10x\n",buf);
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/* aha, we reserve 8 bytes here... */
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for (cnt = 0; cnt < start->size ; cnt++){
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buf[cnt] = ((char *)start->address)[cnt+8];
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}
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/* initialise RAM memory */
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*((unsigned int *)0xFEC00000) = 0x00141A98;
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do_bootm(NULL,0,2,bootm_args);
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}
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int barcobcd_boot_image(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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#if 0
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if (argc > 1) {
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printf ("Usage:\n (%d) %s\n", argc, cmdtp->usage);
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return 1;
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}
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#endif
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barcobcd_boot();
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return 0;
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}
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/* Currently, boot_working and boot_default are the same command. This is
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* left in here to see what we'll do in the future */
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U_BOOT_CMD(
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try_working, 1, 1, barcobcd_boot_image,
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" try_working - check flash value and boot the appropriate image\n",
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"\n"
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);
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U_BOOT_CMD(
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boot_working, 1, 1, barcobcd_boot_image,
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" boot_working - check flash value and boot the appropriate image\n",
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"\n"
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);
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U_BOOT_CMD(
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boot_default, 1, 1, barcobcd_boot_image,
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" boot_default - check flash value and boot the appropriate image\n",
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"\n"
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);
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/*
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* We are not using serial communication, so just provide empty functions
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*/
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int serial_init(void){return 0;}
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void serial_setbrg(void){}
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void serial_putc(const char c){}
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void serial_puts(const char *c){}
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void serial_addr(unsigned int i){}
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int serial_getc(void){return 0;}
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int serial_tstc(void){return 0;}
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unsigned long post_word_load(void){return 0l;};
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void post_word_store(unsigned long val){}
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|
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@ -0,0 +1,68 @@
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/********************************************************************
|
||||
*
|
||||
* Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
|
||||
*
|
||||
* $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/barco_svc.h,v $
|
||||
* $Revision: 1.2 $
|
||||
* $Author: mleeman $
|
||||
* $Date: 2005/02/21 12:48:58 $
|
||||
*
|
||||
* Last ChangeLog Entry
|
||||
* $Log: barco_svc.h,v $
|
||||
* Revision 1.2 2005/02/21 12:48:58 mleeman
|
||||
* update of copyright years (feedback wd)
|
||||
*
|
||||
* Revision 1.1 2005/02/14 09:31:07 mleeman
|
||||
* renaming of files
|
||||
*
|
||||
* Revision 1.1 2005/02/14 09:23:46 mleeman
|
||||
* - moved 'barcohydra' directory to a more generic barco; since we will be
|
||||
* supporting and adding multiple boards
|
||||
*
|
||||
* Revision 1.1 2005/02/08 15:40:19 mleeman
|
||||
* modified and added platform files
|
||||
*
|
||||
* Revision 1.2 2005/01/25 08:05:04 mleeman
|
||||
* more cleanup of the code
|
||||
*
|
||||
* Revision 1.1 2004/07/20 08:49:55 mleeman
|
||||
* Working version of the default and nfs kernel booting.
|
||||
*
|
||||
*
|
||||
*******************************************************************/
|
||||
|
||||
#ifndef _LOCAL_BARCOHYDRA_H_
|
||||
#define _LOCAL_BARCOHYDRA_H_
|
||||
|
||||
#include <flash.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
/* Defines for the barcohydra board */
|
||||
#ifndef CFG_FLASH_ERASE_SECTOR_LENGTH
|
||||
#define CFG_FLASH_ERASE_SECTOR_LENGTH (0x10000)
|
||||
#endif
|
||||
|
||||
#ifndef CFG_DEFAULT_KERNEL_ADDRESS
|
||||
#define CFG_DEFAULT_KERNEL_ADDRESS (CFG_FLASH_BASE + 0x30000)
|
||||
#endif
|
||||
|
||||
#ifndef CFG_WORKING_KERNEL_ADDRESS
|
||||
#define CFG_WORKING_KERNEL_ADDRESS (0xFFE00000)
|
||||
#endif
|
||||
|
||||
|
||||
typedef struct SBootInfo {
|
||||
unsigned int address;
|
||||
unsigned int size;
|
||||
unsigned char state;
|
||||
}TSBootInfo;
|
||||
|
||||
/* barcohydra.c */
|
||||
int checkboard(void);
|
||||
long int initdram(int board_type);
|
||||
void pci_init_board(void);
|
||||
void check_flash(void);
|
||||
int write_flash(char *addr, char value);
|
||||
TSBootInfo* find_boot_info(void);
|
||||
void final_boot(void);
|
||||
#endif
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
#
|
||||
# (C) Copyright 2000, 2001
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# Barco Hydra/SCN boards
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xFFF00000
|
||||
|
||||
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
|
||||
|
|
@ -0,0 +1,152 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Thomas Koeller, tkoeller@gmx.net
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define __ASSEMBLY__ 1
|
||||
#endif
|
||||
|
||||
#include <config.h>
|
||||
#include <asm/processor.h>
|
||||
#include <mpc824x.h>
|
||||
#include <ppc_asm.tmpl>
|
||||
|
||||
#if defined(USE_DINK32)
|
||||
/* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */
|
||||
#define MCCR1VAL ((CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
|
||||
#else
|
||||
#define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT)
|
||||
#endif
|
||||
|
||||
.text
|
||||
|
||||
/* Values to program into memory controller registers */
|
||||
tbl: .long MCCR1, MCCR1VAL
|
||||
.long MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT
|
||||
.long MCCR3
|
||||
.long (((CFG_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
|
||||
(CFG_REFREC << MCCR3_REFREC_SHIFT) | \
|
||||
(CFG_RDLAT << MCCR3_RDLAT_SHIFT)
|
||||
.long MCCR4
|
||||
.long (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
|
||||
(CFG_REGISTERD_TYPE_BUFFER << 20) | \
|
||||
(((CFG_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
|
||||
((CFG_SDMODE_CAS_LAT << 4) | (CFG_SDMODE_WRAP << 3) | \
|
||||
(CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
|
||||
(CFG_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
|
||||
((CFG_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
|
||||
.long MSAR1
|
||||
.long (((CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
|
||||
(((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
|
||||
(((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
|
||||
(((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
|
||||
.long EMSAR1
|
||||
.long (((CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
|
||||
(((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
|
||||
(((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
|
||||
(((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
|
||||
.long MSAR2
|
||||
.long (((CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
|
||||
(((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
|
||||
(((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
|
||||
(((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
|
||||
.long EMSAR2
|
||||
.long (((CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
|
||||
(((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
|
||||
(((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
|
||||
(((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
|
||||
.long MEAR1
|
||||
.long (((CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
|
||||
(((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
|
||||
(((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
|
||||
(((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
|
||||
.long EMEAR1
|
||||
.long (((CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
|
||||
(((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
|
||||
(((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
|
||||
(((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
|
||||
.long MEAR2
|
||||
.long (((CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
|
||||
(((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
|
||||
(((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
|
||||
(((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
|
||||
.long EMEAR2
|
||||
.long (((CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
|
||||
(((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
|
||||
(((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
|
||||
(((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
|
||||
.long 0
|
||||
|
||||
|
||||
/*
|
||||
* Early CPU initialization. Set up memory controller, so we can access any RAM at all. This
|
||||
* must be done in assembly, since we have no stack at this point.
|
||||
*/
|
||||
.global early_init_f
|
||||
early_init_f:
|
||||
mflr r10
|
||||
|
||||
/* basic memory controller configuration */
|
||||
lis r3, CONFIG_ADDR_HIGH
|
||||
lis r4, CONFIG_DATA_HIGH
|
||||
bl lab
|
||||
lab: mflr r5
|
||||
lwzu r0, tbl - lab(r5)
|
||||
loop: lwz r1, 4(r5)
|
||||
stwbrx r0, 0, r3
|
||||
eieio
|
||||
stwbrx r1, 0, r4
|
||||
eieio
|
||||
lwzu r0, 8(r5)
|
||||
cmpli cr0, 0, r0, 0
|
||||
bne cr0, loop
|
||||
|
||||
/* set bank enable bits */
|
||||
lis r0, MBER@h
|
||||
ori r0, 0, MBER@l
|
||||
li r1, CFG_BANK_ENABLE
|
||||
stwbrx r0, 0, r3
|
||||
eieio
|
||||
stb r1, 0(r4)
|
||||
eieio
|
||||
|
||||
/* delay loop */
|
||||
lis r0, 0x0003
|
||||
mtctr r0
|
||||
delay: bdnz delay
|
||||
|
||||
/* enable memory controller */
|
||||
lis r0, MCCR1@h
|
||||
ori r0, 0, MCCR1@l
|
||||
stwbrx r0, 0, r3
|
||||
eieio
|
||||
lwbrx r0, 0, r4
|
||||
oris r0, 0, MCCR1_MEMGO@h
|
||||
stwbrx r0, 0, r4
|
||||
eieio
|
||||
|
||||
/* set up stack pointer */
|
||||
lis r1, CFG_INIT_SP_OFFSET@h
|
||||
ori r1, r1, CFG_INIT_SP_OFFSET@l
|
||||
|
||||
mtlr r10
|
||||
blr
|
||||
|
|
@ -0,0 +1,611 @@
|
|||
/********************************************************************
|
||||
*
|
||||
* Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
|
||||
*
|
||||
* $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/flash.c,v $
|
||||
* $Revision: 1.3 $
|
||||
* $Author: mleeman $
|
||||
* $Date: 2005/02/21 12:48:58 $
|
||||
*
|
||||
* Last ChangeLog Entry
|
||||
* $Log: flash.c,v $
|
||||
* Revision 1.3 2005/02/21 12:48:58 mleeman
|
||||
* update of copyright years (feedback wd)
|
||||
*
|
||||
* Revision 1.2 2005/02/21 11:04:04 mleeman
|
||||
* remove dead code and Coding style (feedback wd)
|
||||
*
|
||||
* Revision 1.1 2005/02/14 09:23:46 mleeman
|
||||
* - moved 'barcohydra' directory to a more generic barco; since we will be
|
||||
* supporting and adding multiple boards
|
||||
*
|
||||
* Revision 1.2 2005/02/09 12:56:23 mleeman
|
||||
* add generic header to track changes in sources
|
||||
*
|
||||
*
|
||||
*******************************************************************/
|
||||
|
||||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc824x.h>
|
||||
#include <asm/processor.h>
|
||||
#include <flash.h>
|
||||
|
||||
#define ROM_CS0_START 0xFF800000
|
||||
#define ROM_CS1_START 0xFF000000
|
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
#if defined(CFG_ENV_IS_IN_FLASH)
|
||||
# ifndef CFG_ENV_ADDR
|
||||
# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
|
||||
# endif
|
||||
# ifndef CFG_ENV_SIZE
|
||||
# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
|
||||
# endif
|
||||
# ifndef CFG_ENV_SECT_SIZE
|
||||
# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static int write_word (flash_info_t *info, ulong dest, ulong data);
|
||||
|
||||
/*flash command address offsets*/
|
||||
|
||||
#define ADDR0 (0xAAA)
|
||||
#define ADDR1 (0x555)
|
||||
#define ADDR3 (0x001)
|
||||
|
||||
#define FLASH_WORD_SIZE unsigned char
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
static unsigned long flash_id(unsigned char mfct, unsigned char chip) __attribute__ ((const));
|
||||
|
||||
typedef struct{
|
||||
FLASH_WORD_SIZE extval;
|
||||
unsigned short intval;
|
||||
} map_entry;
|
||||
|
||||
static unsigned long flash_id(unsigned char mfct, unsigned char chip)
|
||||
{
|
||||
static const map_entry mfct_map[] = {
|
||||
{(FLASH_WORD_SIZE) AMD_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)},
|
||||
{(FLASH_WORD_SIZE) FUJ_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)},
|
||||
{(FLASH_WORD_SIZE) STM_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)},
|
||||
{(FLASH_WORD_SIZE) MT_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)},
|
||||
{(FLASH_WORD_SIZE) INTEL_MANUFACT,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)},
|
||||
{(FLASH_WORD_SIZE) INTEL_ALT_MANU,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}
|
||||
};
|
||||
|
||||
static const map_entry chip_map[] = {
|
||||
{AMD_ID_F040B, FLASH_AM040},
|
||||
{AMD_ID_F033C, FLASH_AM033},
|
||||
{AMD_ID_F065D, FLASH_AM065},
|
||||
{ATM_ID_LV040, FLASH_AT040},
|
||||
{(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB}
|
||||
};
|
||||
|
||||
const map_entry *p;
|
||||
unsigned long result = FLASH_UNKNOWN;
|
||||
|
||||
/* find chip id */
|
||||
for(p = &chip_map[0]; p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++){
|
||||
if(p->extval == chip){
|
||||
result = FLASH_VENDMASK | p->intval;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* find vendor id */
|
||||
for(p = &mfct_map[0]; p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++){
|
||||
if(p->extval == mfct){
|
||||
result &= ~FLASH_VENDMASK;
|
||||
result |= (unsigned long) p->intval << 16;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
unsigned long flash_init(void)
|
||||
{
|
||||
unsigned long i;
|
||||
unsigned char j;
|
||||
static const ulong flash_banks[] = CFG_FLASH_BANKS;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++){
|
||||
flash_info_t * const pflinfo = &flash_info[i];
|
||||
pflinfo->flash_id = FLASH_UNKNOWN;
|
||||
pflinfo->size = 0;
|
||||
pflinfo->sector_count = 0;
|
||||
}
|
||||
|
||||
/* Enable writes to Hydra/Argus flash */
|
||||
{
|
||||
register unsigned int temp;
|
||||
CONFIG_READ_WORD(PICR1,temp);
|
||||
temp |= PICR1_FLASH_WR_EN;
|
||||
CONFIG_WRITE_WORD(PICR1,temp);
|
||||
}
|
||||
|
||||
for(i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++){
|
||||
flash_info_t * const pflinfo = &flash_info[i];
|
||||
const unsigned long base_address = flash_banks[i];
|
||||
volatile FLASH_WORD_SIZE * const flash = (FLASH_WORD_SIZE *) base_address;
|
||||
|
||||
/* write autoselect sequence */
|
||||
flash[0x5555] = 0xaa;
|
||||
flash[0x2aaa] = 0x55;
|
||||
flash[0x5555] = 0x90;
|
||||
__asm__ __volatile__("sync");
|
||||
|
||||
pflinfo->flash_id = flash_id(flash[0x0], flash[0x1]);
|
||||
|
||||
switch(pflinfo->flash_id & FLASH_TYPEMASK){
|
||||
case FLASH_AM033:
|
||||
pflinfo->size = 0x00200000;
|
||||
pflinfo->sector_count = 64;
|
||||
for(j = 0; j < 64; j++){
|
||||
pflinfo->start[j] = base_address + 0x00010000 * j;
|
||||
pflinfo->protect[j] = flash[(j << 16) | 0x2];
|
||||
}
|
||||
break;
|
||||
case FLASH_AM065:
|
||||
pflinfo->size = 0x00800000;
|
||||
pflinfo->sector_count =128;
|
||||
for(j = 0; j < 128; j++){
|
||||
pflinfo->start[j] = base_address + 0x00010000 * j;
|
||||
pflinfo->protect[j] = flash[(j << 16) | 0x2];
|
||||
}
|
||||
break;
|
||||
case FLASH_AT040:
|
||||
pflinfo->size = 0x00080000;
|
||||
pflinfo->sector_count = 2;
|
||||
pflinfo->start[0] = base_address ;
|
||||
pflinfo->start[1] = base_address + 0x00004000;
|
||||
pflinfo->protect[0] = ((flash[0x02] & 0X01)==0) ? 0X02 : 0X01;
|
||||
pflinfo->protect[1] = 0X02;
|
||||
break;
|
||||
case FLASH_AM040:
|
||||
pflinfo->size = 0x00080000;
|
||||
pflinfo->sector_count = 8;
|
||||
for(j = 0; j < 8; j++){
|
||||
pflinfo->start[j] = base_address + 0x00010000 * j;
|
||||
pflinfo->protect[j] = flash[(j << 16) | 0x2];
|
||||
}
|
||||
break;
|
||||
case FLASH_STM800AB:
|
||||
pflinfo->size = 0x00100000;
|
||||
pflinfo->sector_count = 19;
|
||||
pflinfo->start[0] = base_address;
|
||||
pflinfo->start[1] = base_address + 0x4000;
|
||||
pflinfo->start[2] = base_address + 0x6000;
|
||||
pflinfo->start[3] = base_address + 0x8000;
|
||||
for(j = 1; j < 16; j++){
|
||||
pflinfo->start[j+3] = base_address + 0x00010000 * j;
|
||||
}
|
||||
break;
|
||||
}
|
||||
/* Protect monitor and environment sectors */
|
||||
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CFG_MONITOR_BASE,
|
||||
CFG_MONITOR_BASE + monitor_flash_len - 1,
|
||||
&flash_info[0]);
|
||||
#endif
|
||||
|
||||
#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CFG_ENV_ADDR,
|
||||
CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
|
||||
&flash_info[0]);
|
||||
#endif
|
||||
|
||||
/* reset device to read mode */
|
||||
flash[0x0000] = 0xf0;
|
||||
__asm__ __volatile__("sync");
|
||||
}
|
||||
|
||||
return flash_info[0].size + flash_info[1].size;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
void flash_print_info(flash_info_t *info)
|
||||
{
|
||||
static const char unk[] = "Unknown";
|
||||
const char *mfct = unk, *type = unk;
|
||||
unsigned int i;
|
||||
|
||||
if(info->flash_id != FLASH_UNKNOWN){
|
||||
switch(info->flash_id & FLASH_VENDMASK){
|
||||
case FLASH_MAN_ATM:
|
||||
mfct = "Atmel";
|
||||
break;
|
||||
case FLASH_MAN_AMD:
|
||||
mfct = "AMD";
|
||||
break;
|
||||
case FLASH_MAN_FUJ:
|
||||
mfct = "FUJITSU";
|
||||
break;
|
||||
case FLASH_MAN_STM:
|
||||
mfct = "STM";
|
||||
break;
|
||||
case FLASH_MAN_SST:
|
||||
mfct = "SST";
|
||||
break;
|
||||
case FLASH_MAN_BM:
|
||||
mfct = "Bright Microelectonics";
|
||||
break;
|
||||
case FLASH_MAN_INTEL:
|
||||
mfct = "Intel";
|
||||
break;
|
||||
}
|
||||
|
||||
switch(info->flash_id & FLASH_TYPEMASK){
|
||||
case FLASH_AT040:
|
||||
type = "AT49LV040 (512K * 8, uniform sector size)";
|
||||
break;
|
||||
case FLASH_AM033:
|
||||
type = "AM29F033C (4 Mbit * 8, uniform sector size)";
|
||||
break;
|
||||
case FLASH_AM040:
|
||||
type = "AM29F040B (512K * 8, uniform sector size)";
|
||||
break;
|
||||
case FLASH_AM065:
|
||||
type = "AM29F0465D ( 8 MBit * 8, uniform sector size) or part of AM29F652D( 16 MB)";
|
||||
break;
|
||||
case FLASH_AM400B:
|
||||
type = "AM29LV400B (4 Mbit, bottom boot sect)";
|
||||
break;
|
||||
case FLASH_AM400T:
|
||||
type = "AM29LV400T (4 Mbit, top boot sector)";
|
||||
break;
|
||||
case FLASH_AM800B:
|
||||
type = "AM29LV800B (8 Mbit, bottom boot sect)";
|
||||
break;
|
||||
case FLASH_AM800T:
|
||||
type = "AM29LV800T (8 Mbit, top boot sector)";
|
||||
break;
|
||||
case FLASH_AM160T:
|
||||
type = "AM29LV160T (16 Mbit, top boot sector)";
|
||||
break;
|
||||
case FLASH_AM320B:
|
||||
type = "AM29LV320B (32 Mbit, bottom boot sect)";
|
||||
break;
|
||||
case FLASH_AM320T:
|
||||
type = "AM29LV320T (32 Mbit, top boot sector)";
|
||||
break;
|
||||
case FLASH_STM800AB:
|
||||
type = "M29W800AB (8 Mbit, bottom boot sect)";
|
||||
break;
|
||||
case FLASH_SST800A:
|
||||
type = "SST39LF/VF800 (8 Mbit, uniform sector size)";
|
||||
break;
|
||||
case FLASH_SST160A:
|
||||
type = "SST39LF/VF160 (16 Mbit, uniform sector size)";
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
printf(
|
||||
"\n Brand: %s Type: %s\n"
|
||||
" Size: %lu KB in %d Sectors\n",
|
||||
mfct,
|
||||
type,
|
||||
info->size >> 10,
|
||||
info->sector_count
|
||||
);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
|
||||
for (i = 0; i < info->sector_count; i++){
|
||||
unsigned long size;
|
||||
unsigned int erased;
|
||||
unsigned long * flash = (unsigned long *) info->start[i];
|
||||
|
||||
/*
|
||||
* Check if whole sector is erased
|
||||
*/
|
||||
size =
|
||||
(i != (info->sector_count - 1)) ?
|
||||
(info->start[i + 1] - info->start[i]) >> 2 :
|
||||
(info->start[0] + info->size - info->start[i]) >> 2;
|
||||
|
||||
for(
|
||||
flash = (unsigned long *) info->start[i], erased = 1;
|
||||
(flash != (unsigned long *) info->start[i] + size) && erased;
|
||||
flash++
|
||||
){
|
||||
erased = *flash == ~0x0UL;
|
||||
}
|
||||
|
||||
printf(
|
||||
"%s %08lX %s %s",
|
||||
(i % 5) ? "" : "\n ",
|
||||
info->start[i],
|
||||
erased ? "E" : " ",
|
||||
info->protect[i] ? "RO" : " "
|
||||
);
|
||||
}
|
||||
|
||||
puts("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
int flash_erase(flash_info_t *info, int s_first, int s_last)
|
||||
{
|
||||
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
|
||||
int flag, prot, sect, l_sect;
|
||||
ulong start, now, last;
|
||||
unsigned char sh8b;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
if ((info->flash_id == FLASH_UNKNOWN) ||
|
||||
(info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
|
||||
printf ("Can't erase unknown flash type - aborted\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect=s_first; sect<=s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
l_sect = -1;
|
||||
|
||||
/* Check the ROM CS */
|
||||
if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START)){
|
||||
sh8b = 3;
|
||||
}
|
||||
else{
|
||||
sh8b = 0;
|
||||
}
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
|
||||
addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080;
|
||||
addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect<=s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
addr = (FLASH_WORD_SIZE *)(info->start[0] + (
|
||||
(info->start[sect] - info->start[0]) << sh8b));
|
||||
if (info->flash_id & FLASH_MAN_SST){
|
||||
addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
|
||||
addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080;
|
||||
addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
|
||||
addr[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
|
||||
udelay(30000); /* wait 30 ms */
|
||||
}
|
||||
else
|
||||
addr[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
|
||||
l_sect = sect;
|
||||
}
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag){
|
||||
enable_interrupts();
|
||||
}
|
||||
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay (1000);
|
||||
|
||||
/*
|
||||
* We wait for the last triggered sector
|
||||
*/
|
||||
if (l_sect < 0){
|
||||
goto DONE;
|
||||
}
|
||||
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
addr = (FLASH_WORD_SIZE *)(info->start[0] + (
|
||||
(info->start[l_sect] - info->start[0]) << sh8b));
|
||||
while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
|
||||
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
return 1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
serial_putc ('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
|
||||
DONE:
|
||||
/* reset to read mode */
|
||||
addr = (FLASH_WORD_SIZE *)info->start[0];
|
||||
addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
|
||||
|
||||
printf (" done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong cp, wp, data;
|
||||
int i, l, rc;
|
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - wp) != 0) {
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<l; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
for (; i<4 && cnt>0; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
for (; cnt==0 && i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
while (cnt >= 4) {
|
||||
data = 0;
|
||||
for (i=0; i<4; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
}
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
cnt -= 4;
|
||||
}
|
||||
|
||||
if (cnt == 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
}
|
||||
for (; i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
return (write_word(info, wp, data));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word (flash_info_t *info, ulong dest, ulong data)
|
||||
{
|
||||
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)info->start[0];
|
||||
volatile FLASH_WORD_SIZE *dest2;
|
||||
volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
|
||||
ulong start;
|
||||
int flag;
|
||||
int i;
|
||||
unsigned char sh8b;
|
||||
|
||||
/* Check the ROM CS */
|
||||
if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START)){
|
||||
sh8b = 3;
|
||||
}
|
||||
else{
|
||||
sh8b = 0;
|
||||
}
|
||||
|
||||
dest2 = (FLASH_WORD_SIZE *)(((dest - info->start[0]) << sh8b) +
|
||||
info->start[0]);
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*dest2 & (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
|
||||
return (2);
|
||||
}
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++){
|
||||
addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
|
||||
addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00A000A0;
|
||||
|
||||
dest2[i << sh8b] = data2[i];
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag){
|
||||
enable_interrupts();
|
||||
}
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while ((dest2[i << sh8b] & (FLASH_WORD_SIZE)0x00800080) !=
|
||||
(data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
|
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------- */
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
/********************************************************************
|
||||
*
|
||||
* Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
|
||||
*
|
||||
* $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/speed.h,v $
|
||||
* $Revision: 1.2 $
|
||||
* $Author: mleeman $
|
||||
* $Date: 2005/02/21 12:48:58 $
|
||||
*
|
||||
* Last ChangeLog Entry
|
||||
* $Log: speed.h,v $
|
||||
* Revision 1.2 2005/02/21 12:48:58 mleeman
|
||||
* update of copyright years (feedback wd)
|
||||
*
|
||||
* Revision 1.1 2005/02/14 09:23:46 mleeman
|
||||
* - moved 'barcohydra' directory to a more generic barco; since we will be
|
||||
* supporting and adding multiple boards
|
||||
*
|
||||
* Revision 1.2 2005/02/09 12:56:23 mleeman
|
||||
* add generic header to track changes in sources
|
||||
*
|
||||
*
|
||||
*******************************************************************/
|
||||
|
||||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Timer value for timer 2, ICLK = 10
|
||||
*
|
||||
* SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1))
|
||||
* SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
|
||||
*
|
||||
* SPEED_FCOUNT2 timer 2 counting frequency
|
||||
* GCLK CPU clock
|
||||
* SPEED_TMR2_PS prescaler
|
||||
*/
|
||||
#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Timer value for PIT
|
||||
*
|
||||
* PIT_TIME = SPEED_PITC / PITRTCLK
|
||||
* PITRTCLK = 8192
|
||||
*/
|
||||
#define SPEED_PITC (82 << 16) /* start counting from 82 */
|
||||
|
||||
/*
|
||||
* The new value for PTA is calculated from
|
||||
*
|
||||
* PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
|
||||
*
|
||||
* gclk CPU clock (not bus clock !)
|
||||
* Trefresh Refresh cycle * 4 (four word bursts used)
|
||||
* DFBRG For normal mode (no clock reduction) always 0
|
||||
* PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
|
||||
* NCS Number of SDRAM banks (chip selects) on this UPM.
|
||||
*/
|
||||
|
|
@ -0,0 +1,130 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
cpu/mpc824x/start.o (.text)
|
||||
lib_ppc/board.o (.text)
|
||||
lib_ppc/ppcstring.o (.text)
|
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .;
|
||||
common/environment.o (.text)
|
||||
|
||||
*(.text)
|
||||
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
. = ALIGN(16);
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(4096);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -0,0 +1,364 @@
|
|||
/********************************************************************
|
||||
*
|
||||
* Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
|
||||
*
|
||||
* $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/include/configs/barco.h,v $
|
||||
* $Revision: 1.2 $
|
||||
* $Author: mleeman $
|
||||
* $Date: 2005/02/21 12:48:58 $
|
||||
*
|
||||
* Last ChangeLog Entry
|
||||
* $Log: barco.h,v $
|
||||
* Revision 1.2 2005/02/21 12:48:58 mleeman
|
||||
* update of copyright years (feedback wd)
|
||||
*
|
||||
* Revision 1.1 2005/02/14 09:29:25 mleeman
|
||||
* moved barcohydra.h to barco.h
|
||||
*
|
||||
* Revision 1.4 2005/02/09 12:56:23 mleeman
|
||||
* add generic header to track changes in sources
|
||||
*
|
||||
*
|
||||
*******************************************************************/
|
||||
|
||||
/*
|
||||
* (C) Copyright 2001, 2002
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC824X 1
|
||||
#define CONFIG_MPC8245 1
|
||||
#define CONFIG_BARCOBCD_STREAMING 1
|
||||
|
||||
#undef USE_DINK32
|
||||
|
||||
#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */
|
||||
#define CONFIG_BAUDRATE 9600
|
||||
#define CONFIG_DRAM_SPEED 100 /* MHz */
|
||||
|
||||
#define CONFIG_BOOTARGS "mem=32M"
|
||||
|
||||
/* Add support for a few extra bootp options like:
|
||||
* - File size
|
||||
* - DNS
|
||||
*/
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
|
||||
CONFIG_BOOTP_BOOTFILESIZE | \
|
||||
CONFIG_BOOTP_DNS)
|
||||
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_PCI )
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#define CONFIG_HUSH_PARSER 1 /* use "hush" command parser */
|
||||
#define CONFIG_BOOTDELAY 1
|
||||
#define CONFIG_BOOTCOMMAND "boot_default"
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP 1 /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CFG_LOAD_ADDR 0x00100000 /* default load address */
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#undef CONFIG_PCI_PNP
|
||||
#undef CFG_CMD_NET
|
||||
|
||||
#define PCI_ENET0_IOADDR 0x80000000
|
||||
#define PCI_ENET0_MEMADDR 0x80000000
|
||||
#define PCI_ENET1_IOADDR 0x81000000
|
||||
#define PCI_ENET1_MEMADDR 0x81000000
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_MAX_RAM_SIZE 0x02000000
|
||||
|
||||
#define CONFIG_LOGBUFFER
|
||||
#ifdef CONFIG_LOGBUFFER
|
||||
#define CFG_STDOUT_ADDR 0x1FFC000
|
||||
#else
|
||||
#define CFG_STDOUT_ADDR 0x2B9000
|
||||
#endif
|
||||
|
||||
#define CFG_RESET_ADDRESS 0xFFF00100
|
||||
|
||||
#if defined (USE_DINK32)
|
||||
#define CFG_MONITOR_LEN 0x00030000
|
||||
#define CFG_MONITOR_BASE 0x00090000
|
||||
#define CFG_RAMBOOT 1
|
||||
#define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
|
||||
#define CFG_INIT_RAM_END 0x10000
|
||||
#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
#else
|
||||
#undef CFG_RAMBOOT
|
||||
#define CFG_MONITOR_LEN 0x00030000
|
||||
#define CFG_MONITOR_BASE TEXT_BASE
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128
|
||||
|
||||
#define CFG_INIT_RAM_ADDR 0x40000000
|
||||
#define CFG_INIT_RAM_END 0x1000
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
|
||||
#endif
|
||||
|
||||
#define CFG_FLASH_BASE 0xFFF00000
|
||||
#define CFG_FLASH_SIZE (8 * 1024 * 1024) /* Unity has onboard 1MByte flash */
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_OFFSET 0x000047A4 /* Offset of Environment Sector */
|
||||
#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
|
||||
#define ENV_CRC 0x8BF6F24B
|
||||
|
||||
#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
|
||||
|
||||
#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
|
||||
|
||||
#define CFG_EUMB_ADDR 0xFDF00000
|
||||
|
||||
#define CFG_FLASH_RANGE_BASE 0xFFC00000 /* flash memory address range */
|
||||
#define CFG_FLASH_RANGE_SIZE 0x00400000
|
||||
#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */
|
||||
#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */
|
||||
|
||||
/*
|
||||
* select i2c support configuration
|
||||
*
|
||||
* Supported configurations are {none, software, hardware} drivers.
|
||||
* If the software driver is chosen, there are some additional
|
||||
* configuration items that the driver uses to drive the port pins.
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
|
||||
#ifdef CONFIG_SOFT_I2C
|
||||
#error "Soft I2C is not configured properly. Please review!"
|
||||
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
|
||||
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
|
||||
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
|
||||
#define I2C_READ ((iop->pdat & 0x00010000) != 0)
|
||||
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
|
||||
else iop->pdat &= ~0x00010000
|
||||
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
|
||||
else iop->pdat &= ~0x00020000
|
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
|
||||
#endif /* CONFIG_SOFT_I2C */
|
||||
|
||||
#define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
|
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
|
||||
#define CFG_DBUS_SIZE2 1
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* NS16550 Configuration (internal DUART)
|
||||
*/
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
|
||||
|
||||
#define CFG_ROMNAL 0x0F /*rom/flash next access time */
|
||||
#define CFG_ROMFAL 0x1E /*rom/flash access time */
|
||||
|
||||
#define CFG_REFINT 0x8F /* no of clock cycles between CBR refresh cycles */
|
||||
|
||||
/* the following are for SDRAM only*/
|
||||
#define CFG_BSTOPRE 0x25C /* Burst To Precharge, sets open page interval */
|
||||
#define CFG_REFREC 8 /* Refresh to activate interval */
|
||||
#define CFG_RDLAT 4 /* data latency from read command */
|
||||
#define CFG_PRETOACT 3 /* Precharge to activate interval */
|
||||
#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
|
||||
#define CFG_ACTORW 2 /* Activate to R/W */
|
||||
#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
|
||||
#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
|
||||
|
||||
#define CFG_REGISTERD_TYPE_BUFFER 1
|
||||
#define CFG_EXTROM 0
|
||||
#define CFG_REGDIMM 0
|
||||
|
||||
|
||||
/* memory bank settings*/
|
||||
/*
|
||||
* only bits 20-29 are actually used from these vales to set the
|
||||
* start/end address the upper two bits will be 0, and the lower 20
|
||||
* bits will be set to 0x00000 for a start address, or 0xfffff for an
|
||||
* end address
|
||||
*/
|
||||
#define CFG_BANK0_START 0x00000000
|
||||
#define CFG_BANK0_END 0x01FFFFFF
|
||||
#define CFG_BANK0_ENABLE 1
|
||||
#define CFG_BANK1_START 0x02000000
|
||||
#define CFG_BANK1_END 0x02ffffff
|
||||
#define CFG_BANK1_ENABLE 0
|
||||
#define CFG_BANK2_START 0x03f00000
|
||||
#define CFG_BANK2_END 0x03ffffff
|
||||
#define CFG_BANK2_ENABLE 0
|
||||
#define CFG_BANK3_START 0x04000000
|
||||
#define CFG_BANK3_END 0x04ffffff
|
||||
#define CFG_BANK3_ENABLE 0
|
||||
#define CFG_BANK4_START 0x05000000
|
||||
#define CFG_BANK4_END 0x05FFFFFF
|
||||
#define CFG_BANK4_ENABLE 0
|
||||
#define CFG_BANK5_START 0x06000000
|
||||
#define CFG_BANK5_END 0x06FFFFFF
|
||||
#define CFG_BANK5_ENABLE 0
|
||||
#define CFG_BANK6_START 0x07000000
|
||||
#define CFG_BANK6_END 0x07FFFFFF
|
||||
#define CFG_BANK6_ENABLE 0
|
||||
#define CFG_BANK7_START 0x08000000
|
||||
#define CFG_BANK7_END 0x08FFFFFF
|
||||
#define CFG_BANK7_ENABLE 0
|
||||
/*
|
||||
* Memory bank enable bitmask, specifying which of the banks defined above
|
||||
are actually present. MSB is for bank #7, LSB is for bank #0.
|
||||
*/
|
||||
#define CFG_BANK_ENABLE 0x01
|
||||
|
||||
#define CFG_ODCR 0xff /* configures line driver impedances, */
|
||||
/* see 8240 book for bit definitions */
|
||||
#define CFG_PGMAX 0x32 /* how long the 8240 retains the */
|
||||
/* currently accessed page in memory */
|
||||
/* see 8240 book for details */
|
||||
|
||||
/* SDRAM 0 - 256MB */
|
||||
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
/* stack in DCACHE @ 1GB (no backing mem) */
|
||||
#if defined(USE_DINK32)
|
||||
#define CFG_IBAT1L (0x40000000 | BATL_PP_00 )
|
||||
#define CFG_IBAT1U (0x40000000 | BATU_BL_128K )
|
||||
#else
|
||||
#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
|
||||
#endif
|
||||
|
||||
/* PCI memory */
|
||||
#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
|
||||
#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
/* Flash, config addrs, etc */
|
||||
#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
|
||||
#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
#define CFG_DBAT0L CFG_IBAT0L
|
||||
#define CFG_DBAT0U CFG_IBAT0U
|
||||
#define CFG_DBAT1L CFG_IBAT1L
|
||||
#define CFG_DBAT1U CFG_IBAT1U
|
||||
#define CFG_DBAT2L CFG_IBAT2L
|
||||
#define CFG_DBAT2U CFG_IBAT2U
|
||||
#define CFG_DBAT3L CFG_IBAT3L
|
||||
#define CFG_DBAT3U CFG_IBAT3U
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 20 /* max number of sectors on one chip */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CFG_FLASH_CHECKSUM
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
/* values according to the manual */
|
||||
|
||||
#define CONFIG_DRAM_50MHZ 1
|
||||
#define CONFIG_SDRAM_50MHZ
|
||||
|
||||
#define CONFIG_DISK_SPINUP_TIME 1000000
|
||||
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2004
|
||||
* (C) Copyright 2000-2005
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
|
|
@ -128,7 +128,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
|
|||
#define MX_MANUFACT 0x00C200C2 /* MXIC manuf. ID in D23..D16, D7..D0 */
|
||||
#define TOSH_MANUFACT 0x00980098 /* TOSHIBA manuf. ID in D23..D16, D7..D0 */
|
||||
#define MT2_MANUFACT 0x002C002C /* alternate MICRON manufacturer ID*/
|
||||
#define EXCEL_MANUFACT 0x004A004A /* Excel Semiconductor */
|
||||
#define EXCEL_MANUFACT 0x004A004A /* Excel Semiconductor */
|
||||
|
||||
/* Micron Technologies (INTEL compat.) */
|
||||
#define MT_ID_28F400_T 0x44704470 /* 28F400B3 ID ( 4 M, top boot sector) */
|
||||
|
|
@ -137,7 +137,15 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
|
|||
#define AMD_ID_LV040B 0x4F /* 29LV040B ID */
|
||||
/* 4 Mbit, 512K x 8, */
|
||||
/* 8 64K x 8 uniform sectors */
|
||||
|
||||
#define AMD_ID_F033C 0xA3 /* 29LV033C ID */
|
||||
/* 32 Mbit, 4Mbits x 8, */
|
||||
/* 64 64K x 8 uniform sectors */
|
||||
#define AMD_ID_F065D 0x93 /* 29LV065D ID */
|
||||
/* 64 Mbit, 8Mbits x 8, */
|
||||
/* 126 64K x 8 uniform sectors */
|
||||
#define ATM_ID_LV040 0x13 /* 29LV040B ID */
|
||||
/* 4 Mbit, 512K x 8, */
|
||||
/* 8 64K x 8 uniform sectors */
|
||||
#define AMD_ID_F040B 0xA4 /* 29F040B ID */
|
||||
/* 4 Mbit, 512K x 8, */
|
||||
/* 8 64K x 8 uniform sectors */
|
||||
|
|
@ -150,10 +158,10 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
|
|||
#define AMD_ID_F016D 0xAD /* 29F016 ID ( 2 M x 8) */
|
||||
#define AMD_ID_F032B 0x41 /* 29F032 ID ( 4 M x 8) */
|
||||
#define AMD_ID_LV116DT 0xC7 /* 29LV116DT ( 2 M x 8, top boot sect) */
|
||||
#define AMD_ID_LV116DB 0x4C /* 29LV116DB ( 2 M x 8, bottom boot sect) */
|
||||
#define AMD_ID_LV116DB 0x4C /* 29LV116DB ( 2 M x 8, bottom boot sect) */
|
||||
#define AMD_ID_LV016B 0xc8 /* 29LV016 ID ( 2 M x 8) */
|
||||
|
||||
#define AMD_ID_PL160CB 0x22452245 /* 29PL160CB ID (16 M, bottom boot sect */
|
||||
#define AMD_ID_PL160CB 0x22452245 /* 29PL160CB ID (16 M, bottom boot sect */
|
||||
|
||||
#define AMD_ID_LV400T 0x22B922B9 /* 29LV400T ID ( 4 M, top boot sector) */
|
||||
#define AMD_ID_LV400B 0x22BA22BA /* 29LV400B ID ( 4 M, bottom boot sect) */
|
||||
|
|
@ -168,7 +176,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
|
|||
#define AMD_ID_LV160B 0x22492249 /* 29LV160B ID (16 M, bottom boot sect) */
|
||||
|
||||
#define AMD_ID_DL163T 0x22282228 /* 29DL163T ID (16 M, top boot sector) */
|
||||
#define AMD_ID_DL163B 0x222B222B /* 29DL163B ID (16 M, bottom boot sect) */
|
||||
#define AMD_ID_DL163B 0x222B222B /* 29DL163B ID (16 M, bottom boot sect) */
|
||||
|
||||
#define AMD_ID_LV320T 0x22F622F6 /* 29LV320T ID (32 M, top boot sector) */
|
||||
#define MX_ID_LV320T 0x22A722A7 /* 29LV320T by Macronix, AMD compatible */
|
||||
|
|
@ -184,10 +192,10 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
|
|||
|
||||
#define AMD_ID_DL640 0x227E227E /* 29DL640D ID (64 M, dual boot sectors)*/
|
||||
#define AMD_ID_MIRROR 0x227E227E /* 1st ID word for MirrorBit family */
|
||||
#define AMD_ID_DL640G_2 0x22022202 /* 2nd ID word for AM29DL640G at 0x38 */
|
||||
#define AMD_ID_DL640G_3 0x22012201 /* 3rd ID word for AM29DL640G at 0x3c */
|
||||
#define AMD_ID_LV640U_2 0x220C220C /* 2nd ID word for AM29LV640M at 0x38 */
|
||||
#define AMD_ID_LV640U_3 0x22012201 /* 3rd ID word for AM29LV640M at 0x3c */
|
||||
#define AMD_ID_DL640G_2 0x22022202 /* 2nd ID word for AM29DL640G at 0x38 */
|
||||
#define AMD_ID_DL640G_3 0x22012201 /* 3rd ID word for AM29DL640G at 0x3c */
|
||||
#define AMD_ID_LV640U_2 0x220C220C /* 2nd ID word for AM29LV640M at 0x38 */
|
||||
#define AMD_ID_LV640U_3 0x22012201 /* 3rd ID word for AM29LV640M at 0x3c */
|
||||
#define AMD_ID_LV640MT_2 0x22102210 /* 2nd ID word for AM29LV640MT at 0x38 */
|
||||
#define AMD_ID_LV640MT_3 0x22012201 /* 3rd ID word for AM29LV640MT at 0x3c */
|
||||
#define AMD_ID_LV640MB_2 0x22102210 /* 2nd ID word for AM29LV640MB at 0x38 */
|
||||
|
|
@ -199,10 +207,11 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
|
|||
#define AMD_ID_GL064M_2 0x22132213 /* 2nd ID word for S29GL064M-R6 */
|
||||
#define AMD_ID_GL064M_3 0x22012201 /* 3rd ID word for S29GL064M-R6 */
|
||||
|
||||
#define AMD_ID_LV320B_2 0x221A221A /* 2d ID word for AM29LV320MB at 0x38 */
|
||||
#define AMD_ID_LV320B_2 0x221A221A /* 2d ID word for AM29LV320MB at 0x38 */
|
||||
#define AMD_ID_LV320B_3 0x22002200 /* 3d ID word for AM29LV320MB at 0x3c */
|
||||
|
||||
#define AMD_ID_LV640U 0x22D722D7 /* 29LV640U ID (64 M, uniform sectors) */
|
||||
#define AMD_ID_LV650U 0x22D722D7 /* 29LV650U ID (64 M, uniform sectors) */
|
||||
|
||||
#define ATM_ID_BV1614 0x000000C0 /* 49BV1614 ID */
|
||||
#define ATM_ID_BV1614A 0x000000C8 /* 49BV1614A ID */
|
||||
|
|
@ -309,13 +318,13 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
|
|||
#define FLASH_AMDL324T 0x0014 /* AMD AM29DL324 */
|
||||
#define FLASH_AMDL324B 0x0015
|
||||
|
||||
#define FLASH_AMDLV033C 0x0018
|
||||
#define FLASH_AMDLV065D 0x001A
|
||||
#define FLASH_AMDLV033C 0x0018
|
||||
#define FLASH_AMDLV065D 0x001A
|
||||
|
||||
#define FLASH_AMDL640 0x0016 /* AMD AM29DL640D */
|
||||
#define FLASH_AMD016 0x0018 /* AMD AM29F016D */
|
||||
#define FLASH_AMDL640MB 0x0019 /* AMD AM29LV640MB (64M, bottom boot sect)*/
|
||||
#define FLASH_AMDL640MT 0x001A /* AMD AM29LV640MT (64M, top boot sect) */
|
||||
#define FLASH_AMDL640MB 0x0019 /* AMD AM29LV640MB (64M, bottom boot sect)*/
|
||||
#define FLASH_AMDL640MT 0x001A /* AMD AM29LV640MT (64M, top boot sect) */
|
||||
|
||||
#define FLASH_SST200A 0x0040 /* SST 39xF200A ID ( 2M = 128K x 16 ) */
|
||||
#define FLASH_SST400A 0x0042 /* SST 39xF400A ID ( 4M = 256K x 16 ) */
|
||||
|
|
@ -355,6 +364,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
|
|||
#define FLASH_AM033C 0x0091 /* AMD AM29LV033 ( 32M = 4M x 8 ) */
|
||||
#define FLASH_LH28F016SCT 0x0092 /* Sharp 28F016SCT ( 8 Meg Flash SIMM ) */
|
||||
#define FLASH_28F160F3B 0x0093 /* Intel 28F160F3B ( 16M = 1M x 16 ) */
|
||||
#define FLASH_AM065D 0x0093
|
||||
|
||||
#define FLASH_28F640J5 0x0099 /* INTEL 28F640J5 ( 64M = 128K x 64) */
|
||||
|
||||
|
|
@ -366,27 +376,32 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
|
|||
#define FLASH_28F320C3B 0x009F /* Intel 28F320C3B ( 32M = 2M x 16 ) */
|
||||
#define FLASH_28F640C3T 0x00A0 /* Intel 28F640C3T ( 64M = 4M x 16 ) */
|
||||
#define FLASH_28F640C3B 0x00A1 /* Intel 28F640C3B ( 64M = 4M x 16 ) */
|
||||
#define FLASH_AMLV320U 0x00A2 /* AMD 29LV320M ( 32M = 2M x 16 ) */
|
||||
#define FLASH_AMLV640U 0x00A4 /* AMD 29LV640M ( 64M = 4M x 16 ) */
|
||||
#define FLASH_AMLV320U 0x00A2 /* AMD 29LV320M ( 32M = 2M x 16 ) */
|
||||
|
||||
#define FLASH_AM033 0x00A3 /* AMD AmL033C90V1 (32M = 4M x 8) */
|
||||
#define FLASH_AM065 0x0093 /* AMD AmL065DU12RI (64M = 8M x 8) */
|
||||
#define FLASH_AT040 0x00A5 /* Amtel AT49LV040 (4M = 512K x 8) */
|
||||
|
||||
#define FLASH_AMLV640U 0x00A4 /* AMD 29LV640M ( 64M = 4M x 16 ) */
|
||||
#define FLASH_AMLV128U 0x00A6 /* AMD 29LV128M ( 128M = 8M x 16 ) */
|
||||
#define FLASH_AMLV320B 0x00A7 /* AMD 29LV320MB ( 32M = 2M x 16 ) */
|
||||
#define FLASH_AMLV320B 0x00A7 /* AMD 29LV320MB ( 32M = 2M x 16 ) */
|
||||
#define FLASH_AMLV320T 0x00A8 /* AMD 29LV320MT ( 32M = 2M x 16 ) */
|
||||
#define FLASH_AMLV256U 0x00AA /* AMD 29LV256M ( 256M = 16M x 16 ) */
|
||||
#define FLASH_MXLV320B 0x00AB /* MX 29LV320MB ( 32M = 2M x 16 ) */
|
||||
#define FLASH_MXLV320B 0x00AB /* MX 29LV320MB ( 32M = 2M x 16 ) */
|
||||
#define FLASH_MXLV320T 0x00AC /* MX 29LV320MT ( 32M = 2M x 16 ) */
|
||||
#define FLASH_28F256L18T 0x00B0 /* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */
|
||||
#define FLASH_AMDL163T 0x00B2 /* AMD AM29DL163T (2M x 16 ) */
|
||||
#define FLASH_AMDL163B 0x00B3
|
||||
#define FLASH_28F64K3 0x00B4 /* Intel 28F64K3 ( 64M) */
|
||||
#define FLASH_28F128K3 0x00B6 /* Intel 28F128K3 ( 128M = 8M x 16 ) */
|
||||
#define FLASH_28F256K3 0x00B8 /* Intel 28F256K3 ( 256M = 16M x 16 ) */
|
||||
#define FLASH_28F128K3 0x00B6 /* Intel 28F128K3 ( 128M = 8M x 16 ) */
|
||||
#define FLASH_28F256K3 0x00B8 /* Intel 28F256K3 ( 256M = 16M x 16 ) */
|
||||
|
||||
#define FLASH_28F320J3A 0x00C0 /* INTEL 28F320J3A ( 32M = 128K x 32) */
|
||||
#define FLASH_28F640J3A 0x00C2 /* INTEL 28F640J3A ( 64M = 128K x 64) */
|
||||
#define FLASH_28F128J3A 0x00C4 /* INTEL 28F128J3A (128M = 128K x 128) */
|
||||
|
||||
#define FLASH_FUJLV650 0x00D0 /* Fujitsu MBM 29LV650UE/651UE */
|
||||
#define FLASH_MT28S4M16LC 0x00E1 /* Micron MT28S4M16LC */
|
||||
#define FLASH_MT28S4M16LC 0x00E1 /* Micron MT28S4M16LC */
|
||||
#define FLASH_S29GL064M 0x00F0 /* Spansion S29GL064M-R6 */
|
||||
|
||||
#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */
|
||||
|
|
@ -400,11 +415,12 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
|
|||
#define FLASH_MAN_MX 0x00030000 /* MXIC */
|
||||
#define FLASH_MAN_STM 0x00040000
|
||||
#define FLASH_MAN_TOSH 0x00050000 /* Toshiba */
|
||||
#define FLASH_MAN_EXCEL 0x00060000 /* Excel Semiconductor */
|
||||
#define FLASH_MAN_EXCEL 0x00060000 /* Excel Semiconductor */
|
||||
#define FLASH_MAN_SST 0x00100000
|
||||
#define FLASH_MAN_INTEL 0x00300000
|
||||
#define FLASH_MAN_MT 0x00400000
|
||||
#define FLASH_MAN_SHARP 0x00500000
|
||||
#define FLASH_MAN_ATM 0x00600000
|
||||
|
||||
|
||||
#define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */
|
||||
|
|
|
|||
Loading…
Reference in New Issue