Merge branch 'for-next/mips'
Conflicts: arch/mips/boards/loongson-ls1b/serial.c
This commit is contained in:
Sascha Hauer
commit
8fb1d4e075
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|
@ -1,2 +1 @@
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|||
obj-y += ram.o
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obj-y += serial.o
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|
|
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@ -1,12 +0,0 @@
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#include <common.h>
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#include <init.h>
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#include <sizes.h>
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#include <asm/memory.h>
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static int mem_init(void)
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{
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mips_add_ram0(SZ_64M);
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return 0;
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}
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mem_initcall(mem_init);
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@ -1,22 +1,10 @@
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#include <common.h>
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#include <init.h>
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#include <ns16550.h>
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#include <mach/loongson1.h>
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static struct NS16550_plat serial_plat = {
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.clock = 83000000,
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.shift = 0,
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};
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static int console_init(void)
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{
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barebox_set_model("Loongson Tech LS1B Demo Board");
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barebox_set_hostname("ls1b");
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add_ns16550_device(DEVICE_ID_DYNAMIC, KSEG1ADDR(LS1X_UART2_BASE),
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8, IORESOURCE_MEM | IORESOURCE_MEM_8BIT, &serial_plat);
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return 0;
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}
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console_initcall(console_init);
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@ -1,3 +1,5 @@
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CONFIG_BUILTIN_DTB=y
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CONFIG_BUILTIN_DTB_NAME="loongson-ls1b"
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CONFIG_MACH_MIPS_LOONGSON=y
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CONFIG_PBL_IMAGE=y
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CONFIG_STACK_SIZE=0x7000
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@ -36,7 +38,11 @@ CONFIG_CMD_IOMEM=y
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CONFIG_FLEXIBLE_BOOTARGS=y
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CONFIG_CMD_RESET=y
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CONFIG_CMD_GO=y
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CONFIG_CMD_OFTREE=y
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CONFIG_CMD_OF_PROPERTY=y
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CONFIG_CMD_OF_NODE=y
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CONFIG_CMD_TIMEOUT=y
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CONFIG_OFDEVICE=y
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# CONFIG_SPI is not set
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CONFIG_ZLIB=y
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CONFIG_BZLIB=y
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|
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@ -14,16 +14,21 @@ CONFIG_CMD_MEMINFO=y
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CONFIG_CMD_IOMEM=y
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CONFIG_CMD_MM=y
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CONFIG_CMD_SHA1SUM=y
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CONFIG_CMD_FLASH=y
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# CONFIG_CMD_BOOTM is not set
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CONFIG_CMD_RESET=y
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CONFIG_CMD_GO=y
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CONFIG_CMD_OFTREE=y
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CONFIG_CMD_OF_PROPERTY=y
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CONFIG_CMD_OF_NODE=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_CLK=y
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CONFIG_OFDEVICE=y
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CONFIG_DRIVER_SERIAL_AR933X=y
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# CONFIG_SPI is not set
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CONFIG_DRIVER_SPI_ATH79=y
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CONFIG_MTD=y
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# CONFIG_MTD_OOB_DEVICE is not set
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CONFIG_MTD_M25P80=y
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CONFIG_MD5=y
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CONFIG_SHA224=y
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CONFIG_SHA256=y
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|
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@ -22,5 +22,11 @@
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reg = <0xb8050000 0x48>;
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#clock-cells = <1>;
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};
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spi: spi@bf000000{
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compatible = "qca,ath79-spi";
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reg = <0xbf000000 0x01000000>;
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status = "disabled";
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};
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};
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};
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@ -0,0 +1,16 @@
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/dts-v1/;
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#include "ls1b.dtsi"
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/ {
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model = "Loongson Tech LS1B Demo Board";
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compatible = "loongson,ls1b";
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memory {
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reg = <0x00000000 0x4000000>;
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};
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};
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&serial2 {
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status = "okay";
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};
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@ -0,0 +1,43 @@
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#include "skeleton.dtsi"
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/ {
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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device_type = "soc";
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ranges;
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serial0: serial@bfe40000 {
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compatible = "ns16550a";
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reg = <0xbfe40000 0x8>;
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reg-shift = <0>;
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clock-frequency = <83000000>;
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status = "disabled";
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};
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serial1: serial@bfe44000 {
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compatible = "ns16550a";
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reg = <0xbfe44000 0x8>;
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reg-shift = <0>;
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clock-frequency = <83000000>;
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status = "disabled";
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};
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serial2: serial@bfe48000 {
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compatible = "ns16550a";
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reg = <0xbfe48000 0x8>;
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reg-shift = <0>;
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clock-frequency = <83000000>;
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status = "disabled";
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};
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serial3: serial@bfe4c000 {
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compatible = "ns16550a";
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reg = <0xbfe4c000 0x8>;
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reg-shift = <0>;
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clock-frequency = <83000000>;
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status = "disabled";
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};
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};
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};
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@ -14,3 +14,23 @@
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&serial0 {
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status = "okay";
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};
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&spi {
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num-chipselects = <1>;
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status = "okay";
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/* Spansion S25FL032PIF SPI flash */
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spiflash: m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "m25p80";
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spi-max-frequency = <104000000>;
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reg = <0>;
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};
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};
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/ {
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aliases {
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spiflash = &spiflash;
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};
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};
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@ -10,6 +10,10 @@ config DRIVER_SPI_ALTERA
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bool "Altera SPI Master driver"
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depends on NIOS2
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config DRIVER_SPI_ATH79
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bool "Atheros AR71XX/AR724X/AR913X/AR933X SPI controller driver"
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depends on MACH_MIPS_ATH79
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config DRIVER_SPI_ATMEL
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bool "Atmel (AT91) SPI Master driver"
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depends on ARCH_AT91
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@ -1,4 +1,5 @@
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obj-$(CONFIG_SPI) += spi.o
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obj-$(CONFIG_DRIVER_SPI_ATH79) += ath79_spi.o
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obj-$(CONFIG_DRIVER_SPI_IMX) += imx_spi.o
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obj-$(CONFIG_DRIVER_SPI_MVEBU) += mvebu_spi.o
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obj-$(CONFIG_DRIVER_SPI_MXS) += mxs_spi.o
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@ -0,0 +1,299 @@
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/*
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* Copyright (C) 2013, 2014 Antony Pavlov <antonynpavlov@gmail.com>
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*
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* This file is part of barebox.
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* See file CREDITS for list of people who contributed to this project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
|
||||
* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
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||||
#include <common.h>
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#include <init.h>
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#include <driver.h>
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#include <spi/spi.h>
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#include <io.h>
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#include <clock.h>
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struct ath79_spi {
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struct spi_master master;
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void __iomem *regs;
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u32 val;
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u32 reg_ctrl;
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};
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#define AR71XX_SPI_REG_FS 0x00 /* Function Select */
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#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */
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#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */
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#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */
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#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
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#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */
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#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */
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#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
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#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0)
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#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1)
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#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2)
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#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \
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AR71XX_SPI_IOC_CS2)
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static inline u32 ath79_spi_rr(struct ath79_spi *sp, int reg)
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{
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return cpu_readl(sp->regs + reg);
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}
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static inline void ath79_spi_wr(struct ath79_spi *sp, u32 val, int reg)
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{
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cpu_writel(val, sp->regs + reg);
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}
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static inline void setbits(struct ath79_spi *sp, int bits, int on)
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{
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/*
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* We are the only user of SCSPTR so no locking is required.
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* Reading bit 2 and 0 in SCSPTR gives pin state as input.
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* Writing the same bits sets the output value.
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* This makes regular read-modify-write difficult so we
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* use sp->val to keep track of the latest register value.
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*/
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if (on)
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sp->val |= bits;
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else
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sp->val &= ~bits;
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ath79_spi_wr(sp, sp->val, AR71XX_SPI_REG_IOC);
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}
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static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
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{
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return container_of(spi->master, struct ath79_spi, master);
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}
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|
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static inline void setsck(struct spi_device *spi, int on)
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{
|
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struct ath79_spi *sc = ath79_spidev_to_sp(spi);
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|
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setbits(sc, AR71XX_SPI_IOC_CLK, on);
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}
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|
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static inline void setmosi(struct spi_device *spi, int on)
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{
|
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struct ath79_spi *sc = ath79_spidev_to_sp(spi);
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|
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setbits(sc, AR71XX_SPI_IOC_DO, on);
|
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}
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|
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static inline u32 getmiso(struct spi_device *spi)
|
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{
|
||||
struct ath79_spi *sc = ath79_spidev_to_sp(spi);
|
||||
|
||||
return !!((ath79_spi_rr(sc, AR71XX_SPI_REG_RDS) & 1));
|
||||
}
|
||||
|
||||
#include "spi-bitbang-txrx.h"
|
||||
|
||||
static inline void ath79_spi_chipselect(struct ath79_spi *sp, int chipselect)
|
||||
{
|
||||
int off_bits;
|
||||
|
||||
off_bits = 0xffffffff;
|
||||
|
||||
switch (chipselect) {
|
||||
case 0:
|
||||
off_bits &= ~AR71XX_SPI_IOC_CS0;
|
||||
break;
|
||||
|
||||
case 1:
|
||||
off_bits &= ~AR71XX_SPI_IOC_CS1;
|
||||
break;
|
||||
|
||||
case 2:
|
||||
off_bits &= ~AR71XX_SPI_IOC_CS2;
|
||||
break;
|
||||
|
||||
case 3:
|
||||
break;
|
||||
}
|
||||
|
||||
/* by default inactivate chip selects */
|
||||
sp->val |= AR71XX_SPI_IOC_CS_ALL;
|
||||
sp->val &= off_bits;
|
||||
|
||||
ath79_spi_wr(sp, sp->val, AR71XX_SPI_REG_IOC);
|
||||
}
|
||||
|
||||
static int ath79_spi_setup(struct spi_device *spi)
|
||||
{
|
||||
struct spi_master *master = spi->master;
|
||||
struct device_d spi_dev = spi->dev;
|
||||
|
||||
if (spi->bits_per_word != 8) {
|
||||
dev_err(master->dev, "master doesn't support %d bits per word requested by %s\n",
|
||||
spi->bits_per_word, spi_dev.name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if ((spi->mode & (SPI_CPHA | SPI_CPOL)) != SPI_MODE_0) {
|
||||
dev_err(master->dev, "master doesn't support SPI_MODE%d requested by %s\n",
|
||||
spi->mode & (SPI_CPHA | SPI_CPOL), spi_dev.name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ath79_spi_read(struct spi_device *spi, void *buf, size_t nbyte)
|
||||
{
|
||||
ssize_t cnt = 0;
|
||||
u8 *rxf_buf = buf;
|
||||
|
||||
while (cnt < nbyte) {
|
||||
*rxf_buf = bitbang_txrx_be_cpha1(spi, 1000, 1, 0, 8);
|
||||
rxf_buf++;
|
||||
cnt++;
|
||||
}
|
||||
|
||||
return cnt;
|
||||
}
|
||||
|
||||
static int ath79_spi_write(struct spi_device *spi,
|
||||
const void *buf, size_t nbyte)
|
||||
{
|
||||
ssize_t cnt = 0;
|
||||
const u8 *txf_buf = buf;
|
||||
|
||||
while (cnt < nbyte) {
|
||||
bitbang_txrx_be_cpha1(spi, 1000, 1, (u32)*txf_buf, 8);
|
||||
txf_buf++;
|
||||
cnt++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ath79_spi_transfer(struct spi_device *spi, struct spi_message *mesg)
|
||||
{
|
||||
struct ath79_spi *sc = ath79_spidev_to_sp(spi);
|
||||
struct spi_transfer *t;
|
||||
|
||||
mesg->actual_length = 0;
|
||||
|
||||
/* activate chip select signal */
|
||||
ath79_spi_chipselect(sc, spi->chip_select);
|
||||
|
||||
list_for_each_entry(t, &mesg->transfers, transfer_list) {
|
||||
|
||||
if (t->tx_buf)
|
||||
ath79_spi_write(spi, t->tx_buf, t->len);
|
||||
|
||||
if (t->rx_buf)
|
||||
ath79_spi_read(spi, t->rx_buf, t->len);
|
||||
|
||||
mesg->actual_length += t->len;
|
||||
}
|
||||
|
||||
/* inactivate chip select signal */
|
||||
ath79_spi_chipselect(sc, -1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ath79_spi_enable(struct ath79_spi *sp)
|
||||
{
|
||||
/* enable GPIO mode */
|
||||
ath79_spi_wr(sp, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
|
||||
|
||||
/* save CTRL register */
|
||||
sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
|
||||
sp->val = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
|
||||
|
||||
/* TODO: setup speed? */
|
||||
ath79_spi_wr(sp, 0x43, AR71XX_SPI_REG_CTRL);
|
||||
}
|
||||
|
||||
static void ath79_spi_disable(struct ath79_spi *sp)
|
||||
{
|
||||
/* restore CTRL register */
|
||||
ath79_spi_wr(sp, sp->reg_ctrl, AR71XX_SPI_REG_CTRL);
|
||||
/* disable GPIO mode */
|
||||
ath79_spi_wr(sp, 0, AR71XX_SPI_REG_FS);
|
||||
}
|
||||
|
||||
static int ath79_spi_probe(struct device_d *dev)
|
||||
{
|
||||
struct spi_master *master;
|
||||
struct ath79_spi *ath79_spi;
|
||||
|
||||
ath79_spi = xzalloc(sizeof(*ath79_spi));
|
||||
dev->priv = ath79_spi;
|
||||
|
||||
master = &ath79_spi->master;
|
||||
master->dev = dev;
|
||||
|
||||
master->bus_num = dev->id;
|
||||
master->setup = ath79_spi_setup;
|
||||
master->transfer = ath79_spi_transfer;
|
||||
master->num_chipselect = 3;
|
||||
|
||||
if (IS_ENABLED(CONFIG_OFDEVICE)) {
|
||||
struct device_node *node = dev->device_node;
|
||||
u32 num_cs;
|
||||
int ret;
|
||||
|
||||
ret = of_property_read_u32(node, "num-chipselects", &num_cs);
|
||||
if (ret)
|
||||
num_cs = 3;
|
||||
|
||||
if (num_cs > 3) {
|
||||
dev_err(dev, "master doesn't support num-chipselects > 3\n");
|
||||
}
|
||||
|
||||
master->num_chipselect = num_cs;
|
||||
}
|
||||
|
||||
ath79_spi->regs = dev_request_mem_region(dev, 0);
|
||||
|
||||
/* enable gpio mode */
|
||||
ath79_spi_enable(ath79_spi);
|
||||
|
||||
/* inactivate chip select signal */
|
||||
ath79_spi_chipselect(ath79_spi, -1);
|
||||
|
||||
spi_register_master(master);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ath79_spi_remove(struct device_d *dev)
|
||||
{
|
||||
struct ath79_spi *sp = dev->priv;
|
||||
|
||||
ath79_spi_disable(sp);
|
||||
}
|
||||
|
||||
static __maybe_unused struct of_device_id ath79_spi_dt_ids[] = {
|
||||
{
|
||||
.compatible = "qca,ath79-spi",
|
||||
},
|
||||
{
|
||||
/* sentinel */
|
||||
}
|
||||
};
|
||||
|
||||
static struct driver_d ath79_spi_driver = {
|
||||
.name = "ath79-spi",
|
||||
.probe = ath79_spi_probe,
|
||||
.remove = ath79_spi_remove,
|
||||
.of_compatible = DRV_OF_COMPAT(ath79_spi_dt_ids),
|
||||
};
|
||||
device_platform_driver(ath79_spi_driver);
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
/*
|
||||
* Mix this utility code with some glue code to get one of several types of
|
||||
* simple SPI master driver. Two do polled word-at-a-time I/O:
|
||||
*
|
||||
* - GPIO/parport bitbangers. Provide chipselect() and txrx_word[](),
|
||||
* expanding the per-word routines from the inline templates below.
|
||||
*
|
||||
* - Drivers for controllers resembling bare shift registers. Provide
|
||||
* chipselect() and txrx_word[](), with custom setup()/cleanup() methods
|
||||
* that use your controller's clock and chipselect registers.
|
||||
*
|
||||
* Some hardware works well with requests at spi_transfer scope:
|
||||
*
|
||||
* - Drivers leveraging smarter hardware, with fifos or DMA; or for half
|
||||
* duplex (MicroWire) controllers. Provide chipselect() and txrx_bufs(),
|
||||
* and custom setup()/cleanup() methods.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code that knows what GPIO pins do what should have declared four
|
||||
* functions, ideally as inlines, before including this header:
|
||||
*
|
||||
* void setsck(struct spi_device *, int is_on);
|
||||
* void setmosi(struct spi_device *, int is_on);
|
||||
* int getmiso(struct spi_device *);
|
||||
* void spidelay(unsigned);
|
||||
*
|
||||
* setsck()'s is_on parameter is a zero/nonzero boolean.
|
||||
*
|
||||
* setmosi()'s is_on parameter is a zero/nonzero boolean.
|
||||
*
|
||||
* getmiso() is required to return 0 or 1 only. Any other value is invalid
|
||||
* and will result in improper operation.
|
||||
*
|
||||
* A non-inlined routine would call bitbang_txrx_*() routines. The
|
||||
* main loop could easily compile down to a handful of instructions,
|
||||
* especially if the delay is a NOP (to run at peak speed).
|
||||
*
|
||||
* Since this is software, the timings may not be exactly what your board's
|
||||
* chips need ... there may be several reasons you'd need to tweak timings
|
||||
* in these routines, not just to make it faster or slower to match a
|
||||
* particular CPU clock rate.
|
||||
*/
|
||||
|
||||
#define spidelay(nsecs) udelay(nsecs/1000)
|
||||
|
||||
static inline u32
|
||||
bitbang_txrx_be_cpha0(struct spi_device *spi,
|
||||
unsigned nsecs, unsigned cpol,
|
||||
u32 word, u8 bits)
|
||||
{
|
||||
/* if (cpol == 0) this is SPI_MODE_0; else this is SPI_MODE_2 */
|
||||
|
||||
/* clock starts at inactive polarity */
|
||||
for (word <<= (32 - bits); likely(bits); bits--) {
|
||||
|
||||
/* setup MSB (to slave) on trailing edge */
|
||||
setmosi(spi, word & (1 << 31));
|
||||
spidelay(nsecs); /* T(setup) */
|
||||
|
||||
setsck(spi, !cpol);
|
||||
spidelay(nsecs);
|
||||
|
||||
/* sample MSB (from slave) on leading edge */
|
||||
word <<= 1;
|
||||
word |= getmiso(spi);
|
||||
setsck(spi, cpol);
|
||||
}
|
||||
return word;
|
||||
}
|
||||
|
||||
static inline u32
|
||||
bitbang_txrx_be_cpha1(struct spi_device *spi,
|
||||
unsigned nsecs, unsigned cpol,
|
||||
u32 word, u8 bits)
|
||||
{
|
||||
/* if (cpol == 0) this is SPI_MODE_1; else this is SPI_MODE_3 */
|
||||
|
||||
/* clock starts at inactive polarity */
|
||||
for (word <<= (32 - bits); likely(bits); bits--) {
|
||||
|
||||
/* setup MSB (to slave) on leading edge */
|
||||
setsck(spi, !cpol);
|
||||
setmosi(spi, word & (1 << 31));
|
||||
spidelay(nsecs); /* T(setup) */
|
||||
|
||||
setsck(spi, cpol);
|
||||
spidelay(nsecs);
|
||||
|
||||
/* sample MSB (from slave) on trailing edge */
|
||||
word <<= 1;
|
||||
word |= getmiso(spi);
|
||||
}
|
||||
return word;
|
||||
}
|
||||
Loading…
Reference in New Issue