Switch MPC86xADS and MPC885ADS boards to use cpuclk environment
variable to set clock Patch by Yuli Barcohen, 05 Jun 2005
This commit is contained in:
Wolfgang Denk
parent
f47b661141
commit
8ff0208d31
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@ -2,6 +2,10 @@
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Changes since U-Boot 1.1.4:
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======================================================================
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* Switch MPC86xADS and MPC885ADS boards to use cpuclk environment
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variable to set clock
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Patch by Yuli Barcohen, 05 Jun 2005
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* RPXlite configuration fixes
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- Use correct flash sector size
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- Use correct memory test end address
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@ -726,24 +726,23 @@ static void checkdboard(void)
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int checkboard (void)
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{
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/* get revision from BCSR 3 */
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#if defined(CONFIG_MPC86xADS)
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puts ("Board: MPC86xADS\n");
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#elif defined(CONFIG_MPC885ADS)
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puts ("Board: MPC885ADS\n");
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#else /* Only old ADS/FADS have got revision ID in BCSR3 */
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uint r = (((*((uint *) BCSR3) >> 23) & 1) << 3)
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| (((*((uint *) BCSR3) >> 19) & 1) << 2)
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| (((*((uint *) BCSR3) >> 16) & 3));
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puts ("Board: ");
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#if defined(CONFIG_MPC86xADS)
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puts ("MPC86xADS");
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#elif defined(CONFIG_MPC885ADS)
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puts ("MPC885ADS");
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r = 0; /* I've got NR (No Revision) board */
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#elif defined(CONFIG_FADS)
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#if defined(CONFIG_FADS)
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puts ("FADS");
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checkdboard ();
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#else
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puts ("ADS");
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#endif
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puts (" rev ");
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switch (r) {
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@ -758,13 +757,9 @@ int checkboard (void)
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puts ("A - warning, read errata \n");
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break;
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case 0x03:
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puts ("B \n");
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puts ("B\n");
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break;
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#elif defined(CONFIG_MPC885ADS)
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case 0x00:
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puts ("NR\n");
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break;
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#else /* FADS and newer */
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#else /* FADS */
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case 0x00:
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puts ("ENG\n");
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break;
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@ -776,6 +771,7 @@ int checkboard (void)
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printf ("unknown (0x%x)\n", r);
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return -1;
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}
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#endif /* CONFIG_MPC86xADS */
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return 0;
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}
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@ -848,7 +844,7 @@ int pcmcia_init(void)
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switch ((pcmp->pcmc_pipr >> 14) & 3)
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#endif
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{
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case 0x00 :
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case 0x03 :
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printf("5V");
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v = 5;
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break;
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@ -860,7 +856,7 @@ int pcmcia_init(void)
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v = 5;
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#endif
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break;
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case 0x03 :
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case 0x00 :
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printf("5V, 3V and x.xV");
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#ifdef CONFIG_FADS
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v = 3; /* User lower voltage if supported! */
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@ -55,18 +55,26 @@
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_NFSBOOTCOMMAND \
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"dhcp;" \
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"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
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"setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
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"bootm"
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#define CONFIG_BOOTCOMMAND \
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"setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
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"bootm fe080000"
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#undef CONFIG_BOOTARGS
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
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/*
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* New MPC86xADS and Duet provide two Ethernet connectivity options:
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* New MPC86xADS and MPC885ADS provide two Ethernet connectivity options:
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* 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
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* motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
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* got FEC so FEC is the default.
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@ -89,7 +97,9 @@
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#ifndef CONFIG_COMMANDS
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
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| CFG_CMD_ASKENV \
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| CFG_CMD_DHCP \
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| CFG_CMD_ECHO \
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| CFG_CMD_IMMAP \
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| CFG_CMD_JFFS2 \
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| CFG_CMD_MII \
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@ -104,16 +114,18 @@
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/*
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* Miscellaneous configurable options
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*/
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#undef CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=>" /* Monitor Command Prompt */
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#define CFG_PROMPT "=>" /* Monitor Command Prompt */
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#define CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#define CFG_LONGHELP /* #undef to save memory */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_LOAD_ADDR 0x00100000
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@ -126,6 +138,7 @@
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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@ -148,6 +161,14 @@
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#define CFG_SDRAM_BASE 0x00000000
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#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
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#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */
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/*
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* 2048 SDRAM rows
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* 1000 factor s -> ms
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* 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
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* 4 Number of refresh cycles per period
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* 64 Refresh cycle in ms per number of rows
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*/
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#define CFG_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64))
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#elif defined(CONFIG_FADS) /* Old/new FADS */
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#define CFG_SDRAM_SIZE 0x00400000 /* 4 Mbyte */
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#else /* Old ADS */
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@ -223,9 +244,7 @@
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* I2C configuration
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@ -277,31 +296,21 @@
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF11
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#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
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#define CFG_SCCR SCCR_TBS
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 14-22
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* DER - Debug Enable Register
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*-----------------------------------------------------------------------
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* set the PLL, the low-power modes and the reset control
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*/
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#ifndef CFG_PLPRCR
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#define CFG_PLPRCR PLPRCR_TEXPS
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#endif
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/*-----------------------------------------------------------------------
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*
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*-----------------------------------------------------------------------
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*
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* Set to zero to prevent the processor from entering debug mode
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*/
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#define CFG_DER 0
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/* Because of the way the 860 starts up and assigns CS0 the
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* entire address space, we have to set the memory controller
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* differently. Normally, you write the option register
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* first, and then enable the chip select by writing the
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* base register. For CS0, you must write the base register
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* first, followed by the option register.
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*/
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/* Because of the way the 860 starts up and assigns CS0 the entire
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* address space, we have to set the memory controller differently.
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* Normally, you write the option register first, and then enable the
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* chip select by writing the base register. For CS0, you must write
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* the base register first, followed by the option register.
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*/
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/*
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* Init Memory Controller:
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@ -335,9 +344,6 @@
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/* values according to the manual */
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#define PCMCIA_MEM_ADDR ((uint)0xFF020000)
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#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
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#define BCSR0 ((uint) (BCSR_ADDR + 0x00))
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#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
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#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
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@ -396,59 +402,28 @@
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#define BCSR4_TFPLDL ((uint)0x40000000)
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#define BCSR4_TPSQEL ((uint)0x20000000)
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#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
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#define BCSR4_FETH_EN ((uint)0x08000000)
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#define BCSR4_FETHCFG0 ((uint)0x04000000)
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#define BCSR4_FETHFDE ((uint)0x02000000)
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#define BCSR4_FETHCFG1 ((uint)0x00400000)
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#define BCSR4_FETHRST ((uint)0x00200000)
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#ifdef CONFIG_MPC823
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#if defined(CONFIG_MPC823)
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#define BCSR4_USB_EN ((uint)0x08000000)
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#endif /* CONFIG_MPC823 */
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#ifdef CONFIG_MPC860SAR
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#define BCSR4_UTOPIA_EN ((uint)0x08000000)
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#endif /* CONFIG_MPC860SAR */
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#ifdef CONFIG_MPC860T
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#define BCSR4_FETH_EN ((uint)0x08000000)
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#endif /* CONFIG_MPC860T */
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#ifdef CONFIG_MPC823
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#define BCSR4_USB_SPEED ((uint)0x04000000)
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#endif /* CONFIG_MPC823 */
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#ifdef CONFIG_MPC860T
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#define BCSR4_FETHCFG0 ((uint)0x04000000)
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#endif /* CONFIG_MPC860T */
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#ifdef CONFIG_MPC823
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#define BCSR4_VCCO ((uint)0x02000000)
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#endif /* CONFIG_MPC823 */
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#ifdef CONFIG_MPC860T
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#define BCSR4_FETHFDE ((uint)0x02000000)
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#endif /* CONFIG_MPC860T */
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#ifdef CONFIG_MPC823
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#define BCSR4_VIDEO_ON ((uint)0x00800000)
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#endif /* CONFIG_MPC823 */
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#ifdef CONFIG_MPC823
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#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
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#endif /* CONFIG_MPC823 */
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#ifdef CONFIG_MPC860T
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#define BCSR4_FETHCFG1 ((uint)0x00400000)
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#endif /* CONFIG_MPC860T */
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#ifdef CONFIG_MPC823
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#define BCSR4_VIDEO_RST ((uint)0x00200000)
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#endif /* CONFIG_MPC823 */
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#ifdef CONFIG_MPC860T
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#define BCSR4_FETHRST ((uint)0x00200000)
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#endif /* CONFIG_MPC860T */
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#ifdef CONFIG_MPC823
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#define BCSR4_MODEM_EN ((uint)0x00100000)
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#endif /* CONFIG_MPC823 */
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#ifdef CONFIG_MPC823
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#define BCSR4_DATA_VOICE ((uint)0x00080000)
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#endif /* CONFIG_MPC823 */
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#ifdef CONFIG_MPC850
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#elif defined(CONFIG_MPC850)
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#define BCSR4_DATA_VOICE ((uint)0x00080000)
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#endif /* CONFIG_MPC850 */
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#elif defined(CONFIG_MPC860SAR)
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#define BCSR4_UTOPIA_EN ((uint)0x08000000)
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#else /* MPC860T and other chips with FEC */
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#define BCSR4_FETH_EN ((uint)0x08000000)
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#define BCSR4_FETHCFG0 ((uint)0x04000000)
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#define BCSR4_FETHFDE ((uint)0x02000000)
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#define BCSR4_FETHCFG1 ((uint)0x00400000)
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#define BCSR4_FETHRST ((uint)0x00200000)
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#endif
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/* BSCR5 exists on MPC86xADS and Duet ADS only */
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/* BSCR5 exists on MPC86xADS and MPC885ADS only */
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#define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000)
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@ -511,4 +486,4 @@
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#define CFG_ATA_ALT_OFFSET 0x0000
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#define CONFIG_DISK_SPINUP_TIME 1000000
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#undef CONFIG_DISK_SPINUP_TIME /* usin´ Compact Flash */
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/* #undef CONFIG_DISK_SPINUP_TIME */ /* usin Compact Flash */
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@ -21,7 +21,7 @@
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#define CONFIG_MPC86xADS 1 /* new ADS */
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#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */
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/* New MPC86xADS - pick one of these */
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/* CPU type - pick one of these */
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#define CONFIG_MPC866T 1
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#undef CONFIG_MPC866P
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#undef CONFIG_MPC859T
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@ -33,7 +33,10 @@
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 38400
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#define CONFIG_8xx_OSCLK 10000000 /* 10MHz oscillator on EXTCLK */
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#define CONFIG_8xx_OSCLK 10000000 /* 10MHz oscillator on EXTCLK */
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#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
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#define CFG_8xx_CPUCLK_MIN 40000000
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#define CFG_8xx_CPUCLK_MAX 80000000
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#define CONFIG_DRAM_50MHZ 1
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#define CONFIG_SDRAM_50MHZ 1
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@ -1,44 +1,34 @@
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/*
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* A collection of structures, addresses, and values associated with
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* the Motorola DUET ADS board. Values common to all FADS family boards
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* the Motorola MPC885ADS board. Values common to all FADS family boards
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* are in board/fads/fads.h
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*
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* Copyright (C) 2003 Arabella Software Ltd.
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* Copyright (C) 2003-2004 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* Board type */
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#define CONFIG_MPC885ADS 1 /* Duet (MPC87x/88x) ADS */
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#define CONFIG_MPC885ADS 1 /* MPC885ADS board */
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#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */
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#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */
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#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 38400
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#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
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#define CFG_PLPRCR ((1 << PLPRCR_MFD_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS)
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#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
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#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
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#define CFG_8xx_CPUCLK_MIN 40000000
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#define CFG_8xx_CPUCLK_MAX 133000000
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#define CONFIG_SDRAM_50MHZ 1
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
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| CFG_CMD_DHCP \
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| CFG_CMD_IMMAP \
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| CFG_CMD_MII \
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| CFG_CMD_PING \
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)
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#include "fads.h"
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#undef CFG_SCCR
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#define CFG_SCCR (SCCR_TBS|SCCR_EBDF11)
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#define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */
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#define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V)
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