tegra: add Tegra3 ramsize detection
Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -39,6 +39,7 @@
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#define T20_ODMDATA_RAMSIZE_SHIFT 28
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#define T20_ODMDATA_RAMSIZE_MASK (3 << T20_ODMDATA_RAMSIZE_SHIFT)
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#define T30_ODMDATA_RAMSIZE_MASK (0xf << T20_ODMDATA_RAMSIZE_SHIFT)
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#define T20_ODMDATA_UARTTYPE_SHIFT 18
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#define T20_ODMDATA_UARTTYPE_MASK (3 << T20_ODMDATA_UARTTYPE_SHIFT)
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#define T20_ODMDATA_UARTID_SHIFT 15
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@ -124,6 +125,26 @@ uint32_t tegra20_get_ramsize(void)
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}
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}
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static __always_inline
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uint32_t tegra30_get_ramsize(void)
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{
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switch ((tegra_get_odmdata() & T30_ODMDATA_RAMSIZE_MASK) >>
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T20_ODMDATA_RAMSIZE_SHIFT) {
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case 0:
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case 1:
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default:
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return SZ_256M;
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case 2:
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return SZ_512M;
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case 3:
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return SZ_512M + SZ_256M;
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case 4:
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return SZ_1G;
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case 8:
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return SZ_2G - SZ_1M;
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}
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}
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static long uart_id_to_base[] = {
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TEGRA_UARTA_BASE,
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TEGRA_UARTB_BASE,
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
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* Copyright (C) 2013-2014 Lucas Stach <l.stach@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -41,6 +41,10 @@ void tegra_maincomplex_entry(void)
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rambase = 0x0;
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ramsize = tegra20_get_ramsize();
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break;
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case TEGRA30:
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rambase = SZ_2G;
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ramsize = tegra30_get_ramsize();
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break;
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default:
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/* If we don't know the chiptype, better bail out */
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unreachable();
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