amba: add pl011
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Andrea GALLO <andrea.gallo@stericsson.com> Cc: Gael SALLES <gael.salles@stericsson.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Jean-Christophe PLAGNIOL-VILLARD
Sascha Hauer
parent
dfcdce8eec
commit
907d7cb909
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@ -18,6 +18,9 @@ config ARM
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select HAVE_CONFIGURABLE_TEXT_BASE
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default y
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config ARM_AMBA
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bool
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menu "System Type"
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choice
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@ -4,6 +4,15 @@ config DRIVER_SERIAL_ARM_DCC
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depends on ARM
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bool "ARM Debug Communications Channel (DCC) serial driver"
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config SERIAL_AMBA_PL011
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bool "ARM AMBA PL011 serial port support"
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depends on ARM_AMBA
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help
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This selects the ARM(R) AMBA(R) PrimeCell PL011 UART. If you have
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an Integrator/PP2, Integrator/CP or Versatile platform, say Y here.
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If unsure, say N.
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config DRIVER_SERIAL_IMX
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depends on ARCH_IMX
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default y
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@ -5,6 +5,7 @@
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# serial_pl010.o
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# serial_xuartlite.o
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obj-$(CONFIG_DRIVER_SERIAL_ARM_DCC) += arm_dcc.o
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obj-$(CONFIG_SERIAL_AMBA_PL011) += amba-pl011.o
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obj-$(CONFIG_DRIVER_SERIAL_IMX) += serial_imx.o
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obj-$(CONFIG_DRIVER_SERIAL_ATMEL) += atmel.o
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obj-$(CONFIG_DRIVER_SERIAL_NETX) += serial_netx.o
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@ -0,0 +1,192 @@
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/*
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* (C) Copyright 2000
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* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
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*
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* (C) Copyright 2004
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* ARM Ltd.
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* Philippe Robin, <philippe.robin@arm.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
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#include <common.h>
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#include <driver.h>
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#include <init.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <linux/amba/serial.h>
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#include <linux/clk.h>
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/*
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* We wrap our port structure around the generic console_device.
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*/
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struct amba_uart_port {
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struct console_device uart; /* uart */
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struct clk *clk; /* uart clock */
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u32 uartclk;
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};
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static inline struct amba_uart_port *
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to_amba_uart_port(struct console_device *uart)
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{
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return container_of(uart, struct amba_uart_port, uart);
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}
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static int pl011_setbaudrate(struct console_device *cdev, int baudrate)
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{
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struct device_d *dev = cdev->dev;
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struct amba_uart_port *uart = to_amba_uart_port(cdev);
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unsigned int temp;
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unsigned int divider;
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unsigned int remainder;
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unsigned int fraction;
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/*
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** Set baud rate
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**
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** IBRD = UART_CLK / (16 * BAUD_RATE)
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** FBRD = ROUND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
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*/
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temp = 16 * baudrate;
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divider = uart->uartclk / temp;
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remainder = uart->uartclk % temp;
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temp = (8 * remainder) / baudrate;
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fraction = (temp >> 1) + (temp & 1);
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writel(divider, dev->map_base + UART011_IBRD);
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writel(fraction, dev->map_base + UART011_FBRD);
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return 0;
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}
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static void pl011_putc(struct console_device *cdev, char c)
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{
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struct device_d *dev = cdev->dev;
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/* Wait until there is space in the FIFO */
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while (readl(dev->map_base + UART01x_FR) & UART01x_FR_TXFF);
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/* Send the character */
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writel(c, dev->map_base + UART01x_DR);
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}
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static int pl011_getc(struct console_device *cdev)
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{
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struct device_d *dev = cdev->dev;
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unsigned int data;
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/* Wait until there is data in the FIFO */
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while (readl(dev->map_base + UART01x_FR) & UART01x_FR_RXFE);
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data = readl(dev->map_base + UART01x_DR);
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/* Check for an error flag */
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if (data & 0xffffff00) {
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/* Clear the error */
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writel(0xffffffff, dev->map_base + UART01x_ECR);
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return -1;
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}
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return (int)data;
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}
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static int pl011_tstc(struct console_device *cdev)
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{
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struct device_d *dev = cdev->dev;
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return !(readl(dev->map_base + UART01x_FR) & UART01x_FR_RXFE);
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}
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int pl011_init_port (struct console_device *cdev)
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{
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struct device_d *dev = cdev->dev;
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struct amba_uart_port *uart = to_amba_uart_port(cdev);
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/*
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** First, disable everything.
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*/
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writel(0x0, dev->map_base + UART011_CR);
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/*
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* Try to enable the clock producer.
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*/
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clk_enable(uart->clk);
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uart->uartclk = clk_get_rate(uart->clk);
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/*
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* set baud rate
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*/
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pl011_setbaudrate(cdev, 115200);
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/*
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** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled.
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*/
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writel((UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN),
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dev->map_base + UART011_LCRH);
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/*
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** Finally, enable the UART
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*/
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writel((UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE),
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dev->map_base + UART011_CR);
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return 0;
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}
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static int pl011_probe(struct device_d *dev)
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{
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struct amba_uart_port *uart;
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struct console_device *cdev;
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uart = malloc(sizeof(struct amba_uart_port));
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uart->clk = clk_get(dev, NULL);
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cdev = &uart->uart;
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dev->type_data = cdev;
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cdev->dev = dev;
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cdev->f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR;
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cdev->tstc = pl011_tstc;
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cdev->putc = pl011_putc;
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cdev->getc = pl011_getc;
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cdev->setbrg = pl011_setbaudrate;
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pl011_init_port(cdev);
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/* Enable UART */
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console_register(cdev);
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return 0;
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}
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static struct driver_d pl011_driver = {
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.name = "uart-pl011",
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.probe = pl011_probe,
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};
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static int pl011_init(void)
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{
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register_driver(&pl011_driver);
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return 0;
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}
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console_initcall(pl011_init);
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@ -0,0 +1,164 @@
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/*
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* linux/include/linux/amba/serial.h
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*
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* Internal header file for AMBA serial ports
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*
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* Copyright (C) ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H
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#define ASM_ARM_HARDWARE_SERIAL_AMBA_H
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/* -------------------------------------------------------------------------------
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* From AMBA UART (PL010) Block Specification
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* -------------------------------------------------------------------------------
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* UART Register Offsets.
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*/
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#define UART01x_DR 0x00 /* Data read or written from the interface. */
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#define UART01x_RSR 0x04 /* Receive status register (Read). */
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#define UART01x_ECR 0x04 /* Error clear register (Write). */
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#define UART010_LCRH 0x08 /* Line control register, high byte. */
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#define UART010_LCRM 0x0C /* Line control register, middle byte. */
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#define UART010_LCRL 0x10 /* Line control register, low byte. */
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#define UART010_CR 0x14 /* Control register. */
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#define UART01x_FR 0x18 /* Flag register (Read only). */
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#define UART010_IIR 0x1C /* Interrupt indentification register (Read). */
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#define UART010_ICR 0x1C /* Interrupt clear register (Write). */
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#define UART01x_ILPR 0x20 /* IrDA low power counter register. */
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#define UART011_IBRD 0x24 /* Integer baud rate divisor register. */
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#define UART011_FBRD 0x28 /* Fractional baud rate divisor register. */
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#define UART011_LCRH 0x2c /* Line control register. */
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#define UART011_CR 0x30 /* Control register. */
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#define UART011_IFLS 0x34 /* Interrupt fifo level select. */
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#define UART011_IMSC 0x38 /* Interrupt mask. */
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#define UART011_RIS 0x3c /* Raw interrupt status. */
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#define UART011_MIS 0x40 /* Masked interrupt status. */
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#define UART011_ICR 0x44 /* Interrupt clear register. */
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#define UART011_DMACR 0x48 /* DMA control register. */
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#define UART011_DR_OE (1 << 11)
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#define UART011_DR_BE (1 << 10)
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#define UART011_DR_PE (1 << 9)
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#define UART011_DR_FE (1 << 8)
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#define UART01x_RSR_OE 0x08
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#define UART01x_RSR_BE 0x04
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#define UART01x_RSR_PE 0x02
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#define UART01x_RSR_FE 0x01
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#define UART011_FR_RI 0x100
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#define UART011_FR_TXFE 0x080
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#define UART011_FR_RXFF 0x040
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#define UART01x_FR_TXFF 0x020
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#define UART01x_FR_RXFE 0x010
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#define UART01x_FR_BUSY 0x008
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#define UART01x_FR_DCD 0x004
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#define UART01x_FR_DSR 0x002
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#define UART01x_FR_CTS 0x001
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#define UART01x_FR_TMSK (UART01x_FR_TXFF + UART01x_FR_BUSY)
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#define UART011_CR_CTSEN 0x8000 /* CTS hardware flow control */
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#define UART011_CR_RTSEN 0x4000 /* RTS hardware flow control */
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#define UART011_CR_OUT2 0x2000 /* OUT2 */
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#define UART011_CR_OUT1 0x1000 /* OUT1 */
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#define UART011_CR_RTS 0x0800 /* RTS */
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#define UART011_CR_DTR 0x0400 /* DTR */
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#define UART011_CR_RXE 0x0200 /* receive enable */
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#define UART011_CR_TXE 0x0100 /* transmit enable */
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#define UART011_CR_LBE 0x0080 /* loopback enable */
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#define UART010_CR_RTIE 0x0040
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#define UART010_CR_TIE 0x0020
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#define UART010_CR_RIE 0x0010
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#define UART010_CR_MSIE 0x0008
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#define UART01x_CR_IIRLP 0x0004 /* SIR low power mode */
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#define UART01x_CR_SIREN 0x0002 /* SIR enable */
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#define UART01x_CR_UARTEN 0x0001 /* UART enable */
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#define UART011_LCRH_SPS 0x80
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#define UART01x_LCRH_WLEN_8 0x60
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#define UART01x_LCRH_WLEN_7 0x40
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#define UART01x_LCRH_WLEN_6 0x20
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#define UART01x_LCRH_WLEN_5 0x00
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#define UART01x_LCRH_FEN 0x10
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#define UART01x_LCRH_STP2 0x08
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#define UART01x_LCRH_EPS 0x04
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#define UART01x_LCRH_PEN 0x02
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#define UART01x_LCRH_BRK 0x01
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#define UART010_IIR_RTIS 0x08
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#define UART010_IIR_TIS 0x04
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#define UART010_IIR_RIS 0x02
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#define UART010_IIR_MIS 0x01
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#define UART011_IFLS_RX1_8 (0 << 3)
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#define UART011_IFLS_RX2_8 (1 << 3)
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#define UART011_IFLS_RX4_8 (2 << 3)
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#define UART011_IFLS_RX6_8 (3 << 3)
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#define UART011_IFLS_RX7_8 (4 << 3)
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#define UART011_IFLS_TX1_8 (0 << 0)
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#define UART011_IFLS_TX2_8 (1 << 0)
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#define UART011_IFLS_TX4_8 (2 << 0)
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#define UART011_IFLS_TX6_8 (3 << 0)
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#define UART011_IFLS_TX7_8 (4 << 0)
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/* special values for ST vendor with deeper fifo */
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#define UART011_IFLS_RX_HALF (5 << 3)
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#define UART011_IFLS_TX_HALF (5 << 0)
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#define UART011_OEIM (1 << 10) /* overrun error interrupt mask */
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#define UART011_BEIM (1 << 9) /* break error interrupt mask */
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#define UART011_PEIM (1 << 8) /* parity error interrupt mask */
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#define UART011_FEIM (1 << 7) /* framing error interrupt mask */
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#define UART011_RTIM (1 << 6) /* receive timeout interrupt mask */
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#define UART011_TXIM (1 << 5) /* transmit interrupt mask */
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#define UART011_RXIM (1 << 4) /* receive interrupt mask */
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#define UART011_DSRMIM (1 << 3) /* DSR interrupt mask */
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#define UART011_DCDMIM (1 << 2) /* DCD interrupt mask */
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#define UART011_CTSMIM (1 << 1) /* CTS interrupt mask */
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#define UART011_RIMIM (1 << 0) /* RI interrupt mask */
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#define UART011_OEIS (1 << 10) /* overrun error interrupt status */
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#define UART011_BEIS (1 << 9) /* break error interrupt status */
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#define UART011_PEIS (1 << 8) /* parity error interrupt status */
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#define UART011_FEIS (1 << 7) /* framing error interrupt status */
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#define UART011_RTIS (1 << 6) /* receive timeout interrupt status */
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#define UART011_TXIS (1 << 5) /* transmit interrupt status */
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#define UART011_RXIS (1 << 4) /* receive interrupt status */
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#define UART011_DSRMIS (1 << 3) /* DSR interrupt status */
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#define UART011_DCDMIS (1 << 2) /* DCD interrupt status */
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#define UART011_CTSMIS (1 << 1) /* CTS interrupt status */
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#define UART011_RIMIS (1 << 0) /* RI interrupt status */
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#define UART011_OEIC (1 << 10) /* overrun error interrupt clear */
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#define UART011_BEIC (1 << 9) /* break error interrupt clear */
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#define UART011_PEIC (1 << 8) /* parity error interrupt clear */
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#define UART011_FEIC (1 << 7) /* framing error interrupt clear */
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#define UART011_RTIC (1 << 6) /* receive timeout interrupt clear */
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#define UART011_TXIC (1 << 5) /* transmit interrupt clear */
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#define UART011_RXIC (1 << 4) /* receive interrupt clear */
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#define UART011_DSRMIC (1 << 3) /* DSR interrupt clear */
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#define UART011_DCDMIC (1 << 2) /* DCD interrupt clear */
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#define UART011_CTSMIC (1 << 1) /* CTS interrupt clear */
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#define UART011_RIMIC (1 << 0) /* RI interrupt clear */
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#define UART011_DMAONERR (1 << 2) /* disable dma on error */
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#define UART011_TXDMAE (1 << 1) /* enable transmit dma */
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#define UART011_RXDMAE (1 << 0) /* enable receive dma */
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#define UART01x_RSR_ANY (UART01x_RSR_OE|UART01x_RSR_BE|UART01x_RSR_PE|UART01x_RSR_FE)
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#define UART01x_FR_MODEM_ANY (UART01x_FR_DCD|UART01x_FR_DSR|UART01x_FR_CTS)
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#endif
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