remove eco920 board support
It has been broken for long time and nobody cared, so remove it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
8f1691d58c
commit
90fc3a6117
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@ -52,7 +52,6 @@ board-$(CONFIG_MACH_A9M2410) := a9m2410
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board-$(CONFIG_MACH_A9M2440) := a9m2440
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board-$(CONFIG_MACH_AT91SAM9260EK) := at91sam9260ek
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board-$(CONFIG_MACH_AT91SAM9263EK) := at91sam9263ek
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board-$(CONFIG_MACH_ECO920) := eco920
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board-$(CONFIG_MACH_EDB9301) := edb93xx
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board-$(CONFIG_MACH_EDB9302) := edb93xx
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board-$(CONFIG_MACH_EDB9302A) := edb93xx
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@ -2,7 +2,6 @@ if ARCH_AT91RM9200
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config ARCH_TEXT_BASE
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hex
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default 0x21e00000 if MACH_ECO920
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config BOARDINFO
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@ -12,13 +11,6 @@ choice
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prompt "AT91RM9200 Board Type"
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config MACH_ECO920
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bool "eco920"
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select HAS_AT91_ETHER
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select HAS_CFI
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help
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Say Y here if you are using the Motorola MX1ADS board
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endchoice
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endif
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@ -1,2 +0,0 @@
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obj-y += eco920.o
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@ -1,134 +0,0 @@
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/*
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* (C) Copyright 2007 Pengutronix
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* Sascha Hauer, <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* ARM asynchronous clock */
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#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
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#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
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/* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */
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#define AT91_SLOW_CLOCK 32768 /* slow clock */
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#define USE_920T_MMU 1
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CFG_USE_MAIN_OSCILLATOR 1
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/* flash */
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#define MC_PUIA_VAL 0x00000000
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#define MC_PUP_VAL 0x00000000
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#define MC_PUER_VAL 0x00000000
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#define MC_ASR_VAL 0x00000000
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#define MC_AASR_VAL 0x00000000
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#define EBI_CFGR_VAL 0x00000000
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#define SMC2_CSR_VAL 0x00003287
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/* clocks */
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#define PLLAR_VAL 0x2026be04
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#define PLLBR_VAL 0x10483e0e
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#define MCKR_VAL 0x00000202
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/* sdram */
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#define PIOC_ASR_VAL 0xffff0000
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#define PIOC_BSR_VAL 0x00000000
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#define PIOC_PDR_VAL 0xffff0000
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#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
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#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
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#define SDRAM 0x20000000 /* address of the SDRAM */
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#define SDRAM1 0x20000080 /* address of the SDRAM */
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#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
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#define SDRC_MR_VAL 0x00000002 /* Precharge All */
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#define SDRC_MR_VAL1 0x00000004 /* refresh */
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#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
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#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
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#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
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#define CONFIG_BAUDRATE 115200
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/*
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* Hardware drivers
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*/
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/* define one of CONFIG_DBGU, CONFIG_USART0 or CONFIG_USART1 to choose console */
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#define CONFIG_DBGU
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_CMDLINE_EDITING 1
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"mtdids=nor0=physmap-flash.0\0" \
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"mtdparts=mtdparts=physmap-flash.0:128k(barebox)ro,128k(env),1536k(kernel),-(jffs2)\0" \
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"bootargs_base=setenv bootargs console=ttyAT0,115200\0" \
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"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
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"bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \
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"bootargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock3 rootfstype=jffs2\0" \
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"bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash; bootm 0x11040000\0" \
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"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x20000000 $(uimage); bootm\0" \
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"autoload=n\0" \
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"uimage=uImage-eco920\0" \
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"jffs2=root-eco920.jffs2\0"
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM 0x20000000
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#define PHYS_SDRAM_SIZE 0x2000000
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#define CFG_MEMTEST_START PHYS_SDRAM
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#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
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#define CONFIG_DRIVER_ETHER
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#define CONFIG_NET_RETRY_COUNT 20
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#define CONFIG_AT91C_USE_RMII
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#define CFG_LOAD_ADDR 0x21000000 /* default load address */
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#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "barebox> " /* Monitor Command Prompt */
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CFG_MAXARGS 32 /* max number of command args */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CLOCK_TICK_RATE AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
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/* AT91C_TC_TIMER_DIV1_CLOCK */
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#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */
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#define CFG_SPLASH 1
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#define CFG_S1D13706FB 1
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#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
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#define CFG_USB_OHCI_SLOT_NAME "at91rm9200"
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#define LITTLEENDIAN
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#define CONFIG_AT91C_PQFP_UHPBUG
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#endif
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@ -1 +0,0 @@
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TEXT_BASE = 0x21f00000
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@ -1,211 +0,0 @@
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/*
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* (C) Copyright 2007 Pengutronix
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* Sascha Hauer, <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mach/AT91RM9200.h>
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#include <at91rm9200_net.h>
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#include <dm9161.h>
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#include <miiphy.h>
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#include <splash.h>
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#include <asm/armlinux.h>
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#include <s1d13706fb.h>
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#include <net.h>
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#include <init.h>
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/*
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* Miscelaneous platform dependent initialisations
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*/
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static struct cfi_platform_data cfi_info = {
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};
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struct device_d cfi_dev = {
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.name = "cfi_flash",
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.map_base = 0x11000000,
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.size = 16 * 1024 * 1024,
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.platform_data = &cfi_info,
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};
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static struct memory_platform_data ram_pdata = {
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.name = "ram0",
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.flags = DEVFS_RDWR,
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};
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struct device_d sdram_dev = {
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.name = "mem",
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.map_base = 0x20000000,
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.size = 32 * 1024 * 1024,
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.platform_data = &ram_pdata,
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};
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static struct device_d at91_ath_dev = {
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.name = "at91_eth",
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};
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static int devices_init (void)
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{
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register_device(&cfi_dev);
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register_device(&sdram_dev);
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register_device(&at91_ath_dev);
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armlinux_set_bootparams((void *)(PHYS_SDRAM + 0x100));
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armlinux_set_architecture(MACH_TYPE_ECO920);
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return 0;
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}
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device_initcall(devices_init);
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static unsigned int phy_is_connected (AT91PS_EMAC p_mac)
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{
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return 1;
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}
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static unsigned char phy_init_bogus (AT91PS_EMAC p_mac)
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{
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unsigned short val;
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int timeout, adr, speed, fullduplex;
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at91rm9200_EmacEnableMDIO (p_mac);
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/* Scan through phy addresses to find a phy */
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for (adr = 0; adr < 16; adr++) {
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at91rm9200_EmacReadPhy(p_mac, PHY_PHYIDR1 | (adr << 5), &val);
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if (val != 0xffff)
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break;
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}
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adr <<= 5;
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val = PHY_BMCR_RESET;
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at91rm9200_EmacWritePhy(p_mac, PHY_BMCR | adr, &val);
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udelay(1000);
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val = 0x01e1; /* ADVERTISE_100FULL | ADVERTISE_100HALF |
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* ADVERTISE_10FULL | ADVERTISE_10HALF |
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* ADVERTISE_CSMA */
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at91rm9200_EmacWritePhy(p_mac, PHY_ANAR | adr, &val);
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at91rm9200_EmacReadPhy(p_mac, PHY_BMCR | adr, &val);
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val |= PHY_BMCR_AUTON | PHY_BMCR_RST_NEG;
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at91rm9200_EmacWritePhy(p_mac, PHY_BMCR | adr, &val);
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timeout = 500;
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do {
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/* at91rm9200_EmacReadPhy() has a udelay(10000)
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* in it, so this should be about 5 deconds
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*/
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if ((timeout--) == 0) {
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printf("Autonegotiation timeout\n");
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goto out;
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}
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at91rm9200_EmacReadPhy(p_mac, PHY_BMSR | adr, &val);
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} while (!(val & PHY_BMSR_LS));
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at91rm9200_EmacReadPhy(p_mac, PHY_ANLPAR | adr, &val);
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if (val & PHY_ANLPAR_100) {
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speed = 100;
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p_mac->EMAC_CFG |= AT91C_EMAC_SPD;
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} else {
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speed = 10;
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p_mac->EMAC_CFG &= ~AT91C_EMAC_SPD;
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}
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if (val & (PHY_ANLPAR_TXFD | PHY_ANLPAR_10FD)) {
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fullduplex = 1;
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p_mac->EMAC_CFG |= AT91C_EMAC_FD;
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} else {
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fullduplex = 0;
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p_mac->EMAC_CFG &= ~AT91C_EMAC_FD;
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}
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printf("running at %d-%sDuplex\n",speed, fullduplex ? "FUll" : "Half");
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out:
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at91rm9200_EmacDisableMDIO (p_mac);
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return 1;
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}
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void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
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{
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p_phyops->Init = phy_init_bogus;
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p_phyops->IsPhyConnected = phy_is_connected;
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/* This is not used anywhere */
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p_phyops->GetLinkSpeed = NULL;
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/* ditto */
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p_phyops->AutoNegotiate = NULL;
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}
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#ifdef CONFIG_DRIVER_VIDEO_S1D13706
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static int efb_init(struct efb_info *efb)
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{
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writeb(GPIO_CONTROL0_GPO, efb->regs + EFB_GPIO_CONTROL1);
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writeb(PCLK_SOURCE_CLKI2, efb->regs + EFB_PCLK_CONF);
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writeb(0x1, efb->regs + 0x26); /* FIXME: display specific, should be set to zero
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* according to datasheet
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*/
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return 0;
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}
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/* Nanya STN Display */
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static struct efb_info efb = {
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.fbd = {
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.xres = 320,
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.yres = 240,
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.bpp = 8,
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.fb = (void*)0x40020000,
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},
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.init = efb_init,
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.regs = (void*)0x40000000,
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.pixclock = 100000,
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.hsync_len = 1,
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.left_margin = 22,
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.right_margin = 1,
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.vsync_len = 1,
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.upper_margin = 0,
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.lower_margin = 1,
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.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
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.panel_type = PANEL_TYPE_STN | PANEL_TYPE_WIDTH_8 |
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PANEL_TYPE_COLOR | PANEL_TYPE_FORMAT_2,
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};
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#endif
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#define SMC_CSR3 0xFFFFFF7C
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int misc_init_r(void)
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{
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/* Initialization of the Static Memory Controller for Chip Select 3 */
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*(volatile unsigned long*)SMC_CSR3 = 0x00002185;
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#ifdef CONFIG_DRIVER_VIDEO_S1D13706
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s1d13706fb_init(&efb);
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#endif
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#ifdef CONFIG_CMD_SPLASH
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splash_set_fb_data(&efb.fbd);
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#endif
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return 0;
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}
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