arm: cpu: add arm64 specific code
This patch adds arm64 specific codes, which are: - exception support - cache support - rework Makefile to support arm64 Signed-off-by: Raphael Poggi <poggi.raph@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Raphael Poggi
Sascha Hauer
parent
e1287b1a8b
commit
928cc6f4ee
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@ -1,7 +1,24 @@
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obj-y += cpu.o
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ifeq ($(CONFIG_CPU_64v8), y)
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obj-$(CONFIG_ARM_EXCEPTIONS) += exceptions_64.o
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obj-$(CONFIG_MMU) += mmu_64.o
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lwl-y += lowlevel_64.o
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else
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obj-$(CONFIG_ARM_EXCEPTIONS) += exceptions.o
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obj-$(CONFIG_MMU) += mmu.o mmu-early.o
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pbl-$(CONFIG_MMU) += mmu-early.o
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lwl-y += lowlevel.o
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endif
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obj-$(CONFIG_ARM_EXCEPTIONS) += interrupts.o
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obj-y += start.o setupc.o entry.o
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obj-y += start.o entry.o
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ifeq ($(CONFIG_CPU_64v8), y)
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obj-y += setupc_64.o
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else
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obj-y += setupc.o
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endif
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#
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# Any variants can be called as start-armxyz.S
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@ -11,7 +28,6 @@ obj-$(CONFIG_CMD_ARM_MMUINFO) += mmuinfo.o
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obj-$(CONFIG_OFDEVICE) += dtb.o
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obj-$(CONFIG_MMU) += mmu.o cache.o mmu-early.o
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pbl-$(CONFIG_MMU) += mmu-early.o
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ifeq ($(CONFIG_MMU),)
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obj-y += no-mmu.o
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endif
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@ -27,6 +43,10 @@ obj-$(CONFIG_CPU_32v7) += cache-armv7.o
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AFLAGS_pbl-cache-armv7.o :=-Wa,-march=armv7-a
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pbl-$(CONFIG_CPU_32v7) += cache-armv7.o
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obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
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AFLAGS_cache-armv8.o :=-Wa,-march=armv8-a
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obj-$(CONFIG_CPU_64v8) += cache-armv8.o
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AFLAGS_pbl-cache-armv8.o :=-Wa,-march=armv8-a
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pbl-$(CONFIG_CPU_64v8) += cache-armv8.o
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pbl-y += setupc.o entry.o
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pbl-$(CONFIG_PBL_SINGLE_IMAGE) += start-pbl.o
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@ -34,5 +54,3 @@ pbl-$(CONFIG_PBL_MULTI_IMAGES) += uncompress.o
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obj-y += common.o cache.o
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pbl-y += common.o cache.o
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lwl-y += lowlevel.o
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@ -0,0 +1,168 @@
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/*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*
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* This file is based on sample code from ARMv8 ARM.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <init.h>
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/*
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* void v8_flush_dcache_level(level)
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*
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* clean and invalidate one level cache.
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*
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* x0: cache level
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* x1: 0 flush & invalidate, 1 invalidate only
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* x2~x9: clobbered
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*/
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.section .text.v8_flush_dcache_level
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ENTRY(v8_flush_dcache_level)
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lsl x12, x0, #1
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msr csselr_el1, x12 /* select cache level */
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isb /* sync change of cssidr_el1 */
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mrs x6, ccsidr_el1 /* read the new cssidr_el1 */
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and x2, x6, #7 /* x2 <- log2(cache line size)-4 */
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add x2, x2, #4 /* x2 <- log2(cache line size) */
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mov x3, #0x3ff
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and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
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clz w5, w3 /* bit position of #ways */
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mov x4, #0x7fff
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and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
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/* x12 <- cache level << 1 */
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/* x2 <- line length offset */
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/* x3 <- number of cache ways - 1 */
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/* x4 <- number of cache sets - 1 */
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/* x5 <- bit position of #ways */
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loop_set:
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mov x6, x3 /* x6 <- working copy of #ways */
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loop_way:
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lsl x7, x6, x5
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orr x9, x12, x7 /* map way and level to cisw value */
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lsl x7, x4, x2
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orr x9, x9, x7 /* map set number to cisw value */
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tbz w1, #0, 1f
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dc isw, x9
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b 2f
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1: dc cisw, x9 /* clean & invalidate by set/way */
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2: subs x6, x6, #1 /* decrement the way */
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b.ge loop_way
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subs x4, x4, #1 /* decrement the set */
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b.ge loop_set
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ret
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ENDPROC(v8_flush_dcache_level)
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/*
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* void v8_flush_dcache_all(int invalidate_only)
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*
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* x0: 0 flush & invalidate, 1 invalidate only
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*
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* clean and invalidate all data cache by SET/WAY.
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*/
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.section .text.v8_dcache_all
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ENTRY(v8_dcache_all)
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mov x1, x0
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dsb sy
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mrs x10, clidr_el1 /* read clidr_el1 */
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lsr x11, x10, #24
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and x11, x11, #0x7 /* x11 <- loc */
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cbz x11, finished /* if loc is 0, exit */
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mov x15, x30
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mov x0, #0 /* start flush at cache level 0 */
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/* x0 <- cache level */
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/* x10 <- clidr_el1 */
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/* x11 <- loc */
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/* x15 <- return address */
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loop_level:
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lsl x12, x0, #1
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add x12, x12, x0 /* x0 <- tripled cache level */
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lsr x12, x10, x12
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and x12, x12, #7 /* x12 <- cache type */
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cmp x12, #2
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b.lt skip /* skip if no cache or icache */
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bl v8_flush_dcache_level /* x1 = 0 flush, 1 invalidate */
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skip:
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add x0, x0, #1 /* increment cache level */
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cmp x11, x0
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b.gt loop_level
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mov x0, #0
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msr csselr_el1, x0 /* restore csselr_el1 */
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dsb sy
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isb
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mov x30, x15
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finished:
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ret
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ENDPROC(v8_dcache_all)
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.section .text.v8_flush_dcache_all
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ENTRY(v8_flush_dcache_all)
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mov x16, x30
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mov x0, #0
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bl v8_dcache_all
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mov x30, x16
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ret
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ENDPROC(v8_flush_dcache_all)
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.section .text.v8_invalidate_dcache_all
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ENTRY(v8_invalidate_dcache_all)
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mov x16, x30
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mov x0, #0x1
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bl v8_dcache_all
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mov x30, x16
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ret
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ENDPROC(v8_invalidate_dcache_all)
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/*
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* void v8_flush_dcache_range(start, end)
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*
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* clean & invalidate data cache in the range
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*
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* x0: start address
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* x1: end address
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*/
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.section .text.v8_flush_dcache_range
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ENTRY(v8_flush_dcache_range)
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mrs x3, ctr_el0
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lsr x3, x3, #16
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and x3, x3, #0xf
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mov x2, #4
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lsl x2, x2, x3 /* cache line size */
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/* x2 <- minimal cache line size in cache system */
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sub x3, x2, #1
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bic x0, x0, x3
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1: dc civac, x0 /* clean & invalidate data or unified cache */
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add x0, x0, x2
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cmp x0, x1
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b.lo 1b
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dsb sy
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ret
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ENDPROC(v8_flush_dcache_range)
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/*
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* void v8_invalidate_icache_all(void)
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*
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* invalidate all tlb entries.
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*/
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.section .text.v8_invalidate_icache_all
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ENTRY(v8_invalidate_icache_all)
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ic ialluis
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isb sy
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ret
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ENDPROC(v8_invalidate_icache_all)
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.section .text.v8_flush_l3_cache
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ENTRY(v8_flush_l3_cache)
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mov x0, #0 /* return status as success */
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ret
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ENDPROC(v8_flush_l3_cache)
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.weak v8_flush_l3_cache
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@ -36,6 +36,7 @@ DEFINE_CPU_FNS(v4)
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DEFINE_CPU_FNS(v5)
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DEFINE_CPU_FNS(v6)
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DEFINE_CPU_FNS(v7)
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DEFINE_CPU_FNS(v8)
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void __dma_clean_range(unsigned long start, unsigned long end)
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{
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@ -100,6 +101,11 @@ int arm_set_cache_functions(void)
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case CPU_ARCH_ARMv7:
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cache_fns = &cache_fns_armv7;
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break;
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#endif
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#ifdef CONFIG_CPU_64v8
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case CPU_ARCH_ARMv8:
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cache_fns = &cache_fns_armv8;
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break;
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#endif
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default:
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while(1);
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@ -137,6 +143,11 @@ void arm_early_mmu_cache_flush(void)
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case CPU_ARCH_ARMv7:
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v7_mmu_cache_flush();
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return;
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#endif
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#ifdef CONFIG_CPU_64v8
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case CPU_ARCH_ARMv8:
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v8_dcache_all();
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return;
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#endif
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}
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}
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@ -146,6 +157,7 @@ void v7_mmu_cache_invalidate(void);
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void arm_early_mmu_cache_invalidate(void)
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{
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switch (arm_early_get_cpu_architecture()) {
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#if __LINUX_ARM_ARCH__ <= 7
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case CPU_ARCH_ARMv4T:
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case CPU_ARCH_ARMv5:
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case CPU_ARCH_ARMv5T:
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@ -158,6 +170,13 @@ void arm_early_mmu_cache_invalidate(void)
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case CPU_ARCH_ARMv7:
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v7_mmu_cache_invalidate();
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return;
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#endif
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#else
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#ifdef CONFIG_CPU_64v8
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case CPU_ARCH_ARMv8:
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v8_invalidate_icache_all();
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return;
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#endif
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#endif
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}
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}
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@ -0,0 +1,127 @@
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/*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <asm/ptrace.h>
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#include <linux/linkage.h>
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/*
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* Enter Exception.
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* This will save the processor state that is ELR/X0~X30
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* to the stack frame.
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*/
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.macro exception_entry
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stp x29, x30, [sp, #-16]!
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stp x27, x28, [sp, #-16]!
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stp x25, x26, [sp, #-16]!
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stp x23, x24, [sp, #-16]!
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stp x21, x22, [sp, #-16]!
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stp x19, x20, [sp, #-16]!
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stp x17, x18, [sp, #-16]!
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stp x15, x16, [sp, #-16]!
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stp x13, x14, [sp, #-16]!
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stp x11, x12, [sp, #-16]!
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stp x9, x10, [sp, #-16]!
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stp x7, x8, [sp, #-16]!
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stp x5, x6, [sp, #-16]!
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stp x3, x4, [sp, #-16]!
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stp x1, x2, [sp, #-16]!
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/* Could be running at EL3/EL2/EL1 */
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mrs x11, CurrentEL
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cmp x11, #0xC /* Check EL3 state */
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b.eq 1f
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cmp x11, #0x8 /* Check EL2 state */
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b.eq 2f
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cmp x11, #0x4 /* Check EL1 state */
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b.eq 3f
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3: mrs x1, esr_el3
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mrs x2, elr_el3
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b 0f
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2: mrs x1, esr_el2
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mrs x2, elr_el2
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b 0f
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1: mrs x1, esr_el1
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mrs x2, elr_el1
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0:
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stp x2, x0, [sp, #-16]!
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mov x0, sp
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.endm
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/*
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* Exception vectors.
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*/
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.align 11
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.globl vectors
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vectors:
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.align 7
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b _do_bad_sync /* Current EL Synchronous Thread */
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.align 7
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b _do_bad_irq /* Current EL IRQ Thread */
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.align 7
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b _do_bad_fiq /* Current EL FIQ Thread */
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.align 7
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b _do_bad_error /* Current EL Error Thread */
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.align 7
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b _do_sync /* Current EL Synchronous Handler */
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.align 7
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b _do_irq /* Current EL IRQ Handler */
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.align 7
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b _do_fiq /* Current EL FIQ Handler */
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.align 7
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b _do_error /* Current EL Error Handler */
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_do_bad_sync:
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exception_entry
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bl do_bad_sync
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_do_bad_irq:
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exception_entry
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bl do_bad_irq
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_do_bad_fiq:
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exception_entry
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bl do_bad_fiq
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_do_bad_error:
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exception_entry
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bl do_bad_error
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_do_sync:
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exception_entry
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bl do_sync
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_do_irq:
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exception_entry
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bl do_irq
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_do_fiq:
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exception_entry
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bl do_fiq
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_do_error:
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exception_entry
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bl do_error
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.section .data
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.align 4
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.global arm_ignore_data_abort
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arm_ignore_data_abort:
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.word 0 /* When != 0 data aborts are ignored */
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.global arm_data_abort_occurred
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arm_data_abort_occurred:
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.word 0 /* set != 0 by the data abort handler */
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abort_stack:
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.space 8
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@ -27,6 +27,8 @@
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#include <asm/ptrace.h>
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#include <asm/unwind.h>
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#if __LINUX_ARM_ARCH__ <= 7
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/**
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* Display current register set content
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* @param[in] regs Guess what
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@ -70,10 +72,13 @@ void show_regs (struct pt_regs *regs)
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unwind_backtrace(regs);
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#endif
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}
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#endif
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static void __noreturn do_exception(struct pt_regs *pt_regs)
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{
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#if __LINUX_ARM_ARCH__ <= 7
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show_regs(pt_regs);
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#endif
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panic("");
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}
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@ -121,6 +126,8 @@ void do_prefetch_abort (struct pt_regs *pt_regs)
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*/
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void do_data_abort (struct pt_regs *pt_regs)
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{
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#if __LINUX_ARM_ARCH__ <= 7
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u32 far;
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asm volatile ("mrc p15, 0, %0, c6, c0, 0" : "=r" (far) : : "cc");
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@ -128,6 +135,7 @@ void do_data_abort (struct pt_regs *pt_regs)
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printf("unable to handle %s at address 0x%08x\n",
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far < PAGE_SIZE ? "NULL pointer dereference" :
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"paging request", far);
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#endif
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do_exception(pt_regs);
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}
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@ -156,6 +164,45 @@ void do_irq (struct pt_regs *pt_regs)
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do_exception(pt_regs);
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}
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#ifdef CONFIG_CPU_64v8
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void do_bad_sync(struct pt_regs *pt_regs)
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{
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printf("bad sync\n");
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do_exception(pt_regs);
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}
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void do_bad_irq(struct pt_regs *pt_regs)
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{
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printf("bad irq\n");
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do_exception(pt_regs);
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}
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void do_bad_fiq(struct pt_regs *pt_regs)
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{
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printf("bad fiq\n");
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do_exception(pt_regs);
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}
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void do_bad_error(struct pt_regs *pt_regs)
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{
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printf("bad error\n");
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do_exception(pt_regs);
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}
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||||
|
||||
void do_sync(struct pt_regs *pt_regs)
|
||||
{
|
||||
printf("sync exception\n");
|
||||
do_exception(pt_regs);
|
||||
}
|
||||
|
||||
|
||||
void do_error(struct pt_regs *pt_regs)
|
||||
{
|
||||
printf("error exception\n");
|
||||
do_exception(pt_regs);
|
||||
}
|
||||
#endif
|
||||
|
||||
extern volatile int arm_ignore_data_abort;
|
||||
extern volatile int arm_data_abort_occurred;
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,40 @@
|
|||
#include <linux/linkage.h>
|
||||
#include <init.h>
|
||||
#include <asm/system.h>
|
||||
|
||||
.section ".text_bare_init_","ax"
|
||||
ENTRY(arm_cpu_lowlevel_init)
|
||||
adr x0, vectors
|
||||
mrs x1, CurrentEL
|
||||
cmp x1, #0xC /* Check EL3 state */
|
||||
b.eq 1f
|
||||
cmp x1, #0x8 /* Check EL2 state */
|
||||
b.eq 2f
|
||||
cmp x1, #0x4 /* Check EL1 state */
|
||||
b.eq 3f
|
||||
|
||||
1:
|
||||
msr vbar_el3, x0
|
||||
mov x0, #1 /* Non-Secure EL0/1 */
|
||||
orr x0, x0, #(1 << 10) /* 64-bit EL2 */
|
||||
msr scr_el3, x0
|
||||
msr cptr_el3, xzr
|
||||
b done
|
||||
|
||||
2:
|
||||
msr vbar_el2, x0
|
||||
mov x0, #0x33ff /* Enable FP/SIMD */
|
||||
msr cptr_el2, x0
|
||||
b done
|
||||
|
||||
|
||||
3:
|
||||
msr vbar_el1, x0
|
||||
mov x0, #(3 << 20) /* Enable FP/SIMD */
|
||||
msr cpacr_el1, x0
|
||||
b done
|
||||
|
||||
done:
|
||||
ret
|
||||
|
||||
ENDPROC(arm_cpu_lowlevel_init)
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
#include <linux/linkage.h>
|
||||
#include <asm/sections.h>
|
||||
|
||||
.section .text.setupc
|
||||
|
||||
/*
|
||||
* setup_c: clear bss
|
||||
*/
|
||||
ENTRY(setup_c)
|
||||
mov x15, x30
|
||||
ldr x0, =__bss_start
|
||||
mov x1, #0
|
||||
ldr x2, =__bss_stop
|
||||
sub x2, x2, x0
|
||||
bl memset /* clear bss */
|
||||
mov x30, x15
|
||||
ret
|
||||
ENDPROC(setup_c)
|
||||
|
|
@ -1,9 +1,18 @@
|
|||
#ifndef __ASM_CACHE_H
|
||||
#define __ASM_CACHE_H
|
||||
|
||||
#ifdef CONFIG_CPU_64v8
|
||||
extern void v8_invalidate_icache_all(void);
|
||||
extern void v8_dcache_all(void);
|
||||
#endif
|
||||
|
||||
static inline void flush_icache(void)
|
||||
{
|
||||
#if __LINUX_ARM_ARCH__ <= 7
|
||||
asm volatile("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
|
||||
#else
|
||||
v8_invalidate_icache_all();
|
||||
#endif
|
||||
}
|
||||
|
||||
int arm_set_cache_functions(void);
|
||||
|
|
|
|||
Loading…
Reference in New Issue