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remove unported includes and drivers

This commit is contained in:
Sascha Hauer 2007-09-21 14:18:25 +02:00
parent d323c2e1d2
commit 9414ad39af
29 changed files with 0 additions and 11692 deletions
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162
include/74xx_7xx.h
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@ -1,162 +0,0 @@
/*
* (C) Copyright 2001
* Josh Huber, Mission Critical Linux, Inc. <huber@mclx.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* 74xx_7xx.h
*
* 74xx/7xx specific definitions
*/
#ifndef __MPC74XX_H__
#define __MPC74XX_H__
/*----------------------------------------------------------------
* Exception offsets (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */
/*----------------------------------------------------------------
* l2cr values
*/
#define l2cr 1017
#define L2CR_L2E 0x80000000 /* bit 0 - enable */
#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */
#define L2CR_L2SIZ_2M 0x00000000 /* bits 2-3 - 2MB, MPC7400 only! */
#define L2CR_L2SIZ_1M 0x30000000 /* ... 1MB */
#define L2CR_L2SIZ_HM 0x20000000 /* ... 512K */
#define L2CR_L2SIZ_QM 0x10000000 /* ... 256k */
#define L2CR_L2CLK_1 0x02000000 /* bits 4-6 clock ratio div 1 */
#define L2CR_L2CLK_1_5 0x04000000 /* bits 4-6 clock ratio div 1.5 */
#define L2CR_L2CLK_2 0x08000000 /* bits 4-6 clock ratio div 2 */
#define L2CR_L2CLK_2_5 0x0a000000 /* bits 4-6 clock ratio div 2.5 */
#define L2CR_L2CLK_3 0x0c000000 /* bits 4-6 clock ratio div 3 */
#define L2CR_L2CLK_3_5 0x06000000 /* bits 4-6 clock ratio div 3.5 */
#define L2CR_L2CLK_4 0x0e000000 /* bits 4-6 clock ratio div 4 */
#define L2CR_L2RAM_BURST 0x01000000 /* bits 7-8 - burst SRAM */
#define L2CR_DO 0x00400000 /* bit 9 - enable caching of instr. in L2 */
#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */
#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */
#define L2CR_L2WT 0x00080000 /* bit 12 - l2 write-through */
#define L2CR_TS 0x00040000 /* bit 13 - test support on */
#define L2CR_TS_OFF -L2CR_TS /* bit 13 - test support off */
#define L2CR_L2OH_5 0x00000000 /* bits 14-15 - output hold time = short */
#define L2CR_L2OH_1 0x00010000 /* bits 14-15 - output hold time = medium */
#define L2CR_L2OH_INV 0x00020000 /* bits 14-15 - output hold time = long */
#define L2CR_L2IP 0x00000001 /* global invalidate in progress */
/*----------------------------------------------------------------
* BAT settings. Look in config_<BOARD>.h for the actual setup
*/
#define BATU_BL_128K 0x00000000
#define BATU_BL_256K 0x00000004
#define BATU_BL_512K 0x0000000c
#define BATU_BL_1M 0x0000001c
#define BATU_BL_2M 0x0000003c
#define BATU_BL_4M 0x0000007c
#define BATU_BL_8M 0x000000fc
#define BATU_BL_16M 0x000001fc
#define BATU_BL_32M 0x000003fc
#define BATU_BL_64M 0x000007fc
#define BATU_BL_128M 0x00000ffc
#define BATU_BL_256M 0x00001ffc
#define BATU_VS 0x00000002
#define BATU_VP 0x00000001
#define BATU_INVALID 0x00000000
#define BATL_WRITETHROUGH 0x00000040
#define BATL_CACHEINHIBIT 0x00000020
#define BATL_MEMCOHERENCE 0x00000010
#define BATL_GUARDEDSTORAGE 0x00000008
#define BATL_NO_ACCESS 0x00000000
#define BATL_PP_MSK 0x00000003
#define BATL_PP_00 0x00000000 /* No access */
#define BATL_PP_01 0x00000001 /* Read-only */
#define BATL_PP_10 0x00000002 /* Read-write */
#define BATL_PP_11 0x00000003
#define BATL_PP_NO_ACCESS BATL_PP_00
#define BATL_PP_RO BATL_PP_01
#define BATL_PP_RW BATL_PP_10
#ifndef __ASSEMBLY__
/* cpu ids we detect */
typedef enum __cpu_t {
CPU_740, CPU_750,
CPU_740P, CPU_750P,
CPU_745, CPU_755,
CPU_750CX, CPU_750FX, CPU_750GX,
CPU_7400,
CPU_7410,
CPU_7448,
CPU_7450, CPU_7455, CPU_7457,
CPU_UNKNOWN} cpu_t;
extern cpu_t get_cpu_type(void);
#define l1icache_enable icache_enable
void l2cache_enable(void);
void l1dcache_enable(void);
static __inline__ unsigned long get_msr (void)
{
unsigned long msr;
asm volatile("mfmsr %0" : "=r" (msr) :);
return msr;
}
static __inline__ void set_msr (unsigned long msr)
{
asm volatile("mtmsr %0" : : "r" (msr));
}
static __inline__ unsigned long get_hid0 (void)
{
unsigned long hid0;
asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
return hid0;
}
static __inline__ unsigned long get_hid1 (void)
{
unsigned long hid1;
asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
return hid1;
}
static __inline__ void set_hid0 (unsigned long hid0)
{
asm volatile("mtspr 1008, %0" : : "r" (hid0));
}
static __inline__ void set_hid1 (unsigned long hid1)
{
asm volatile("mtspr 1009, %0" : : "r" (hid1));
}
#endif /* __ASSEMBLY__ */
#endif /* __MPC74XX_H__ */

258
include/ata.h
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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Most of the following information was derived from the document
* "Information Technology - AT Attachment-3 Interface (ATA-3)"
* which can be found at:
* http://www.dt.wdc.com/ata/ata-3/ata3r5v.zip
* ftp://poctok.iae.nsk.su/pub/asm/Documents/IDE/ATA3R5V.ZIP
* ftp://ftp.fee.vutbr.cz/pub/doc/io/ata/ata-3/ata3r5v.zip
*/
#ifndef _ATA_H
#define _ATA_H
/* Register addressing depends on the hardware design; for instance,
* 8-bit (register) and 16-bit (data) accesses might use different
* address spaces. This is implemented by the following definitions.
*/
#ifndef CFG_ATA_STRIDE
#define CFG_ATA_STRIDE 1
#endif
#define ATA_IO_DATA(x) (CFG_ATA_DATA_OFFSET+((x) * CFG_ATA_STRIDE))
#define ATA_IO_REG(x) (CFG_ATA_REG_OFFSET +((x) * CFG_ATA_STRIDE))
#define ATA_IO_ALT(x) (CFG_ATA_ALT_OFFSET +((x) * CFG_ATA_STRIDE))
/*
* I/O Register Descriptions
*/
#define ATA_DATA_REG ATA_IO_DATA(0)
#define ATA_ERROR_REG ATA_IO_REG(1)
#define ATA_SECT_CNT ATA_IO_REG(2)
#define ATA_SECT_NUM ATA_IO_REG(3)
#define ATA_CYL_LOW ATA_IO_REG(4)
#define ATA_CYL_HIGH ATA_IO_REG(5)
#define ATA_DEV_HD ATA_IO_REG(6)
#define ATA_COMMAND ATA_IO_REG(7)
#define ATA_DATA_EVEN ATA_IO_REG(8)
#define ATA_DATA_ODD ATA_IO_REG(9)
#define ATA_STATUS ATA_COMMAND
#define ATA_DEV_CTL ATA_IO_ALT(6)
#define ATA_LBA_LOW ATA_SECT_NUM
#define ATA_LBA_MID ATA_CYL_LOW
#define ATA_LBA_HIGH ATA_CYL_HIGH
#define ATA_LBA_SEL ATA_DEV_CTL
/*
* Status register bits
*/
#define ATA_STAT_BUSY 0x80 /* Device Busy */
#define ATA_STAT_READY 0x40 /* Device Ready */
#define ATA_STAT_FAULT 0x20 /* Device Fault */
#define ATA_STAT_SEEK 0x10 /* Device Seek Complete */
#define ATA_STAT_DRQ 0x08 /* Data Request (ready) */
#define ATA_STAT_CORR 0x04 /* Corrected Data Error */
#define ATA_STAT_INDEX 0x02 /* Vendor specific */
#define ATA_STAT_ERR 0x01 /* Error */
/*
* Device / Head Register Bits
*/
#define ATA_DEVICE(x) ((x & 1)<<4)
#define ATA_LBA 0xE0
/*
* ATA Commands (only mandatory commands listed here)
*/
#define ATA_CMD_READ 0x20 /* Read Sectors (with retries) */
#define ATA_CMD_READN 0x21 /* Read Sectors ( no retries) */
#define ATA_CMD_WRITE 0x30 /* Write Sectores (with retries)*/
#define ATA_CMD_WRITEN 0x31 /* Write Sectors ( no retries)*/
#define ATA_CMD_VRFY 0x40 /* Read Verify (with retries) */
#define ATA_CMD_VRFYN 0x41 /* Read verify ( no retries) */
#define ATA_CMD_SEEK 0x70 /* Seek */
#define ATA_CMD_DIAG 0x90 /* Execute Device Diagnostic */
#define ATA_CMD_INIT 0x91 /* Initialize Device Parameters */
#define ATA_CMD_RD_MULT 0xC4 /* Read Multiple */
#define ATA_CMD_WR_MULT 0xC5 /* Write Multiple */
#define ATA_CMD_SETMULT 0xC6 /* Set Multiple Mode */
#define ATA_CMD_RD_DMA 0xC8 /* Read DMA (with retries) */
#define ATA_CMD_RD_DMAN 0xC9 /* Read DMS ( no retries) */
#define ATA_CMD_WR_DMA 0xCA /* Write DMA (with retries) */
#define ATA_CMD_WR_DMAN 0xCB /* Write DMA ( no retires) */
#define ATA_CMD_IDENT 0xEC /* Identify Device */
#define ATA_CMD_SETF 0xEF /* Set Features */
#define ATA_CMD_CHK_PWR 0xE5 /* Check Power Mode */
#define ATA_CMD_READ_EXT 0x24 /* Read Sectors (with retries) with 48bit addressing */
#define ATA_CMD_WRITE_EXT 0x34 /* Write Sectores (with retries) with 48bit addressing */
#define ATA_CMD_VRFY_EXT 0x42 /* Read Verify (with retries) with 48bit addressing */
/*
* ATAPI Commands
*/
#define ATAPI_CMD_IDENT 0xA1 /* Identify AT Atachment Packed Interface Device */
#define ATAPI_CMD_PACKET 0xA0 /* Packed Command */
#define ATAPI_CMD_INQUIRY 0x12
#define ATAPI_CMD_REQ_SENSE 0x03
#define ATAPI_CMD_READ_CAP 0x25
#define ATAPI_CMD_START_STOP 0x1B
#define ATAPI_CMD_READ_12 0xA8
#define ATA_GET_ERR() inb(ATA_STATUS)
#define ATA_GET_STAT() inb(ATA_STATUS)
#define ATA_OK_STAT(stat,good,bad) (((stat)&((good)|(bad)))==(good))
#define ATA_BAD_R_STAT (ATA_STAT_BUSY | ATA_STAT_ERR)
#define ATA_BAD_W_STAT (ATA_BAD_R_STAT | ATA_STAT_FAULT)
#define ATA_BAD_STAT (ATA_BAD_R_STAT | ATA_STAT_DRQ)
#define ATA_DRIVE_READY (ATA_READY_STAT | ATA_STAT_SEEK)
#define ATA_DATA_READY (ATA_STAT_DRQ)
#define ATA_BLOCKSIZE 512 /* bytes */
#define ATA_BLOCKSHIFT 9 /* 2 ^ ATA_BLOCKSIZESHIFT = 512 */
#define ATA_SECTORWORDS (512 / sizeof(unsigned long))
#ifndef ATA_RESET_TIME
#define ATA_RESET_TIME 60 /* spec allows up to 31 seconds */
#endif
/* ------------------------------------------------------------------------- */
/*
* structure returned by ATA_CMD_IDENT, as per ANSI ATA2 rev.2f spec
*/
typedef struct hd_driveid {
unsigned short config; /* lots of obsolete bit flags */
unsigned short cyls; /* "physical" cyls */
unsigned short reserved2; /* reserved (word 2) */
unsigned short heads; /* "physical" heads */
unsigned short track_bytes; /* unformatted bytes per track */
unsigned short sector_bytes; /* unformatted bytes per sector */
unsigned short sectors; /* "physical" sectors per track */
unsigned short vendor0; /* vendor unique */
unsigned short vendor1; /* vendor unique */
unsigned short vendor2; /* vendor unique */
unsigned char serial_no[20]; /* 0 = not_specified */
unsigned short buf_type;
unsigned short buf_size; /* 512 byte increments; 0 = not_specified */
unsigned short ecc_bytes; /* for r/w long cmds; 0 = not_specified */
unsigned char fw_rev[8]; /* 0 = not_specified */
unsigned char model[40]; /* 0 = not_specified */
unsigned char max_multsect; /* 0=not_implemented */
unsigned char vendor3; /* vendor unique */
unsigned short dword_io; /* 0=not_implemented; 1=implemented */
unsigned char vendor4; /* vendor unique */
unsigned char capability; /* bits 0:DMA 1:LBA 2:IORDYsw 3:IORDYsup*/
unsigned short reserved50; /* reserved (word 50) */
unsigned char vendor5; /* vendor unique */
unsigned char tPIO; /* 0=slow, 1=medium, 2=fast */
unsigned char vendor6; /* vendor unique */
unsigned char tDMA; /* 0=slow, 1=medium, 2=fast */
unsigned short field_valid; /* bits 0:cur_ok 1:eide_ok */
unsigned short cur_cyls; /* logical cylinders */
unsigned short cur_heads; /* logical heads */
unsigned short cur_sectors; /* logical sectors per track */
unsigned short cur_capacity0; /* logical total sectors on drive */
unsigned short cur_capacity1; /* (2 words, misaligned int) */
unsigned char multsect; /* current multiple sector count */
unsigned char multsect_valid; /* when (bit0==1) multsect is ok */
unsigned int lba_capacity; /* total number of sectors */
unsigned short dma_1word; /* single-word dma info */
unsigned short dma_mword; /* multiple-word dma info */
unsigned short eide_pio_modes; /* bits 0:mode3 1:mode4 */
unsigned short eide_dma_min; /* min mword dma cycle time (ns) */
unsigned short eide_dma_time; /* recommended mword dma cycle time (ns) */
unsigned short eide_pio; /* min cycle time (ns), no IORDY */
unsigned short eide_pio_iordy; /* min cycle time (ns), with IORDY */
unsigned short words69_70[2]; /* reserved words 69-70 */
unsigned short words71_74[4]; /* reserved words 71-74 */
unsigned short queue_depth; /* */
unsigned short words76_79[4]; /* reserved words 76-79 */
unsigned short major_rev_num; /* */
unsigned short minor_rev_num; /* */
unsigned short command_set_1; /* bits 0:Smart 1:Security 2:Removable 3:PM */
unsigned short command_set_2; /* bits 14:Smart Enabled 13:0 zero 10:lba48 support*/
unsigned short cfsse; /* command set-feature supported extensions */
unsigned short cfs_enable_1; /* command set-feature enabled */
unsigned short cfs_enable_2; /* command set-feature enabled */
unsigned short csf_default; /* command set-feature default */
unsigned short dma_ultra; /* */
unsigned short word89; /* reserved (word 89) */
unsigned short word90; /* reserved (word 90) */
unsigned short CurAPMvalues; /* current APM values */
unsigned short word92; /* reserved (word 92) */
unsigned short hw_config; /* hardware config */
unsigned short words94_99[6];/* reserved words 94-99 */
/*unsigned long long lba48_capacity; /--* 4 16bit values containing lba 48 total number of sectors */
unsigned short lba48_capacity[4]; /* 4 16bit values containing lba 48 total number of sectors */
unsigned short words104_125[22];/* reserved words 104-125 */
unsigned short last_lun; /* reserved (word 126) */
unsigned short word127; /* reserved (word 127) */
unsigned short dlf; /* device lock function
* 15:9 reserved
* 8 security level 1:max 0:high
* 7:6 reserved
* 5 enhanced erase
* 4 expire
* 3 frozen
* 2 locked
* 1 en/disabled
* 0 capability
*/
unsigned short csfo; /* current set features options
* 15:4 reserved
* 3 auto reassign
* 2 reverting
* 1 read-look-ahead
* 0 write cache
*/
unsigned short words130_155[26];/* reserved vendor words 130-155 */
unsigned short word156;
unsigned short words157_159[3];/* reserved vendor words 157-159 */
unsigned short words160_255[95];/* reserved words 160-255 */
} hd_driveid_t;
/*
* PIO Mode Configuration
*
* See ATA-3 (AT Attachment-3 Interface) documentation, Figure 14 / Table 21
*/
typedef struct {
unsigned int t_setup; /* Setup Time in [ns] or clocks */
unsigned int t_length; /* Length Time in [ns] or clocks */
unsigned int t_hold; /* Hold Time in [ns] or clocks */
}
pio_config_t;
#define IDE_MAX_PIO_MODE 4 /* max suppurted PIO mode */
/* ------------------------------------------------------------------------- */
#endif /* _ATA_H */

42
include/bedbug/bedbug.h
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/* $Id$ */
#ifndef _BEDBUG_H
#define _BEDBUG_H
#ifndef NULL
#define NULL 0
#endif
#define _USE_PROTOTYPES
#ifndef isblank
#define isblank(c) isspace((int)(c))
#endif
#ifndef __P
#if defined(_USE_PROTOTYPES) && (defined(__STDC__) || defined(__cplusplus))
#define __P(protos) protos /* full-blown ANSI C */
#else
#define __P(protos) () /* traditional C preprocessor */
#endif
#endif
#define assert( condition ) if( (condition) ) _exit(0)
#endif /* _BEDBUG_H */
/*
* Copyright (c) 2001 William L. Pitts
* All rights reserved.
*
* Redistribution and use in source and binary forms are freely
* permitted provided that the above copyright notice and this
* paragraph and the following disclaimer are duplicated in all
* such forms.
*
* This software is provided "AS IS" and without any express or
* implied warranties, including, without limitation, the implied
* warranties of merchantability and fitness for a particular
* purpose.
*/

413
include/bedbug/ppc.h
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/* $Id$ */
#ifndef _PPC_H
#define _PPC_H
/*======================================================================
*
* OPERANDS
*
*======================================================================*/
enum OP_FIELD {
O_AA = 1, O_BD, O_BI, O_BO, O_crbD, O_crbA, O_crbB, O_CRM, O_d, O_frC, O_frD,
O_frS, O_IMM, O_LI, O_LK, O_MB, O_ME, O_NB, O_OE, O_rA, O_rB, O_Rc, O_rD,
O_rS, O_SH, O_SIMM, O_SR, O_TO, O_UIMM, O_crfD, O_crfS, O_L, O_spr, O_tbr,
O_cr2 };
struct operand {
enum OP_FIELD field; /* The operand identifier from the
enum above */
char * name; /* Symbolic name of this operand */
unsigned int bits; /* The number of bits used by this
operand */
unsigned int shift; /* How far to the right the operand
should be shifted so that it is
aligned at the beginning of the
word */
unsigned int hint; /* A bitwise-inclusive-OR of the
values shown below. These are used
tell the disassembler how to print
this operand */
};
/* Values for operand hint */
#define OH_SILENT 0x01 /* dont print this operand */
#define OH_ADDR 0x02 /* this operand is an address */
#define OH_REG 0x04 /* this operand is a register */
#define OH_SPR 0x08 /* this operand is an SPR */
#define OH_TBR 0x10 /* this operand is a TBR */
#define OH_OFFSET 0x20 /* this operand is an offset */
#define OH_LITERAL 0x40 /* a literal string */
/*======================================================================
*
* OPCODES
*
*======================================================================*/
/* From the MPCxxx instruction set documentation, all instructions are
* 32 bits long and word aligned. Bits 0-5 always specify the primary
* opcode. Many instructions also have an extended opcode.
*/
#define GET_OPCD(i) (((unsigned long)(i) >> 26) & 0x3f)
#define MAKE_OPCODE(i) ((((unsigned long)(i)) & 0x3f) << 26)
/* The MPC860 User's Manual, Appendix D.4 contains the definitions of the
* instruction forms
*/
/*-------------------------------------------------
* I-Form Instructions:
* bX
*-------------------------------------------------
* OPCD | LI |AA|LK
*-------------------------------------------------*/
#define I_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1))
#define I_MASK I_OPCODE(0x3f,0x1,0x1)
/*-------------------------------------------------
* B-Form Instructions:
* bcX
*-------------------------------------------------
* OPCD | BO | BI | BD |AA|LK
*-------------------------------------------------*/
#define B_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1))
#define B_MASK B_OPCODE(0x3f,0x1,0x1)
/*-------------------------------------------------
* SC-Form Instructions:
* sc
*-------------------------------------------------
* OPCD | 00000 | 00000 | 00000000000000 |1|0
*-------------------------------------------------*/
#define SC_OPCODE(i) (MAKE_OPCODE(i) | 0x2)
#define SC_MASK SC_OPCODE(0x3f)
/*-------------------------------------------------
* D-Form Instructions:
* addi addic addic. addis andi. andis. cmpi cmpli
* lbz lbzu lha lhau lhz lhzu lmw lwz lwzu mulli
* ori oris stb stbu sth sthu stmw stw stwu subfic
* twi xori xoris
*-------------------------------------------------
* OPCD | D | A | d
* OPCD | D | A | SIMM
* OPCD | S | A | d
* OPCD | S | A | UIMM
* OPCD |crfD|0|L| A | SIMM
* OPCD |crfD|0|L| A | UIMM
* OPCD | TO | A | SIMM
*-------------------------------------------------*/
#define D_OPCODE(i) MAKE_OPCODE(i)
#define D_MASK MAKE_OPCODE(0x3f)
/*-------------------------------------------------
* DS-Form Instructions:
* (none supported by MPC860)
*-------------------------------------------------
* OPCD | D | A | ds |XO
* OPCD | S | A | ds |XO
*-------------------------------------------------*/
#define DS_OPCODE(i,xo) (MAKE_OPCODE(i) | ((xo) & 0x3))
#define DS_MASK DS_OPCODE(0x3f,0x1)
/*---------------------------------------------------
* X-Form Instructions:
* andX andcX cmp cmpl cntlzwX dcbf dcbi dcbst dcbt
* dcbtst dcbz eciwx ecowx eieio eqvX extsbX extshX
* icbi lbzux lbxz lhaux lhax lhbrx lhzux lhxz lswi
* lswx lwarx lwbrx lwzux lwxz mcrfs mcrxr mfcr
* mfmsr mfsr mfsrin mtmsr mtsr mtsrin nandX norX
* orX orcX slwX srawX srawiX srwX stbux stbx
* sthbrx sthuxsthx stswi stswx stwbrx stwcx. stwux
* stwx sync tlbie tlbld tlbli tlbsync tw xorX
*---------------------------------------------------
* OPCD | D | A | B | XO |0
* OPCD | D | A | NB | XO |0
* OPCD | D | 00000 | B | XO |0
* OPCD | D | 00000 | 00000 | XO |0
* OPCD | D |0| SR | 00000 | XO |0
* OPCD | S | A | B | XO |Rc
* OPCD | S | A | B | XO |1
* OPCD | S | A | B | XO |0
* OPCD | S | A | NB | XO |0
* OPCD | S | A | 00000 | XO |Rc
* OPCD | S | 00000 | B | XO |0
* OPCD | S | 00000 | 00000 | XO |0
* OPCD | S |0| SR | 00000 | XO |0
* OPCD | S | A | SH | XO |Rc
* OPCD |crfD|0|L| A | SH | XO |0
* OPCD |crfD |00| A | B | XO |0
* OPCD |crfD |00|crfS |00| 00000 | XO |0
* OPCD |crfD |00| 00000 | 00000 | XO |0
* OPCD |crfD |00| 00000 | IMM |0| XO |Rc
* OPCD | TO | A | B | XO |0
* OPCD | D | 00000 | B | XO |Rc
* OPCD | D | 00000 | 00000 | XO |Rc
* OPCD | crbD | 00000 | 00000 | XO |Rc
* OPCD | 00000 | A | B | XO |0
* OPCD | 00000 | 00000 | B | XO |0
* OPCD | 00000 | 00000 | 00000 | XO |0
*---------------------------------------------------*/
#define X_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
((rc) & 0x1))
#define X_MASK X_OPCODE(0x3f,0x3ff,0x1)
/*---------------------------------------------------
* XL-Form Instructions:
* bcctrX bclrX crand crandc creqv crnand crnor cror
* croc crxorisync mcrf rfi
*---------------------------------------------------
* OPCD | BO | BI | 00000 | XO |LK
* OPCD | crbD | crbA | crbB | XO |0
* OPCD |crfD |00|crfS |00| 00000 | XO |0
* OPCD | 00000 | 00000 | 00000 | XO |0
*---------------------------------------------------*/
#define XL_OPCODE(i,xo,lk) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
((lk) & 0x1))
#define XL_MASK XL_OPCODE(0x3f,0x3ff,0x1)
/*---------------------------------------------------
* XFX-Form Instructions:
* mfspr mftb mtcrf mtspr
*---------------------------------------------------
* OPCD | D | spr | XO |0
* OPCD | D |0| CRM |0| XO |0
* OPCD | S | spr | XO |0
* OPCD | D | tbr | XO |0
*---------------------------------------------------*/
#define XFX_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
((rc) & 0x1))
#define XFX_MASK XFX_OPCODE(0x3f,0x3ff,0x1)
/*---------------------------------------------------
* XFL-Form Instructions:
* (none supported by MPC860)
*---------------------------------------------------
* OPCD |0| FM |0| B | XO |0
*---------------------------------------------------*/
#define XFL_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
((rc) & 0x1))
#define XFL_MASK XFL_OPCODE(0x3f,0x3ff,0x1)
/*---------------------------------------------------
* XS-Form Instructions:
* (none supported by MPC860)
*---------------------------------------------------
* OPCD | S | A | sh | XO |sh|LK
*---------------------------------------------------*/
#define XS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1ff) << 2) | \
((rc) & 0x1))
#define XS_MASK XS_OPCODE(0x3f,0x1ff,0x1)
/*---------------------------------------------------
* XO-Form Instructions:
* addX addcXaddeX addmeX addzeX divwX divwuX mulhwX
* mulhwuX mullwX negX subfX subfcX subfeX subfmeX
* subfzeX
*---------------------------------------------------
* OPCD | D | A | B |OE| XO |Rc
* OPCD | D | A | B |0 | XO |Rc
* OPCD | D | A | 00000 |OE| XO |Rc
*---------------------------------------------------*/
#define XO_OPCODE(i,xo,oe,rc) (MAKE_OPCODE(i) | (((oe) & 0x1) << 10) | \
(((xo) & 0x1ff) << 1) | ((rc) & 0x1))
#define XO_MASK XO_OPCODE(0x3f,0x1ff,0x1,0x1)
/*---------------------------------------------------
* A-Form Instructions:
* (none supported by MPC860)
*---------------------------------------------------
* OPCD | D | A | B |00000| XO |Rc
* OPCD | D | A | B | C | XO |Rc
* OPCD | D | A | 00000 | C | XO |Rc
* OPCD | D | 00000 | B |00000| XO |Rc
*---------------------------------------------------*/
#define A_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1f) << 1) | \
((rc) & 0x1))
#define A_MASK A_OPCODE(0x3f,0x1f,0x1)
/*---------------------------------------------------
* M-Form Instructions:
* rlwimiX rlwinmX rlwnmX
*---------------------------------------------------
* OPCD | S | A | SH | MB | ME |Rc
* OPCD | S | A | B | MB | ME |Rc
*---------------------------------------------------*/
#define M_OPCODE(i,rc) (MAKE_OPCODE(i) | ((rc) & 0x1))
#define M_MASK M_OPCODE(0x3f,0x1)
/*---------------------------------------------------
* MD-Form Instructions:
* (none supported by MPC860)
*---------------------------------------------------
* OPCD | S | A | sh | mb | XO |sh|Rc
* OPCD | S | A | sh | me | XO |sh|Rc
*---------------------------------------------------*/
#define MD_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x7) << 2) | \
((rc) & 0x1))
#define MD_MASK MD_OPCODE(0x3f,0x7,0x1)
/*---------------------------------------------------
* MDS-Form Instructions:
* (none supported by MPC860)
*---------------------------------------------------
* OPCD | S | A | B | mb | XO |Rc
* OPCD | S | A | B | me | XO |Rc
*---------------------------------------------------*/
#define MDS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0xf) << 1) | \
((rc) & 0x1))
#define MDS_MASK MDS_OPCODE(0x3f,0xf,0x1)
#ifndef FALSE
#define FALSE 0
#define TRUE (!FALSE)
#endif
#define INSTRUCTION( memaddr ) ntohl(*(unsigned long *)(memaddr))
#define MAX_OPERANDS 8
struct ppc_ctx;
struct opcode {
unsigned long opcode; /* The complete opcode as produced by
one of the XXX_OPCODE macros above */
unsigned long mask; /* The mask to use on an instruction
before comparing with the opcode
field to see if it matches */
enum OP_FIELD fields[MAX_OPERANDS];
/* An array defining the operands for
this opcode. The values of the
array are the operand identifiers */
int (*hfunc)(struct ppc_ctx *);
/* Address of a function to handle the given
mnemonic */
char * name; /* The symbolic name of this opcode */
unsigned int hint; /* A bitwise-inclusive-OR of the
values shown below. These are used
tell the disassembler how to print
some operands for this opcode */
};
/* values for opcode hints */
#define H_RELATIVE 0x1 /* The address operand is relative */
#define H_IMM_HIGH 0x2 /* [U|S]IMM field shifted high */
#define H_RA0_IS_0 0x4 /* If rA = 0 then treat as literal 0 */
struct ppc_ctx {
struct opcode * op;
unsigned long instr;
unsigned int flags;
int datalen;
char data[ 256 ];
char radix_fmt[ 8 ];
unsigned char * virtual;
};
/*======================================================================
*
* FUNCTIONS
*
*======================================================================*/
/* Values for flags as passed to various ppc routines */
#define F_RADOCTAL 0x1 /* output radix = unsigned octal */
#define F_RADUDECIMAL 0x2 /* output radix = unsigned decimal */
#define F_RADSDECIMAL 0x4 /* output radix = signed decimal */
#define F_RADHEX 0x8 /* output radix = unsigned hex */
#define F_SIMPLE 0x10 /* use simplified mnemonics */
#define F_SYMBOL 0x20 /* use symbol lookups for addresses */
#define F_INSTR 0x40 /* output the raw instruction */
#define F_LOCALMEM 0x80 /* retrieve opcodes from local memory
rather than from the HMI */
#define F_LINENO 0x100 /* show line number info if available */
#define F_VALIDONLY 0x200 /* cache: valid entries only */
/* Values for assembler error codes */
#define E_ASM_BAD_OPCODE 1
#define E_ASM_NUM_OPERANDS 2
#define E_ASM_BAD_REGISTER 3
#define E_ASM_BAD_SPR 4
#define E_ASM_BAD_TBR 5
extern int disppc __P((unsigned char *,unsigned char *,int,
int (*)(const char *), unsigned long));
extern int print_source_line __P((char *,char *,int,
int (*pfunc)(const char *)));
extern int find_next_address __P((unsigned char *,int,struct pt_regs *));
extern int handle_bc __P((struct ppc_ctx *));
extern unsigned long asmppc __P((unsigned long,char*,int*));
extern char *asm_error_str __P((int));
/*======================================================================
*
* GLOBAL VARIABLES
*
*======================================================================*/
extern struct operand operands[];
extern const unsigned int n_operands;
extern struct opcode opcodes[];
extern const unsigned int n_opcodes;
#endif /* _PPC_H */
/*
* Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
* All rights reserved.
*
* Redistribution and use in source and binary forms are freely
* permitted provided that the above copyright notice and this
* paragraph and the following disclaimer are duplicated in all
* such forms.
*
* This software is provided "AS IS" and without any express or
* implied warranties, including, without limitation, the implied
* warranties of merchantability and fitness for a particular
* purpose.
*/

403
include/bedbug/regs.h
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@ -1,403 +0,0 @@
/* $Id$ */
#ifndef _REGS_H
#define _REGS_H
/* Special Purpose Registers */
#define SPR_CR -1
#define SPR_MSR -2
#define SPR_XER 1
#define SPR_LR 8
#define SPR_CTR 9
#define SPR_DSISR 18
#define SPR_DAR 19
#define SPR_DEC 22
#define SPR_SRR0 26
#define SPR_SRR1 27
#define SPR_EIE 80
#define SPR_EID 81
#define SPR_CMPA 144
#define SPR_CMPB 145
#define SPR_CMPC 146
#define SPR_CMPD 147
#define SPR_ICR 148
#define SPR_DER 149
#define SPR_COUNTA 150
#define SPR_COUNTB 151
#define SPR_CMPE 152
#define SPR_CMPF 153
#define SPR_CMPG 154
#define SPR_CMPH 155
#define SPR_LCTRL1 156
#define SPR_LCTRL2 157
#define SPR_ICTRL 158
#define SPR_BAR 159
#define SPR_USPRG0 256
#define SPR_SPRG4_RO 260
#define SPR_SPRG5_RO 261
#define SPR_SPRG6_RO 262
#define SPR_SPRG7_RO 263
#define SPR_SPRG0 272
#define SPR_SPRG1 273
#define SPR_SPRG2 274
#define SPR_SPRG3 275
#define SPR_SPRG4 276
#define SPR_SPRG5 277
#define SPR_SPRG6 278
#define SPR_SPRG7 279
#define SPR_EAR 282 /* MPC603e core */
#define SPR_TBL 284
#define SPR_TBU 285
#define SPR_PVR 287
#define SPR_IC_CST 560
#define SPR_IC_ADR 561
#define SPR_IC_DAT 562
#define SPR_DC_CST 568
#define SPR_DC_ADR 569
#define SPR_DC_DAT 570
#define SPR_DPDR 630
#define SPR_IMMR 638
#define SPR_MI_CTR 784
#define SPR_MI_AP 786
#define SPR_MI_EPN 787
#define SPR_MI_TWC 789
#define SPR_MI_RPN 790
#define SPR_MD_CTR 792
#define SPR_M_CASID 793
#define SPR_MD_AP 794
#define SPR_MD_EPN 795
#define SPR_M_TWB 796
#define SPR_MD_TWC 797
#define SPR_MD_RPN 798
#define SPR_M_TW 799
#define SPR_MI_DBCAM 816
#define SPR_MI_DBRAM0 817
#define SPR_MI_DBRAM1 818
#define SPR_MD_DBCAM 824
#define SPR_MD_DBRAM0 825
#define SPR_MD_DBRAM1 826
#define SPR_ZPR 944
#define SPR_PID 945
#define SPR_CCR0 947
#define SPR_IAC3 948
#define SPR_IAC4 949
#define SPR_DVC1 950
#define SPR_DVC2 951
#define SPR_SGR 953
#define SPR_DCWR 954
#define SPR_SLER 955
#define SPR_SU0R 956
#define SPR_DBCR1 957
#define SPR_ICDBDR 979
#define SPR_ESR 980
#define SPR_DEAR 981
#define SPR_EVPR 982
#define SPR_TSR 984
#define SPR_TCR 986
#define SPR_PIT 987
#define SPR_SRR2 990
#define SPR_SRR3 991
#define SPR_DBSR 1008
#define SPR_DBCR0 1010
#define SPR_IABR 1010 /* MPC603e core */
#define SPR_IAC1 1012
#define SPR_IAC2 1013
#define SPR_DAC1 1014
#define SPR_DAC2 1015
#define SPR_DCCR 1018
#define SPR_ICCR 1019
/* Bits for the DBCR0 register */
#define DBCR0_EDM 0x80000000
#define DBCR0_IDM 0x40000000
#define DBCR0_RST 0x30000000
#define DBCR0_IC 0x08000000
#define DBCR0_BT 0x04000000
#define DBCR0_EDE 0x02000000
#define DBCR0_TDE 0x01000000
#define DBCR0_IA1 0x00800000
#define DBCR0_IA2 0x00400000
#define DBCR0_IA12 0x00200000
#define DBCR0_IA12X 0x00100000
#define DBCR0_IA3 0x00080000
#define DBCR0_IA4 0x00040000
#define DBCR0_IA34 0x00020000
#define DBCR0_IA34X 0x00010000
#define DBCR0_IA12T 0x00008000
#define DBCR0_IA34T 0x00004000
#define DBCR0_FT 0x00000001
/* Bits for the DBCR1 register */
#define DBCR1_D1R 0x80000000
#define DBCR1_D2R 0x40000000
#define DBCR1_D1W 0x20000000
#define DBCR1_D2W 0x10000000
#define DBCR1_D1S 0x0C000000
#define DBCR1_D2S 0x03000000
#define DBCR1_DA12 0x00800000
#define DBCR1_DA12X 0x00400000
#define DBCR1_DV1M 0x000C0000
#define DBCR1_DV2M 0x00030000
#define DBCR1_DV1BE 0x0000F000
#define DBCR1_DV2BE 0x00000F00
/* Bits for the DBSR register */
#define DBSR_IC 0x80000000
#define DBSR_BT 0x40000000
#define DBSR_EDE 0x20000000
#define DBSR_TIE 0x10000000
#define DBSR_UDE 0x08000000
#define DBSR_IA1 0x04000000
#define DBSR_IA2 0x02000000
#define DBSR_DR1 0x01000000
#define DBSR_DW1 0x00800000
#define DBSR_DR2 0x00400000
#define DBSR_DW2 0x00200000
#define DBSR_IDE 0x00100000
#define DBSR_IA3 0x00080000
#define DBSR_IA4 0x00040000
#define DBSR_MRR 0x00000300
struct spr_info {
int spr_val;
char spr_name[ 10 ];
};
extern struct spr_info spr_map[];
extern const unsigned int n_sprs;
#define SET_REGISTER( str, val ) \
({ unsigned long __value = (val); \
asm volatile( str : : "r" (__value)); \
__value; })
#define GET_REGISTER( str ) \
({ unsigned long __value; \
asm volatile( str : "=r" (__value) : ); \
__value; })
#define GET_CR() GET_REGISTER( "mfcr %0" )
#define SET_CR(val) SET_REGISTER( "mtcr %0", val )
#define GET_MSR() GET_REGISTER( "mfmsr %0" )
#define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
#define GET_XER() GET_REGISTER( "mfspr %0,1" )
#define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
#define GET_LR() GET_REGISTER( "mfspr %0,8" )
#define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
#define GET_CTR() GET_REGISTER( "mfspr %0,9" )
#define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
#define GET_DSISR() GET_REGISTER( "mfspr %0,18" )
#define SET_DSISR(val) SET_REGISTER( "mtspr 18,%0", val )
#define GET_DAR() GET_REGISTER( "mfspr %0,19" )
#define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
#define GET_DEC() GET_REGISTER( "mfspr %0,22" )
#define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
#define GET_SRR0() GET_REGISTER( "mfspr %0,26" )
#define SET_SRR0(val) SET_REGISTER( "mtspr 26,%0", val )
#define GET_SRR1() GET_REGISTER( "mfspr %0,27" )
#define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
#define GET_EIE() GET_REGISTER( "mfspr %0,80" )
#define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
#define GET_EID() GET_REGISTER( "mfspr %0,81" )
#define SET_EID(val) SET_REGISTER( "mtspr 81,%0", val )
#define GET_CMPA() GET_REGISTER( "mfspr %0,144" )
#define SET_CMPA(val) SET_REGISTER( "mtspr 144,%0", val )
#define GET_CMPB() GET_REGISTER( "mfspr %0,145" )
#define SET_CMPB(val) SET_REGISTER( "mtspr 145,%0", val )
#define GET_CMPC() GET_REGISTER( "mfspr %0,146" )
#define SET_CMPC(val) SET_REGISTER( "mtspr 146,%0", val )
#define GET_CMPD() GET_REGISTER( "mfspr %0,147" )
#define SET_CMPD(val) SET_REGISTER( "mtspr 147,%0", val )
#define GET_ICR() GET_REGISTER( "mfspr %0,148" )
#define SET_ICR(val) SET_REGISTER( "mtspr 148,%0", val )
#define GET_DER() GET_REGISTER( "mfspr %0,149" )
#define SET_DER(val) SET_REGISTER( "mtspr 149,%0", val )
#define GET_COUNTA() GET_REGISTER( "mfspr %0,150" )
#define SET_COUNTA(val) SET_REGISTER( "mtspr 150,%0", val )
#define GET_COUNTB() GET_REGISTER( "mfspr %0,151" )
#define SET_COUNTB(val) SET_REGISTER( "mtspr 151,%0", val )
#define GET_CMPE() GET_REGISTER( "mfspr %0,152" )
#define SET_CMPE(val) SET_REGISTER( "mtspr 152,%0", val )
#define GET_CMPF() GET_REGISTER( "mfspr %0,153" )
#define SET_CMPF(val) SET_REGISTER( "mtspr 153,%0", val )
#define GET_CMPG() GET_REGISTER( "mfspr %0,154" )
#define SET_CMPG(val) SET_REGISTER( "mtspr 154,%0", val )
#define GET_CMPH() GET_REGISTER( "mfspr %0,155" )
#define SET_CMPH(val) SET_REGISTER( "mtspr 155,%0", val )
#define GET_LCTRL1() GET_REGISTER( "mfspr %0,156" )
#define SET_LCTRL1(val) SET_REGISTER( "mtspr 156,%0", val )
#define GET_LCTRL2() GET_REGISTER( "mfspr %0,157" )
#define SET_LCTRL2(val) SET_REGISTER( "mtspr 157,%0", val )
#define GET_ICTRL() GET_REGISTER( "mfspr %0,158" )
#define SET_ICTRL(val) SET_REGISTER( "mtspr 158,%0", val )
#define GET_BAR() GET_REGISTER( "mfspr %0,159" )
#define SET_BAR(val) SET_REGISTER( "mtspr 159,%0", val )
#define GET_USPRG0() GET_REGISTER( "mfspr %0,256" )
#define SET_USPRG0(val) SET_REGISTER( "mtspr 256,%0", val )
#define GET_SPRG4_RO() GET_REGISTER( "mfspr %0,260" )
#define SET_SPRG4_RO(val) SET_REGISTER( "mtspr 260,%0", val )
#define GET_SPRG5_RO() GET_REGISTER( "mfspr %0,261" )
#define SET_SPRG5_RO(val) SET_REGISTER( "mtspr 261,%0", val )
#define GET_SPRG6_RO() GET_REGISTER( "mfspr %0,262" )
#define SET_SPRG6_RO(val) SET_REGISTER( "mtspr 262,%0", val )
#define GET_SPRG7_RO() GET_REGISTER( "mfspr %0,263" )
#define SET_SPRG7_RO(val) SET_REGISTER( "mtspr 263,%0", val )
#define GET_SPRG0() GET_REGISTER( "mfspr %0,272" )
#define SET_SPRG0(val) SET_REGISTER( "mtspr 272,%0", val )
#define GET_SPRG1() GET_REGISTER( "mfspr %0,273" )
#define SET_SPRG1(val) SET_REGISTER( "mtspr 273,%0", val )
#define GET_SPRG2() GET_REGISTER( "mfspr %0,274" )
#define SET_SPRG2(val) SET_REGISTER( "mtspr 274,%0", val )
#define GET_SPRG3() GET_REGISTER( "mfspr %0,275" )
#define SET_SPRG3(val) SET_REGISTER( "mtspr 275,%0", val )
#define GET_SPRG4() GET_REGISTER( "mfspr %0,276" )
#define SET_SPRG4(val) SET_REGISTER( "mtspr 276,%0", val )
#define GET_SPRG5() GET_REGISTER( "mfspr %0,277" )
#define SET_SPRG5(val) SET_REGISTER( "mtspr 277,%0", val )
#define GET_SPRG6() GET_REGISTER( "mfspr %0,278" )
#define SET_SPRG6(val) SET_REGISTER( "mtspr 278,%0", val )
#define GET_SPRG7() GET_REGISTER( "mfspr %0,279" )
#define SET_SPRG7(val) SET_REGISTER( "mtspr 279,%0", val )
#define GET_EAR() GET_REGISTER( "mfspr %0,282" )
#define SET_EAR(val) SET_REGISTER( "mtspr 282,%0", val )
#define GET_TBL() GET_REGISTER( "mfspr %0,284" )
#define SET_TBL(val) SET_REGISTER( "mtspr 284,%0", val )
#define GET_TBU() GET_REGISTER( "mfspr %0,285" )
#define SET_TBU(val) SET_REGISTER( "mtspr 285,%0", val )
#define GET_PVR() GET_REGISTER( "mfspr %0,287" )
#define SET_PVR(val) SET_REGISTER( "mtspr 287,%0", val )
#define GET_IC_CST() GET_REGISTER( "mfspr %0,560" )
#define SET_IC_CST(val) SET_REGISTER( "mtspr 560,%0", val )
#define GET_IC_ADR() GET_REGISTER( "mfspr %0,561" )
#define SET_IC_ADR(val) SET_REGISTER( "mtspr 561,%0", val )
#define GET_IC_DAT() GET_REGISTER( "mfspr %0,562" )
#define SET_IC_DAT(val) SET_REGISTER( "mtspr 562,%0", val )
#define GET_DC_CST() GET_REGISTER( "mfspr %0,568" )
#define SET_DC_CST(val) SET_REGISTER( "mtspr 568,%0", val )
#define GET_DC_ADR() GET_REGISTER( "mfspr %0,569" )
#define SET_DC_ADR(val) SET_REGISTER( "mtspr 569,%0", val )
#define GET_DC_DAT() GET_REGISTER( "mfspr %0,570" )
#define SET_DC_DAT(val) SET_REGISTER( "mtspr 570,%0", val )
#define GET_DPDR() GET_REGISTER( "mfspr %0,630" )
#define SET_DPDR(val) SET_REGISTER( "mtspr 630,%0", val )
#define GET_IMMR() GET_REGISTER( "mfspr %0,638" )
#define SET_IMMR(val) SET_REGISTER( "mtspr 638,%0", val )
#define GET_MI_CTR() GET_REGISTER( "mfspr %0,784" )
#define SET_MI_CTR(val) SET_REGISTER( "mtspr 784,%0", val )
#define GET_MI_AP() GET_REGISTER( "mfspr %0,786" )
#define SET_MI_AP(val) SET_REGISTER( "mtspr 786,%0", val )
#define GET_MI_EPN() GET_REGISTER( "mfspr %0,787" )
#define SET_MI_EPN(val) SET_REGISTER( "mtspr 787,%0", val )
#define GET_MI_TWC() GET_REGISTER( "mfspr %0,789" )
#define SET_MI_TWC(val) SET_REGISTER( "mtspr 789,%0", val )
#define GET_MI_RPN() GET_REGISTER( "mfspr %0,790" )
#define SET_MI_RPN(val) SET_REGISTER( "mtspr 790,%0", val )
#define GET_MD_CTR() GET_REGISTER( "mfspr %0,792" )
#define SET_MD_CTR(val) SET_REGISTER( "mtspr 792,%0", val )
#define GET_M_CASID() GET_REGISTER( "mfspr %0,793" )
#define SET_M_CASID(val) SET_REGISTER( "mtspr 793,%0", val )
#define GET_MD_AP() GET_REGISTER( "mfspr %0,794" )
#define SET_MD_AP(val) SET_REGISTER( "mtspr ,794%0", val )
#define GET_MD_EPN() GET_REGISTER( "mfspr %0,795" )
#define SET_MD_EPN(val) SET_REGISTER( "mtspr 795,%0", val )
#define GET_M_TWB() GET_REGISTER( "mfspr %0,796" )
#define SET_M_TWB(val) SET_REGISTER( "mtspr 796,%0", val )
#define GET_MD_TWC() GET_REGISTER( "mfspr %0,797" )
#define SET_MD_TWC(val) SET_REGISTER( "mtspr 797,%0", val )
#define GET_MD_RPN() GET_REGISTER( "mfspr %0,798" )
#define SET_MD_RPN(val) SET_REGISTER( "mtspr 798,%0", val )
#define GET_M_TW() GET_REGISTER( "mfspr %0,799" )
#define SET_M_TW(val) SET_REGISTER( "mtspr 799,%0", val )
#define GET_MI_DBCAM() GET_REGISTER( "mfspr %0,816" )
#define SET_MI_DBCAM(val) SET_REGISTER( "mtspr 816,%0", val )
#define GET_MI_DBRAM0() GET_REGISTER( "mfspr %0,817" )
#define SET_MI_DBRAM0(val) SET_REGISTER( "mtspr 817,%0", val )
#define GET_MI_DBRAM1() GET_REGISTER( "mfspr %0,818" )
#define SET_MI_DBRAM1(val) SET_REGISTER( "mtspr 818,%0", val )
#define GET_MD_DBCAM() GET_REGISTER( "mfspr %0,824" )
#define SET_MD_DBCA(val) SET_REGISTER( "mtspr 824,%0", val )
#define GET_MD_DBRAM0() GET_REGISTER( "mfspr %0,825" )
#define SET_MD_DBRAM0(val) SET_REGISTER( "mtspr 825,%0", val )
#define GET_MD_DBRAM1() GET_REGISTER( "mfspr %0,826" )
#define SET_MD_DBRAM1(val) SET_REGISTER( "mtspr 826,%0", val )
#define GET_ZPR() GET_REGISTER( "mfspr %0,944" )
#define SET_ZPR(val) SET_REGISTER( "mtspr 944,%0", val )
#define GET_PID() GET_REGISTER( "mfspr %0,945" )
#define SET_PID(val) SET_REGISTER( "mtspr 945,%0", val )
#define GET_CCR0() GET_REGISTER( "mfspr %0,947" )
#define SET_CCR0(val) SET_REGISTER( "mtspr 947,%0", val )
#define GET_IAC3() GET_REGISTER( "mfspr %0,948" )
#define SET_IAC3(val) SET_REGISTER( "mtspr 948,%0", val )
#define GET_IAC4() GET_REGISTER( "mfspr %0,949" )
#define SET_IAC4(val) SET_REGISTER( "mtspr 949,%0", val )
#define GET_DVC1() GET_REGISTER( "mfspr %0,950" )
#define SET_DVC1(val) SET_REGISTER( "mtspr 950,%0", val )
#define GET_DVC2() GET_REGISTER( "mfspr %0,951" )
#define SET_DVC2(val) SET_REGISTER( "mtspr 951,%0", val )
#define GET_SGR() GET_REGISTER( "mfspr %0,953" )
#define SET_SGR(val) SET_REGISTER( "mtspr 953,%0", val )
#define GET_DCWR() GET_REGISTER( "mfspr %0,954" )
#define SET_DCWR(val) SET_REGISTER( "mtspr 954,%0", val )
#define GET_SLER() GET_REGISTER( "mfspr %0,955" )
#define SET_SLER(val) SET_REGISTER( "mtspr 955,%0", val )
#define GET_SU0R() GET_REGISTER( "mfspr %0,956" )
#define SET_SU0R(val) SET_REGISTER( "mtspr 956,%0", val )
#define GET_DBCR1() GET_REGISTER( "mfspr %0,957" )
#define SET_DBCR1(val) SET_REGISTER( "mtspr 957,%0", val )
#define GET_ICDBDR() GET_REGISTER( "mfspr %0,979" )
#define SET_ICDBDR(val) SET_REGISTER( "mtspr 979,%0", val )
#define GET_ESR() GET_REGISTER( "mfspr %0,980" )
#define SET_ESR(val) SET_REGISTER( "mtspr 980,%0", val )
#define GET_DEAR() GET_REGISTER( "mfspr %0,981" )
#define SET_DEAR(val) SET_REGISTER( "mtspr 981,%0", val )
#define GET_EVPR() GET_REGISTER( "mfspr %0,982" )
#define SET_EVPR(val) SET_REGISTER( "mtspr 982,%0", val )
#define GET_TSR() GET_REGISTER( "mfspr %0,984" )
#define SET_TSR(val) SET_REGISTER( "mtspr 984,%0", val )
#define GET_TCR() GET_REGISTER( "mfspr %0,986" )
#define SET_TCR(val) SET_REGISTER( "mtspr 986,%0", val )
#define GET_PIT() GET_REGISTER( "mfspr %0,987" )
#define SET_PIT(val) SET_REGISTER( "mtspr 987,%0", val )
#define GET_SRR2() GET_REGISTER( "mfspr %0,990" )
#define SET_SRR2(val) SET_REGISTER( "mtspr 990,%0", val )
#define GET_SRR3() GET_REGISTER( "mfspr %0,991" )
#define SET_SRR3(val) SET_REGISTER( "mtspr 991,%0", val )
#define GET_DBSR() GET_REGISTER( "mfspr %0,1008" )
#define SET_DBSR(val) SET_REGISTER( "mtspr 1008,%0", val )
#define GET_DBCR0() GET_REGISTER( "mfspr %0,1010" )
#define SET_DBCR0(val) SET_REGISTER( "mtspr 1010,%0", val )
#define GET_IABR() GET_REGISTER( "mfspr %0,1010" )
#define SET_IABR(val) SET_REGISTER( "mtspr 1010,%0", val )
#define GET_IAC1() GET_REGISTER( "mfspr %0,1012" )
#define SET_IAC1(val) SET_REGISTER( "mtspr 1012,%0", val )
#define GET_IAC2() GET_REGISTER( "mfspr %0,1013" )
#define SET_IAC2(val) SET_REGISTER( "mtspr 1013,%0", val )
#define GET_DAC1() GET_REGISTER( "mfspr %0,1014" )
#define SET_DAC1(val) SET_REGISTER( "mtspr 1014,%0", val )
#define GET_DAC2() GET_REGISTER( "mfspr %0,1015" )
#define SET_DAC2(val) SET_REGISTER( "mtspr 1015,%0", val )
#define GET_DCCR() GET_REGISTER( "mfspr %0,1018" )
#define SET_DCCR(val) SET_REGISTER( "mtspr 1018,%0", val )
#define GET_ICCR() GET_REGISTER( "mfspr %0,1019" )
#define SET_ICCR(val) SET_REGISTER( "mtspr 1019,%0", val )
#endif /* _REGS_H */
/*
* Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
* All rights reserved.
*
* Redistribution and use in source and binary forms are freely
* permitted provided that the above copyright notice and this
* paragraph and the following disclaimer are duplicated in all
* such forms.
*
* This software is provided "AS IS" and without any express or
* implied warranties, including, without limitation, the implied
* warranties of merchantability and fitness for a particular
* purpose.
*/

601
include/bedbug/tables.h
View File

@ -1,601 +0,0 @@
/* $Id$ */
#ifndef TABLES_H
#define TABLES_H
/* This is only included by common/bedbug.c, and depends on the following
* files to already be included
* common.h
* bedbug/bedbug.h
* bedbug/ppc.h
* bedbug/regs.h
*/
struct operand operands[] = {
/*Field Name Bits Shift Hint Position */
/*----- ------ ----- ----- ---- ------------ */
{ O_AA, "O_AA", 1, 1, OH_SILENT }, /* 30 */
{ O_BD, "O_BD", 14, 2, OH_ADDR }, /* 16-29 */
{ O_BI, "O_BI", 5, 16, 0 }, /* 11-15 */
{ O_BO, "O_BO", 5, 21, 0 }, /* 6-10 */
{ O_crbD, "O_crbD", 5, 21, 0 }, /* 6-10 */
{ O_crbA, "O_crbA", 5, 16, 0 }, /* 11-15 */
{ O_crbB, "O_crbB", 5, 11, 0 }, /* 16-20 */
{ O_CRM, "O_CRM", 8, 12, 0 }, /* 12-19 */
{ O_d, "O_d", 15, 0, OH_OFFSET }, /* 16-31 */
{ O_frC, "O_frC", 5, 6, 0 }, /* 21-25 */
{ O_frD, "O_frD", 5, 21, 0 }, /* 6-10 */
{ O_frS, "O_frS", 5, 21, 0 }, /* 6-10 */
{ O_IMM, "O_IMM", 4, 12, 0 }, /* 16-19 */
{ O_LI, "O_LI", 24, 2, OH_ADDR }, /* 6-29 */
{ O_LK, "O_LK", 1, 0, OH_SILENT }, /* 31 */
{ O_MB, "O_MB", 5, 6, 0 }, /* 21-25 */
{ O_ME, "O_ME", 5, 1, 0 }, /* 26-30 */
{ O_NB, "O_NB", 5, 11, 0 }, /* 16-20 */
{ O_OE, "O_OE", 1, 10, OH_SILENT }, /* 21 */
{ O_rA, "O_rA", 5, 16, OH_REG }, /* 11-15 */
{ O_rB, "O_rB", 5, 11, OH_REG }, /* 16-20 */
{ O_Rc, "O_Rc", 1, 0, OH_SILENT }, /* 31 */
{ O_rD, "O_rD", 5, 21, OH_REG }, /* 6-10 */
{ O_rS, "O_rS", 5, 21, OH_REG }, /* 6-10 */
{ O_SH, "O_SH", 5, 11, 0 }, /* 16-20 */
{ O_SIMM, "O_SIMM", 16, 0, 0 }, /* 16-31 */
{ O_SR, "O_SR", 4, 16, 0 }, /* 12-15 */
{ O_TO, "O_TO", 5, 21, 0 }, /* 6-10 */
{ O_UIMM, "O_UIMM", 16, 0, 0 }, /* 16-31 */
{ O_crfD, "O_crfD", 3, 23, 0 }, /* 6- 8 */
{ O_crfS, "O_crfS", 3, 18, 0 }, /* 11-13 */
{ O_L, "O_L", 1, 21, 0 }, /* 10 */
{ O_spr, "O_spr", 10, 11, OH_SPR }, /* 11-20 */
{ O_tbr, "O_tbr", 10, 11, OH_TBR }, /* 11-20 */
{ O_cr2, "O_cr2", 0, 0, OH_LITERAL }, /* "cr2" */
};
const unsigned int n_operands = sizeof(operands) / sizeof(operands[0]);
/* A note about the fields array in the opcodes structure:
The operands are listed in the order they appear in the output.
This table is arranged in numeric order of the opcode. Note that some
opcodes have defined bits in odd places so not all forms of a command
will be in the same place. This is done so that a binary search can be
done to find the opcodes. Note that table D.2 in the MPC860 User's
Manual "Instructions Sorted by Opcode" does not account for these
bit locations */
struct opcode opcodes[] = {
{ D_OPCODE(3), D_MASK, {O_TO, O_rA, O_SIMM, 0},
0, "twi", 0 },
{ D_OPCODE(7), D_MASK, {O_rD, O_rA, O_SIMM, 0},
0, "mulli", 0 },
{ D_OPCODE(8), D_MASK, {O_rD, O_rA, O_SIMM, 0},
0, "subfic", 0 },
{ D_OPCODE(10), D_MASK, {O_crfD, O_L, O_rA, O_UIMM, 0},
0, "cmpli", 0 },
{ D_OPCODE(11), D_MASK, {O_crfD, O_L, O_rA, O_SIMM, 0},
0, "cmpi", 0 },
{ D_OPCODE(12), D_MASK, {O_rD, O_rA, O_SIMM, 0},
0, "addic", 0 },
{ D_OPCODE(13), D_MASK, {O_rD, O_rA, O_SIMM, 0},
0, "addic.", 0 },
{ D_OPCODE(14), D_MASK, {O_rD, O_rA, O_SIMM, 0},
0, "addi", H_RA0_IS_0 },
{ D_OPCODE(15), D_MASK, {O_rD, O_rA, O_SIMM, 0},
0, "addis", H_RA0_IS_0|H_IMM_HIGH },
{ B_OPCODE(16,0,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
handle_bc, "bc", H_RELATIVE },
{ B_OPCODE(16,0,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
0, "bcl", H_RELATIVE },
{ B_OPCODE(16,1,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
0, "bca", 0 },
{ B_OPCODE(16,1,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
0, "bcla", 0 },
{ SC_OPCODE(17), SC_MASK, {0},
0, "sc", 0 },
{ I_OPCODE(18,0,0), I_MASK, {O_LI, O_AA, O_LK, 0},
0, "b", H_RELATIVE },
{ I_OPCODE(18,0,1), I_MASK, {O_LI, O_AA, O_LK, 0},
0, "bl", H_RELATIVE },
{ I_OPCODE(18,1,0), I_MASK, {O_LI, O_AA, O_LK, 0},
0, "ba", 0 },
{ I_OPCODE(18,1,1), I_MASK, {O_LI, O_AA, O_LK, 0},
0, "bla", 0 },
{ XL_OPCODE(19,0,0), XL_MASK, {O_crfD, O_crfS},
0, "mcrf", 0 },
{ XL_OPCODE(19,16,0), XL_MASK, {O_BO, O_BI, O_LK, 0},
0, "bclr", 0 },
{ XL_OPCODE(19,16,1), XL_MASK, {O_BO, O_BI, O_LK, 0},
0, "bclrl", 0 },
{ XL_OPCODE(19,33,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
0, "crnor", 0 },
{ XL_OPCODE(19,50,0), XL_MASK, {0},
0, "rfi", 0 },
{ XL_OPCODE(19,129,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
0, "crandc", 0 },
{ XL_OPCODE(19,150,0), XL_MASK, {0},
0, "isync", 0 },
{ XL_OPCODE(19,193,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
0, "crxor", 0 },
{ XL_OPCODE(19,225,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
0, "crnand", 0 },
{ XL_OPCODE(19,257,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
0, "crand", 0 },
{ XL_OPCODE(19,289,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
0, "creqv", 0 },
{ XL_OPCODE(19,417,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
0, "crorc", 0 },
{ XL_OPCODE(19,449,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
0, "cror", 0 },
{ XL_OPCODE(19,528,0), XL_MASK, {O_BO, O_BI, O_LK, 0},
0, "bcctr", 0 },
{ XL_OPCODE(19,528,1), XL_MASK, {O_BO, O_BI, O_LK, 0},
0, "bcctrl", 0 },
{ M_OPCODE(20,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
0, "rlwimi", 0 },
{ M_OPCODE(20,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
0, "rlwimi.", 0 },
{ M_OPCODE(21,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
0, "rlwinm", 0 },
{ M_OPCODE(21,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
0, "rlwinm.", 0 },
{ M_OPCODE(23,0), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
0, "rlwnm", 0 },
{ M_OPCODE(23,1), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
0, "rlwnm.", 0 },
{ D_OPCODE(24), D_MASK, {O_rA, O_rS, O_UIMM, 0},
0, "ori", 0 },
{ D_OPCODE(25), D_MASK, {O_rA, O_rS, O_UIMM, 0},
0, "oris", H_IMM_HIGH },
{ D_OPCODE(26), D_MASK, {O_rA, O_rS, O_UIMM, 0},
0, "xori", 0 },
{ D_OPCODE(27), D_MASK, {O_rA, O_rS, O_UIMM, 0},
0, "xoris", H_IMM_HIGH },
{ D_OPCODE(28), D_MASK, {O_rA, O_rS, O_UIMM, 0},
0, "andi.", 0 },
{ D_OPCODE(29), D_MASK, {O_rA, O_rS, O_UIMM, 0},
0, "andis.", H_IMM_HIGH },
{ X_OPCODE(31,0,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0},
0, "cmp", 0 },
{ X_OPCODE(31,4,0), X_MASK, {O_TO, O_rA, O_rB, 0},
0, "tw", 0 },
{ XO_OPCODE(31,8,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "subfc", 0 },
{ XO_OPCODE(31,8,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "subfc.", 0 },
{ XO_OPCODE(31,10,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "addc", 0 },
{ XO_OPCODE(31,10,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "addc.", 0 },
{ XO_OPCODE(31,11,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0},
0, "mulhwu", 0 },
{ XO_OPCODE(31,11,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0},
0, "mulhwu.", 0 },
{ X_OPCODE(31,19,0), X_MASK, {O_rD, 0},
0, "mfcr", 0 },
{ X_OPCODE(31,20,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "lwarx", H_RA0_IS_0 },
{ X_OPCODE(31,23,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "lwzx", H_RA0_IS_0 },
{ X_OPCODE(31,24,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "slw", 0 },
{ X_OPCODE(31,24,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "slw.", 0 },
{ X_OPCODE(31,26,0), X_MASK, {O_rA, O_rS, O_Rc, 0 },
0, "cntlzw", 0 },
{ X_OPCODE(31,26,1), X_MASK, {O_rA, O_rS, O_Rc, 0},
0, "cntlzw.", 0 },
{ X_OPCODE(31,28,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "and", 0 },
{ X_OPCODE(31,28,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "and.", 0 },
{ X_OPCODE(31,32,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0},
0, "cmpl", 0 },
{ XO_OPCODE(31,40,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "subf", 0 },
{ XO_OPCODE(31,40,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "subf.", 0 },
{ X_OPCODE(31,54,0), X_MASK, {O_rA, O_rB, 0},
0, "dcbst", H_RA0_IS_0 },
{ X_OPCODE(31,55,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "lwzux", 0 },
{ X_OPCODE(31,60,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "andc", 0 },
{ X_OPCODE(31,60,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "andc.", 0 },
{ XO_OPCODE(31,75,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0},
0, "mulhw", 0 },
{ XO_OPCODE(31,75,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0},
0, "mulhw.", 0 },
{ X_OPCODE(31,83,0), X_MASK, {O_rD, 0},
0, "mfmsr", 0 },
{ X_OPCODE(31,86,0), X_MASK, {O_rA, O_rB, 0},
0, "dcbf", H_RA0_IS_0 },
{ X_OPCODE(31,87,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "lbzx", H_RA0_IS_0 },
{ XO_OPCODE(31,104,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "neg", 0 },
{ XO_OPCODE(31,104,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "neg.", 0 },
{ X_OPCODE(31,119,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "lbzux", 0 },
{ X_OPCODE(31,124,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "nor", 0 },
{ X_OPCODE(31,124,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "nor.", 0 },
{ XO_OPCODE(31,136,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "subfe", 0 },
{ XO_OPCODE(31,136,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "subfe.", 0 },
{ XO_OPCODE(31,138,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "adde", 0 },
{ XO_OPCODE(31,138,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "adde.", 0 },
{ XFX_OPCODE(31,144,0), XFX_MASK, {O_CRM, O_rS, 0},
0, "mtcrf", 0 },
{ X_OPCODE(31,146,0), X_MASK, {O_rS, 0},
0, "mtmsr", 0 },
{ X_OPCODE(31,150,1), X_MASK, {O_rS, O_rA, O_rB, 0},
0, "stwcx.", 0 },
{ X_OPCODE(31,151,0), X_MASK, {O_rS, O_rA, O_rB, 0},
0, "stwx", 0 },
{ X_OPCODE(31,183,0), X_MASK, {O_rS, O_rA, O_rB, 0},
0, "stwux", 0 },
{ XO_OPCODE(31,200,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "subfze", 0 },
{ XO_OPCODE(31,200,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "subfze.", 0 },
{ XO_OPCODE(31,202,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "addze", 0 },
{ XO_OPCODE(31,202,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "addze.", 0 },
{ X_OPCODE(31,210,0), X_MASK, {O_SR, O_rS, 0},
0, "mtsr", 0 },
{ X_OPCODE(31,215,0), X_MASK, {O_rS, O_rA, O_rB, 0},
0, "stbx", H_RA0_IS_0 },
{ XO_OPCODE(31,232,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "subfme", 0 },
{ XO_OPCODE(31,232,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "subfme.", 0 },
{ XO_OPCODE(31,234,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "addme", 0 },
{ XO_OPCODE(31,234,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "addme.", 0 },
{ XO_OPCODE(31,235,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "mullw", 0 },
{ XO_OPCODE(31,235,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "mullw.", 0 },
{ X_OPCODE(31,242,0), X_MASK, {O_rS, O_rB, 0},
0, "mtsrin", 0 },
{ X_OPCODE(31,246,0), X_MASK, {O_rA, O_rB, 0},
0, "dcbtst", H_RA0_IS_0 },
{ X_OPCODE(31,247,0), X_MASK, {O_rS, O_rA, O_rB, 0},
0, "stbux", 0 },
{ XO_OPCODE(31,266,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "add", 0 },
{ XO_OPCODE(31,266,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "add.", 0 },
{ X_OPCODE(31,278,0), X_MASK, {O_rA, O_rB, 0},
0, "dcbt", H_RA0_IS_0 },
{ X_OPCODE(31,279,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "lhzx", H_RA0_IS_0 },
{ X_OPCODE(31,284,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "eqv", 0 },
{ X_OPCODE(31,284,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "eqv.", 0 },
{ X_OPCODE(31,306,0), X_MASK, {O_rB, 0},
0, "tlbie", 0 },
{ X_OPCODE(31,310,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "eciwx", H_RA0_IS_0 },
{ X_OPCODE(31,311,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "lhzux", 0 },
{ X_OPCODE(31,316,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "xor", 0 },
{ X_OPCODE(31,316,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "xor.", 0 },
{ XFX_OPCODE(31,339,0), XFX_MASK, {O_rD, O_spr, 0},
0, "mfspr", 0 },
{ X_OPCODE(31,343,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "lhax", H_RA0_IS_0 },
{ X_OPCODE(31,370,0), X_MASK, {0},
0, "tlbia", 0 },
{ XFX_OPCODE(31,371,0), XFX_MASK, {O_rD, O_tbr, 0},
0, "mftb", 0 },
{ X_OPCODE(31,375,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "lhaux", 0 },
{ X_OPCODE(31,407,0), X_MASK, {O_rS, O_rA, O_rB, 0},
0, "sthx", H_RA0_IS_0 },
{ X_OPCODE(31,412,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "orc", 0 },
{ X_OPCODE(31,412,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "orc.", 0 },
{ X_OPCODE(31,438,0), X_MASK, {O_rS, O_rA, O_rB, 0},
0, "ecowx", H_RA0_IS_0 },
{ X_OPCODE(31,439,0), X_MASK, {O_rS, O_rA, O_rB, 0},
0, "sthux", 0 },
{ X_OPCODE(31,444,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "or", 0 },
{ X_OPCODE(31,444,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "or.", 0 },
{ XO_OPCODE(31,459,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "divwu", 0 },
{ XO_OPCODE(31,459,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "divwu.", 0 },
{ XFX_OPCODE(31,467,0), XFX_MASK, {O_spr, O_rS, 0},
0, "mtspr", 0 },
{ X_OPCODE(31,470,0), X_MASK, {O_rA, O_rB, 0},
0, "dcbi", H_RA0_IS_0 },
{ X_OPCODE(31,476,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "nand", 0 },
{ X_OPCODE(31,476,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc,0},
0, "nand.", 0 },
{ XO_OPCODE(31,491,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "divw", 0 },
{ XO_OPCODE(31,491,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "divw.", 0 },
{ X_OPCODE(31,512,0), X_MASK, {O_crfD, 0},
0, "mcrxr", 0 },
{ XO_OPCODE(31,8,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "subfco", 0 },
{ XO_OPCODE(31,8,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "subfco.", 0 },
{ XO_OPCODE(31,10,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "addco", 0 },
{ XO_OPCODE(31,10,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "addco.", 0 },
{ X_OPCODE(31,533,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "lswx", H_RA0_IS_0 },
{ X_OPCODE(31,534,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "lwbrx", H_RA0_IS_0 },
{ X_OPCODE(31,536,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "srw", 0 },
{ X_OPCODE(31,536,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "srw.", 0 },
{ XO_OPCODE(31,40,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "subfo", 0 },
{ XO_OPCODE(31,40,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "subfo.", 0 },
{ X_OPCODE(31,566,0), X_MASK, {0},
0, "tlbsync", 0 },
{ X_OPCODE(31,595,0), X_MASK, {O_rD, O_SR, 0},
0, "mfsr", 0 },
{ X_OPCODE(31,597,0), X_MASK, {O_rD, O_rA, O_NB, 0},
0, "lswi", H_RA0_IS_0 },
{ X_OPCODE(31,598,0), X_MASK, {0},
0, "sync", 0 },
{ XO_OPCODE(31,104,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "nego", 0 },
{ XO_OPCODE(31,104,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "nego.", 0 },
{ XO_OPCODE(31,136,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "subfeo", 0 },
{ XO_OPCODE(31,136,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "subfeo.", 0 },
{ XO_OPCODE(31,138,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "addeo", 0 },
{ XO_OPCODE(31,138,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "addeo.", 0 },
{ X_OPCODE(31,659,0), X_MASK, {O_rD, O_rB, 0},
0, "mfsrin", 0 },
{ X_OPCODE(31,661,0), X_MASK, {O_rS, O_rA, O_rB, 0},
0, "stswx", H_RA0_IS_0 },
{ X_OPCODE(31,662,0), X_MASK, {O_rS, O_rA, O_rB, 0},
0, "stwbrx", H_RA0_IS_0 },
{ XO_OPCODE(31,200,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "subfzeo", 0 },
{ XO_OPCODE(31,200,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "subfzeo.", 0 },
{ XO_OPCODE(31,202,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "addzeo", 0 },
{ XO_OPCODE(31,202,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "addzeo.", 0 },
{ X_OPCODE(31,725,0), X_MASK, {O_rS, O_rA, O_NB, 0},
0, "stswi", H_RA0_IS_0 },
{ XO_OPCODE(31,232,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "subfmeo", 0 },
{ XO_OPCODE(31,232,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "subfmeo.", 0 },
{ XO_OPCODE(31,234,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "addmeo", 0 },
{ XO_OPCODE(31,234,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "addmeo.", 0 },
{ XO_OPCODE(31,235,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "mullwo", 0 },
{ XO_OPCODE(31,235,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "mullwo.", 0 },
{ XO_OPCODE(31,266,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "addo", 0 },
{ XO_OPCODE(31,266,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "addo.", 0 },
{ X_OPCODE(31,790,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "lhbrx", H_RA0_IS_0 },
{ X_OPCODE(31,792,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "sraw", 0 },
{ X_OPCODE(31,792,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "sraw.", 0 },
{ X_OPCODE(31,824,0), X_MASK, {O_rA, O_rS, O_SH, O_Rc, 0},
0, "srawi", 0 },
{ X_OPCODE(31,824,1), X_MASK, {O_rA, O_rS, O_SH, O_Rc, 0},
0, "srawi.", 0 },
{ X_OPCODE(31,854,0), X_MASK, {0},
0, "eieio", 0 },
{ X_OPCODE(31,918,0), X_MASK, {O_rS, O_rA, O_rB, 0},
0, "sthbrx", H_RA0_IS_0 },
{ X_OPCODE(31,922,0), X_MASK, {O_rA, O_rS, O_Rc, 0},
0, "extsh", 0 },
{ X_OPCODE(31,922,1), X_MASK, {O_rA, O_rS, O_Rc, 0},
0, "extsh.", 0 },
{ X_OPCODE(31,954,0), X_MASK, {O_rA, O_rS, O_Rc, 0},
0, "extsb", 0 },
{ X_OPCODE(31,954,1), X_MASK, {O_rA, O_rS, O_Rc, 0},
0, "extsb.", 0 },
{ XO_OPCODE(31,459,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "divwuo", 0 },
{ XO_OPCODE(31,459,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "divwuo.", 0 },
{ X_OPCODE(31,978,0), X_MASK, {O_rB, 0},
0, "tlbld", 0 },
{ X_OPCODE(31,982,0), X_MASK, {O_rA, O_rB, 0},
0, "icbi", H_RA0_IS_0 },
{ XO_OPCODE(31,491,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "divwo", 0 },
{ XO_OPCODE(31,491,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "divwo.", 0 },
{ X_OPCODE(31,1010,0), X_MASK, {O_rB, 0},
0, "tlbli", 0 },
{ X_OPCODE(31,1014,0), X_MASK, {O_rA, O_rB, 0},
0, "dcbz", H_RA0_IS_0 },
{ D_OPCODE(32), D_MASK, {O_rD, O_d, O_rA, 0},
0, "lwz", H_RA0_IS_0 },
{ D_OPCODE(33), D_MASK, {O_rD, O_d, O_rA, 0},
0, "lwzu", 0 },
{ D_OPCODE(34), D_MASK, {O_rD, O_d, O_rA, 0},
0, "lbz", H_RA0_IS_0 },
{ D_OPCODE(35), D_MASK, {O_rD, O_d, O_rA, 0},
0, "lbzu", 0 },
{ D_OPCODE(36), D_MASK, {O_rS, O_d, O_rA, 0},
0, "stw", H_RA0_IS_0 },
{ D_OPCODE(37), D_MASK, {O_rS, O_d, O_rA, 0},
0, "stwu", 0 },
{ D_OPCODE(38), D_MASK, {O_rS, O_d, O_rA, 0},
0, "stb", H_RA0_IS_0 },
{ D_OPCODE(39), D_MASK, {O_rS, O_d, O_rA, 0},
0, "stbu", 0 },
{ D_OPCODE(40), D_MASK, {O_rD, O_d, O_rA, 0},
0, "lhz", H_RA0_IS_0 },
{ D_OPCODE(41), D_MASK, {O_rD, O_d, O_rA, 0},
0, "lhzu", 0 },
{ D_OPCODE(42), D_MASK, {O_rD, O_d, O_rA, 0},
0, "lha", H_RA0_IS_0 },
{ D_OPCODE(43), D_MASK, {O_rD, O_d, O_rA, 0},
0, "lhau", 0 },
{ D_OPCODE(44), D_MASK, {O_rS, O_d, O_rA, 0},
0, "sth", H_RA0_IS_0 },
{ D_OPCODE(45), D_MASK, {O_rS, O_d, O_rA, 0},
0, "sthu", 0 },
{ D_OPCODE(46), D_MASK, {O_rD, O_d, O_rA, 0},
0, "lmw", H_RA0_IS_0 },
{ D_OPCODE(47), D_MASK, {O_rS, O_d, O_rA, 0},
0, "stmw", H_RA0_IS_0 },
};
const unsigned int n_opcodes = sizeof(opcodes) / sizeof(opcodes[0]);
struct spr_info spr_map[] = {
{ SPR_XER, "XER" },
{ SPR_LR, "LR" },
{ SPR_CTR, "CTR" },
{ SPR_DSISR, "DSISR" },
{ SPR_DAR, "DAR" },
{ SPR_DEC, "DEC" },
{ SPR_SRR0, "SRR0" },
{ SPR_SRR1, "SRR1" },
{ SPR_EIE, "EIE" },
{ SPR_EID, "EID" },
{ SPR_CMPA, "CMPA" },
{ SPR_CMPB, "CMPB" },
{ SPR_CMPC, "CMPC" },
{ SPR_CMPD, "CMPD" },
{ SPR_ICR, "ICR" },
{ SPR_DER, "DER" },
{ SPR_COUNTA, "COUNTA" },
{ SPR_COUNTB, "COUNTB" },
{ SPR_CMPE, "CMPE" },
{ SPR_CMPF, "CMPF" },
{ SPR_CMPG, "CMPG" },
{ SPR_CMPH, "CMPH" },
{ SPR_LCTRL1, "LCTRL1" },
{ SPR_LCTRL2, "LCTRL2" },
{ SPR_ICTRL, "ICTRL" },
{ SPR_BAR, "BAR" },
{ SPR_USPRG0, "USPRG0" },
{ SPR_SPRG4_RO, "SPRG4_RO" },
{ SPR_SPRG5_RO, "SPRG5_RO" },
{ SPR_SPRG6_RO, "SPRG6_RO" },
{ SPR_SPRG7_RO, "SPRG7_RO" },
{ SPR_SPRG0, "SPRG0" },
{ SPR_SPRG1, "SPRG1" },
{ SPR_SPRG2, "SPRG2" },
{ SPR_SPRG3, "SPRG3" },
{ SPR_SPRG4, "SPRG4" },
{ SPR_SPRG5, "SPRG5" },
{ SPR_SPRG6, "SPRG6" },
{ SPR_SPRG7, "SPRG7" },
{ SPR_EAR, "EAR" },
{ SPR_TBL, "TBL" },
{ SPR_TBU, "TBU" },
{ SPR_IC_CST, "IC_CST" },
{ SPR_IC_ADR, "IC_ADR" },
{ SPR_IC_DAT, "IC_DAT" },
{ SPR_DC_CST, "DC_CST" },
{ SPR_DC_ADR, "DC_ADR" },
{ SPR_DC_DAT, "DC_DAT" },
{ SPR_DPDR, "DPDR" },
{ SPR_IMMR, "IMMR" },
{ SPR_MI_CTR, "MI_CTR" },
{ SPR_MI_AP, "MI_AP" },
{ SPR_MI_EPN, "MI_EPN" },
{ SPR_MI_TWC, "MI_TWC" },
{ SPR_MI_RPN, "MI_RPN" },
{ SPR_MD_CTR, "MD_CTR" },
{ SPR_M_CASID, "M_CASID" },
{ SPR_MD_AP, "MD_AP" },
{ SPR_MD_EPN, "MD_EPN" },
{ SPR_M_TWB, "M_TWB" },
{ SPR_MD_TWC, "MD_TWC" },
{ SPR_MD_RPN, "MD_RPN" },
{ SPR_M_TW, "M_TW" },
{ SPR_MI_DBCAM, "MI_DBCAM" },
{ SPR_MI_DBRAM0, "MI_DBRAM0" },
{ SPR_MI_DBRAM1, "MI_DBRAM1" },
{ SPR_MD_DBCAM, "MD_DBCAM" },
{ SPR_MD_DBRAM0, "MD_DBRAM0" },
{ SPR_MD_DBRAM1, "MD_DBRAM1" },
{ SPR_ZPR, "ZPR" },
{ SPR_PID, "PID" },
{ SPR_CCR0, "CCR0" },
{ SPR_IAC3, "IAC3" },
{ SPR_IAC4, "IAC4" },
{ SPR_DVC1, "DVC1" },
{ SPR_DVC2, "DVC2" },
{ SPR_SGR, "SGR" },
{ SPR_DCWR, "DCWR" },
{ SPR_SLER, "SLER" },
{ SPR_SU0R, "SU0R" },
{ SPR_DBCR1, "DBCR1" },
{ SPR_ICDBDR, "ICDBDR" },
{ SPR_ESR, "ESR" },
{ SPR_DEAR, "DEAR" },
{ SPR_EVPR, "EVPR" },
{ SPR_TSR, "TSR" },
{ SPR_TCR, "TCR" },
{ SPR_PIT, "PIT" },
{ SPR_SRR2, "SRR2" },
{ SPR_SRR3, "SRR3" },
{ SPR_DBSR, "DBSR" },
{ SPR_DBCR0, "DBCR0" },
{ SPR_IAC1, "IAC1" },
{ SPR_IAC2, "IAC2" },
{ SPR_DAC1, "DAC1" },
{ SPR_DAC2, "DAC2" },
{ SPR_DCCR, "DCCR" },
{ SPR_ICCR, "ICCR" },
};
const unsigned int n_sprs = sizeof(spr_map) / sizeof(spr_map[0]);
#endif
/*
* Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
* All rights reserved.
*
* Redistribution and use in source and binary forms are freely
* permitted provided that the above copyright notice and this
* paragraph and the following disclaimer are duplicated in all
* such forms.
*
* This software is provided "AS IS" and without any express or
* implied warranties, including, without limitation, the implied
* warranties of merchantability and fitness for a particular
* purpose.
*/

1818
include/commproc.h
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File diff suppressed because it is too large Load Diff

105
include/dtt.h
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@ -1,105 +0,0 @@
/*
* (C) Copyright 2001
* Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Digital Thermometers and Thermostats.
*/
#ifndef _DTT_H_
#define _DTT_H_
#if defined(CONFIG_DTT_LM75) || \
defined(CONFIG_DTT_DS1621) || \
defined(CONFIG_DTT_ADM1021)
#define CONFIG_DTT /* We have a DTT */
#ifndef CONFIG_DTT_ADM1021
#define DTT_COMMERCIAL_MAX_TEMP 70 /* 0 - +70 C */
#define DTT_INDUSTRIAL_MAX_TEMP 85 /* -40 - +85 C */
#define DTT_AUTOMOTIVE_MAX_TEMP 105 /* -40 - +105 C */
#ifndef CFG_DTT_MAX_TEMP
#define CFG_DTT_MAX_TEMP DTT_COMMERCIAL_MAX_TEMP
#endif
#ifndef CFG_DTT_HYSTERESIS
#define CFG_DTT_HYSTERESIS 5 /* 5 C */
#endif
#endif /* CONFIG_DTT_ADM1021 */
extern int dtt_init (void);
extern int dtt_read(int sensor, int reg);
extern int dtt_write(int sensor, int reg, int val);
extern int dtt_get_temp(int sensor);
#endif
#if defined(CONFIG_DTT_LM75)
#define DTT_READ_TEMP 0x0
#define DTT_CONFIG 0x1
#define DTT_TEMP_HYST 0x2
#define DTT_TEMP_SET 0x3
#endif
#if defined(CONFIG_DTT_DS1621)
#define DTT_READ_TEMP 0xAA
#define DTT_READ_COUNTER 0xA8
#define DTT_READ_SLOPE 0xA9
#define DTT_WRITE_START_CONV 0xEE
#define DTT_WRITE_STOP_CONV 0x22
#define DTT_TEMP_HIGH 0xA1
#define DTT_TEMP_LOW 0xA2
#define DTT_CONFIG 0xAC
#endif
#if defined(CONFIG_DTT_ADM1021)
#define DTT_READ_LOC_VALUE 0x00
#define DTT_READ_REM_VALUE 0x01
#define DTT_READ_STATUS 0x02
#define DTT_READ_CONFIG 0x03
#define DTT_READ_CONVRATE 0x04
#define DTT_READ_LOC_HIGHLIM 0x05
#define DTT_READ_LOC_LOWLIM 0x06
#define DTT_READ_REM_HIGHLIM 0x07
#define DTT_READ_REM_LOWLIM 0x08
#define DTT_READ_DEVID 0xfe
#define DTT_WRITE_CONFIG 0x09
#define DTT_WRITE_CONVRATE 0x0a
#define DTT_WRITE_LOC_HIGHLIM 0x0b
#define DTT_WRITE_LOC_LOWLIM 0x0c
#define DTT_WRITE_REM_HIGHLIM 0x0d
#define DTT_WRITE_REM_LOWLIM 0x0e
#define DTT_WRITE_ONESHOT 0x0f
#define DTT_STATUS_BUSY 0x80 /* 1=ADC Converting */
#define DTT_STATUS_LHIGH 0x40 /* 1=Local High Temp Limit Tripped */
#define DTT_STATUS_LLOW 0x20 /* 1=Local Low Temp Limit Tripped */
#define DTT_STATUS_RHIGH 0x10 /* 1=Remote High Temp Limit Tripped */
#define DTT_STATUS_RLOW 0x08 /* 1=Remote Low Temp Limit Tripped */
#define DTT_STATUS_OPEN 0x04 /* 1=Remote Sensor Open-Circuit */
#define DTT_CONFIG_ALERT_MASKED 0x80 /* 0=ALERT Enabled, 1=ALERT Masked */
#define DTT_CONFIG_STANDBY 0x40 /* 0=Run, 1=Standby */
#define DTT_ADM1021_DEVID 0x41
#endif
#endif /* _DTT_H_ */

37
include/fdc.h
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/*
* (C) Copyright 2002
* Stäubli Faverges - <www.staubli.com>
* Pierre AUBERT p.aubert@staubli.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _FDC_H_
#define _FDC_H_
/* Functions prototype */
int fdc_fdos_init (int drive);
int fdc_fdos_seek (int where);
int fdc_fdos_read (void *buffer, int len);
int dos_open(char *name);
int dos_read (ulong addr);
int dos_dir (void);
#endif

129
include/i2c.h
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@ -1,129 +0,0 @@
/*
* (C) Copyright 2001
* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* The original I2C interface was
* (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
* AIRVENT SAM s.p.a - RIMINI(ITALY)
* but has been changed substantially.
*/
#ifndef _I2C_H_
#define _I2C_H_
/*
* WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
*
* The implementation MUST NOT use static or global variables if the
* I2C routines are used to read SDRAM configuration information
* because this is done before the memories are initialized. Limited
* use of stack-based variables are OK (the initial stack size is
* limited).
*
* WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
*/
/*
* Configuration items.
*/
#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
/*
* Initialization, must be called once on start up, may be called
* repeatedly to change the speed and slave addresses.
*/
#ifdef CFG_I2C_INIT_BOARD
void i2c_init_board(void);
#endif
/*
* Probe the given I2C chip address. Returns 0 if a chip responded,
* not 0 on failure.
*/
int i2c_probe(uchar chip);
/*
* Read/Write interface:
* chip: I2C chip address, range 0..127
* addr: Memory (register) address within the chip
* alen: Number of bytes to use for addr (typically 1, 2 for larger
* memories, 0 for register type devices with only one
* register)
* buffer: Where to read/write the data
* len: How many bytes to read/write
*
* Returns: 0 on success, not 0 on failure
*/
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
/*
* Utility routines to read/write registers.
*/
uchar i2c_reg_read (uchar chip, uchar reg);
void i2c_reg_write(uchar chip, uchar reg, uchar val);
/*
* Functions for setting the current I2C bus and its speed
*/
/*
* i2c_set_bus_num:
*
* Change the active I2C bus. Subsequent read/write calls will
* go to this one.
*
* bus - bus index, zero based
*
* Returns: 0 on success, not 0 on failure
*
*/
int i2c_set_bus_num(unsigned int bus);
/*
* i2c_get_bus_num:
*
* Returns index of currently active I2C bus. Zero-based.
*/
unsigned int i2c_get_bus_num(void);
/*
* i2c_set_bus_speed:
*
* Change the speed of the active I2C bus
*
* speed - bus speed in Hz
*
* Returns: 0 on success, not 0 on failure
*
*/
int i2c_set_bus_speed(unsigned int);
/*
* i2c_get_bus_speed:
*
* Returns speed of currently active I2C bus in Hz
*/
unsigned int i2c_get_bus_speed(void);
#endif /* _I2C_H_ */

76
include/i8042.h
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/*
* (C) Copyright 2002 ELTEC Elektronik AG
* Frank Gottschling <fgottschling@eltec.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* i8042.h - Intel 8042 keyboard driver header */
#ifndef _I8042_H_
#define _I8042_H_
#ifdef __I386__
#include <common.h>
#include <asm/io.h>
#define in8(p) inb(p)
#define out8(p,v) outb(v,p)
#endif
/* defines */
#define I8042_DATA_REG (CFG_ISA_IO + 0x0060) /* keyboard i/o buffer */
#define I8042_STATUS_REG (CFG_ISA_IO + 0x0064) /* keyboard status read */
#define I8042_COMMAND_REG (CFG_ISA_IO + 0x0064) /* keyboard ctrl write */
#define KBD_US 0 /* default US layout */
#define KBD_GER 1 /* german layout */
#define KBD_TIMEOUT 1000 /* 1 sec */
#define KBD_RESET_TRIES 3
#define AS 0 /* normal character index */
#define SH 1 /* shift index */
#define CN 2 /* control index */
#define NM 3 /* numeric lock index */
#define AK 4 /* right alt key */
#define CP 5 /* capslock index */
#define ST 6 /* stop output index */
#define EX 7 /* extended code index */
#define ES 8 /* escape and extended code index */
#define NORMAL 0x0000 /* normal key */
#define STP 0x0001 /* scroll lock stop output*/
#define NUM 0x0002 /* numeric lock */
#define CAPS 0x0004 /* capslock */
#define SHIFT 0x0008 /* shift */
#define CTRL 0x0010 /* control*/
#define EXT 0x0020 /* extended scan code 0xe0 */
#define ESC 0x0040 /* escape key press */
#define E1 0x0080 /* extended scan code 0xe1 */
#define BRK 0x0100 /* make break flag for keyboard */
#define ALT 0x0200 /* right alt */
/* exports */
int i8042_kbd_init(void);
int i8042_tstc(void);
int i8042_getc(void);
#endif /* _I8042_H_ */

55
include/ide.h
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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _IDE_H
#define _IDE_H
#define IDE_BUS(dev) (dev >> 1)
#ifdef CONFIG_IDE_LED
/*
* LED Port
*/
#define LED_PORT ((uchar *)(PER8_BASE + 0x3000))
#define LED_IDE1 0x01
#define LED_IDE2 0x02
#define DEVICE_LED(d) ((d & 2) | ((d & 2) == 0)) /* depends on bit positions! */
#endif /* CONFIG_IDE_LED */
#ifdef CFG_64BIT_LBA
typedef uint64_t lbaint_t;
#else
typedef ulong lbaint_t;
#endif
/*
* Function Prototypes
*/
void ide_init (void);
ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer);
ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer);
#endif /* _IDE_H */

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include/jffs2/jffs2.h
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/*
* JFFS2 -- Journalling Flash File System, Version 2.
*
* Copyright (C) 2001 Red Hat, Inc.
*
* Created by David Woodhouse <dwmw2@cambridge.redhat.com>
*
* The original JFFS, from which the design for JFFS2 was derived,
* was designed and implemented by Axis Communications AB.
*
* The contents of this file are subject to the Red Hat eCos Public
* License Version 1.1 (the "Licence"); you may not use this file
* except in compliance with the Licence. You may obtain a copy of
* the Licence at http://www.redhat.com/
*
* Software distributed under the Licence is distributed on an "AS IS"
* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
* See the Licence for the specific language governing rights and
* limitations under the Licence.
*
* The Original Code is JFFS2 - Journalling Flash File System, version 2
*
* Alternatively, the contents of this file may be used under the
* terms of the GNU General Public License version 2 (the "GPL"), in
* which case the provisions of the GPL are applicable instead of the
* above. If you wish to allow the use of your version of this file
* only under the terms of the GPL and not to allow others to use your
* version of this file under the RHEPL, indicate your decision by
* deleting the provisions above and replace them with the notice and
* other provisions required by the GPL. If you do not delete the
* provisions above, a recipient may use your version of this file
* under either the RHEPL or the GPL.
*
* $Id: jffs2.h,v 1.2 2002/01/17 00:53:20 nyet Exp $
*
*/
#ifndef __LINUX_JFFS2_H__
#define __LINUX_JFFS2_H__
#include <asm/types.h>
#include <jffs2/load_kernel.h>
#define JFFS2_SUPER_MAGIC 0x72b6
/* Values we may expect to find in the 'magic' field */
#define JFFS2_OLD_MAGIC_BITMASK 0x1984
#define JFFS2_MAGIC_BITMASK 0x1985
#define KSAMTIB_CIGAM_2SFFJ 0x5981 /* For detecting wrong-endian fs */
#define JFFS2_EMPTY_BITMASK 0xffff
#define JFFS2_DIRTY_BITMASK 0x0000
/* We only allow a single char for length, and 0xFF is empty flash so
we don't want it confused with a real length. Hence max 254.
*/
#define JFFS2_MAX_NAME_LEN 254
/* How small can we sensibly write nodes? */
#define JFFS2_MIN_DATA_LEN 128
#define JFFS2_COMPR_NONE 0x00
#define JFFS2_COMPR_ZERO 0x01
#define JFFS2_COMPR_RTIME 0x02
#define JFFS2_COMPR_RUBINMIPS 0x03
#define JFFS2_COMPR_COPY 0x04
#define JFFS2_COMPR_DYNRUBIN 0x05
#define JFFS2_COMPR_ZLIB 0x06
#if defined(CONFIG_JFFS2_LZO_LZARI)
#define JFFS2_COMPR_LZO 0x07
#define JFFS2_COMPR_LZARI 0x08
#define JFFS2_NUM_COMPR 9
#else
#define JFFS2_NUM_COMPR 7
#endif
/* Compatibility flags. */
#define JFFS2_COMPAT_MASK 0xc000 /* What do to if an unknown nodetype is found */
#define JFFS2_NODE_ACCURATE 0x2000
/* INCOMPAT: Fail to mount the filesystem */
#define JFFS2_FEATURE_INCOMPAT 0xc000
/* ROCOMPAT: Mount read-only */
#define JFFS2_FEATURE_ROCOMPAT 0x8000
/* RWCOMPAT_COPY: Mount read/write, and copy the node when it's GC'd */
#define JFFS2_FEATURE_RWCOMPAT_COPY 0x4000
/* RWCOMPAT_DELETE: Mount read/write, and delete the node when it's GC'd */
#define JFFS2_FEATURE_RWCOMPAT_DELETE 0x0000
#define JFFS2_NODETYPE_DIRENT (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 1)
#define JFFS2_NODETYPE_INODE (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 2)
#define JFFS2_NODETYPE_CLEANMARKER (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3)
#define JFFS2_NODETYPE_PADDING (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 4)
/* Maybe later... */
/*#define JFFS2_NODETYPE_CHECKPOINT (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3) */
/*#define JFFS2_NODETYPE_OPTIONS (JFFS2_FEATURE_RWCOMPAT_COPY | JFFS2_NODE_ACCURATE | 4) */
/* Same as the non_ECC versions, but with extra space for real
* ECC instead of just the checksum. For use on NAND flash
*/
/*#define JFFS2_NODETYPE_DIRENT_ECC (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 5) */
/*#define JFFS2_NODETYPE_INODE_ECC (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 6) */
#define JFFS2_INO_FLAG_PREREAD 1 /* Do read_inode() for this one at
mount time, don't wait for it to
happen later */
#define JFFS2_INO_FLAG_USERCOMPR 2 /* User has requested a specific
compression type */
struct jffs2_unknown_node
{
/* All start like this */
__u16 magic;
__u16 nodetype;
__u32 totlen; /* So we can skip over nodes we don't grok */
__u32 hdr_crc;
} __attribute__((packed));
struct jffs2_raw_dirent
{
__u16 magic;
__u16 nodetype; /* == JFFS_NODETYPE_DIRENT */
__u32 totlen;
__u32 hdr_crc;
__u32 pino;
__u32 version;
__u32 ino; /* == zero for unlink */
__u32 mctime;
__u8 nsize;
__u8 type;
__u8 unused[2];
__u32 node_crc;
__u32 name_crc;
__u8 name[0];
} __attribute__((packed));
/* The JFFS2 raw inode structure: Used for storage on physical media. */
/* The uid, gid, atime, mtime and ctime members could be longer, but
are left like this for space efficiency. If and when people decide
they really need them extended, it's simple enough to add support for
a new type of raw node.
*/
struct jffs2_raw_inode
{
__u16 magic; /* A constant magic number. */
__u16 nodetype; /* == JFFS_NODETYPE_INODE */
__u32 totlen; /* Total length of this node (inc data, etc.) */
__u32 hdr_crc;
__u32 ino; /* Inode number. */
__u32 version; /* Version number. */
__u32 mode; /* The file's type or mode. */
__u16 uid; /* The file's owner. */
__u16 gid; /* The file's group. */
__u32 isize; /* Total resultant size of this inode (used for truncations) */
__u32 atime; /* Last access time. */
__u32 mtime; /* Last modification time. */
__u32 ctime; /* Change time. */
__u32 offset; /* Where to begin to write. */
__u32 csize; /* (Compressed) data size */
__u32 dsize; /* Size of the node's data. (after decompression) */
__u8 compr; /* Compression algorithm used */
__u8 usercompr; /* Compression algorithm requested by the user */
__u16 flags; /* See JFFS2_INO_FLAG_* */
__u32 data_crc; /* CRC for the (compressed) data. */
__u32 node_crc; /* CRC for the raw inode (excluding data) */
/* __u8 data[dsize]; */
} __attribute__((packed));
union jffs2_node_union {
struct jffs2_raw_inode i;
struct jffs2_raw_dirent d;
struct jffs2_unknown_node u;
} __attribute__((packed));
enum
{
DT_UNKNOWN = 0,
# define DT_UNKNOWN DT_UNKNOWN
DT_FIFO = 1,
# define DT_FIFO DT_FIFO
DT_CHR = 2,
# define DT_CHR DT_CHR
DT_DIR = 4,
# define DT_DIR DT_DIR
DT_BLK = 6,
# define DT_BLK DT_BLK
DT_REG = 8,
# define DT_REG DT_REG
DT_LNK = 10,
# define DT_LNK DT_LNK
DT_SOCK = 12,
# define DT_SOCK DT_SOCK
DT_WHT = 14
# define DT_WHT DT_WHT
};
u32 jffs2_1pass_ls(struct part_info *part,const char *fname);
u32 jffs2_1pass_load(char *dest, struct part_info *part,const char *fname);
u32 jffs2_1pass_info(struct part_info *part);
void rtime_decompress(unsigned char *data_in, unsigned char *cpage_out,
u32 srclen, u32 destlen);
void rubin_do_decompress(unsigned char *bits, unsigned char *in,
unsigned char *page_out, __u32 destlen);
void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out,
unsigned long sourcelen, unsigned long dstlen);
long zlib_decompress(unsigned char *data_in, unsigned char *cpage_out,
__u32 srclen, __u32 destlen);
#if defined(CONFIG_JFFS2_LZO_LZARI)
int lzo_decompress(unsigned char *data_in, unsigned char *cpage_out,
u32 srclen, u32 destlen);
int lzari_decompress(unsigned char *data_in, unsigned char *cpage_out,
u32 srclen, u32 destlen);
#endif
char *mkmodestr(unsigned long mode, char *str);
#endif /* __LINUX_JFFS2_H__ */

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include/jffs2/load_kernel.h
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#ifndef load_kernel_h
#define load_kernel_h
/*-------------------------------------------------------------------------
* Filename: load_kernel.h
* Version: $Id: load_kernel.h,v 1.3 2002/01/25 01:34:11 nyet Exp $
* Copyright: Copyright (C) 2001, Russ Dill
* Author: Russ Dill <Russ.Dill@asu.edu>
* Description: header for load kernel modules
*-----------------------------------------------------------------------*/
/*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <linux/list.h>
/* mtd device types */
#define MTD_DEV_TYPE_NOR 0x0001
#define MTD_DEV_TYPE_NAND 0x0002
#define MTD_DEV_TYPE(type) ((type == MTD_DEV_TYPE_NAND) ? "nand" : "nor")
struct mtd_device {
struct list_head link;
struct mtdids *id; /* parent mtd id entry */
u16 num_parts; /* number of partitions on this device */
struct list_head parts; /* partitions */
};
struct part_info {
struct list_head link;
char *name; /* partition name */
u8 auto_name; /* set to 1 for generated name */
u32 size; /* total size of the partition */
u32 offset; /* offset within device */
void *jffs2_priv; /* used internaly by jffs2 */
u32 mask_flags; /* kernel MTD mask flags */
struct mtd_device *dev; /* parent device */
};
struct mtdids {
struct list_head link;
u8 type; /* device type */
u8 num; /* device number */
u32 size; /* device size */
char *mtd_id; /* linux kernel device id */
};
#define ldr_strlen strlen
#define ldr_strncmp strncmp
#define ldr_memcpy memcpy
#define putstr(x) printf("%s", x)
#define mmalloc malloc
#define UDEBUG printf
#define putnstr(str, size) printf("%*.*s", size, size, str)
#define ldr_output_string(x) puts(x)
#define putLabeledWord(x, y) printf("%s %08x\n", x, (unsigned int)y)
#define led_blink(x, y, z, a)
#endif /* load_kernel_h */

1445
include/linux_logo.h
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124
include/nand.h
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/*
* (C) Copyright 2005
* 2N Telekomunikace, a.s. <www.2n.cz>
* Ladislav Michl <michl@2n.cz>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _NAND_H_
#define _NAND_H_
#include <linux/mtd/compat.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
typedef struct mtd_info nand_info_t;
extern int nand_curr_device;
extern nand_info_t nand_info[];
static inline int nand_read(nand_info_t *info, ulong ofs, ulong *len, u_char *buf)
{
return info->read(info, ofs, *len, (size_t *)len, buf);
}
static inline int nand_write(nand_info_t *info, ulong ofs, ulong *len, u_char *buf)
{
return info->write(info, ofs, *len, (size_t *)len, buf);
}
static inline int nand_block_isbad(nand_info_t *info, ulong ofs)
{
return info->block_isbad(info, ofs);
}
static inline int nand_erase(nand_info_t *info, ulong off, ulong size)
{
struct erase_info instr;
instr.mtd = info;
instr.addr = off;
instr.len = size;
instr.callback = 0;
return info->erase(info, &instr);
}
/*****************************************************************************
* declarations from nand_util.c
****************************************************************************/
struct nand_write_options {
u_char *buffer; /* memory block containing image to write */
ulong length; /* number of bytes to write */
ulong offset; /* start address in NAND */
int quiet; /* don't display progress messages */
int autoplace; /* if true use auto oob layout */
int forcejffs2; /* force jffs2 oob layout */
int forceyaffs; /* force yaffs oob layout */
int noecc; /* write without ecc */
int writeoob; /* image contains oob data */
int pad; /* pad to page size */
int blockalign; /* 1|2|4 set multiple of eraseblocks
* to align to */
};
typedef struct nand_write_options nand_write_options_t;
struct nand_read_options {
u_char *buffer; /* memory block in which read image is written*/
ulong length; /* number of bytes to read */
ulong offset; /* start address in NAND */
int quiet; /* don't display progress messages */
int readoob; /* put oob data in image */
};
typedef struct nand_read_options nand_read_options_t;
struct nand_erase_options {
ulong length; /* number of bytes to erase */
ulong offset; /* first address in NAND to erase */
int quiet; /* don't display progress messages */
int jffs2; /* if true: format for jffs2 usage
* (write appropriate cleanmarker blocks) */
int scrub; /* if true, really clean NAND by erasing
* bad blocks (UNSAFE) */
};
typedef struct nand_erase_options nand_erase_options_t;
int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts);
int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts);
int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts);
#define NAND_LOCK_STATUS_TIGHT 0x01
#define NAND_LOCK_STATUS_LOCK 0x02
#define NAND_LOCK_STATUS_UNLOCK 0x04
int nand_lock( nand_info_t *meminfo, int tight );
int nand_unlock( nand_info_t *meminfo, ulong start, ulong length );
int nand_get_lock_status(nand_info_t *meminfo, ulong offset);
#ifdef CFG_NAND_SELECT_DEVICE
void board_nand_select_device(struct nand_chip *nand, int chip);
#endif
#endif

159
include/ns16550.h
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/*
* NS16550 Serial Port
* originally from linux source (arch/ppc/boot/ns16550.h)
* modified slightly to
* have addresses as offsets from CFG_ISA_BASE
* added a few more definitions
* added prototypes for ns16550.c
* reduced no of com ports to 2
* modifications (c) Rob Taylor, Flying Pig Systems. 2000.
*
* added support for port on 64-bit bus
* by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
*/
#if (CFG_NS16550_REG_SIZE == 1)
struct NS16550 {
unsigned char rbr; /* 0 */
unsigned char ier; /* 1 */
unsigned char fcr; /* 2 */
unsigned char lcr; /* 3 */
unsigned char mcr; /* 4 */
unsigned char lsr; /* 5 */
unsigned char msr; /* 6 */
unsigned char scr; /* 7 */
#if defined(CONFIG_OMAP730)
unsigned char mdr1; /* 8 */
unsigned char reg9; /* 9 */
unsigned char regA; /* A */
unsigned char regB; /* B */
unsigned char regC; /* C */
unsigned char regD; /* D */
unsigned char regE; /* E */
unsigned char regF; /* F */
unsigned char reg10; /* 10 */
unsigned char ssr; /* 11*/
#endif
} __attribute__ ((packed));
#elif (CFG_NS16550_REG_SIZE == 2)
struct NS16550 {
unsigned short rbr; /* 0 */
unsigned short ier; /* 1 */
unsigned short fcr; /* 2 */
unsigned short lcr; /* 3 */
unsigned short mcr; /* 4 */
unsigned short lsr; /* 5 */
unsigned short msr; /* 6 */
unsigned short scr; /* 7 */
} __attribute__ ((packed));
#elif (CFG_NS16550_REG_SIZE == 4)
struct NS16550 {
unsigned long rbr; /* 0 r */
unsigned long ier; /* 1 rw */
unsigned long fcr; /* 2 w */
unsigned long lcr; /* 3 rw */
unsigned long mcr; /* 4 rw */
unsigned long lsr; /* 5 r */
unsigned long msr; /* 6 r */
unsigned long scr; /* 7 rw */
}; /* No need to pack an already aligned struct */
#elif (CFG_NS16550_REG_SIZE == -4)
struct NS16550 {
unsigned char rbr; /* 0 */
int pad1:24;
unsigned char ier; /* 1 */
int pad2:24;
unsigned char fcr; /* 2 */
int pad3:24;
unsigned char lcr; /* 3 */
int pad4:24;
unsigned char mcr; /* 4 */
int pad5:24;
unsigned char lsr; /* 5 */
int pad6:24;
unsigned char msr; /* 6 */
int pad7:24;
unsigned char scr; /* 7 */
int pad8:24;
#if defined(CONFIG_OMAP)
unsigned char mdr1; /* mode select reset TL16C750*/
#endif
#ifdef CONFIG_OMAP1510
int pad9:24;
unsigned long pad[10];
unsigned char osc_12m_sel;
int pad10:24;
#endif
} __attribute__ ((packed));
#elif (CFG_NS16550_REG_SIZE == -8)
struct NS16550 {
unsigned char rbr; /* 0 */
unsigned char pad0[7];
unsigned char ier; /* 1 */
unsigned char pad1[7];
unsigned char fcr; /* 2 */
unsigned char pad2[7];
unsigned char lcr; /* 3 */
unsigned char pad3[7];
unsigned char mcr; /* 4 */
unsigned char pad4[7];
unsigned char lsr; /* 5 */
unsigned char pad5[7];
unsigned char msr; /* 6 */
unsigned char pad6[7];
unsigned char scr; /* 7 */
unsigned char pad7[7];
} __attribute__ ((packed));
#else
#error "Please define NS16550 registers size."
#endif
#define thr rbr
#define iir fcr
#define dll rbr
#define dlm ier
typedef volatile struct NS16550 *NS16550_t;
#define FCR_FIFO_EN 0x01 /* Fifo enable */
#define FCR_RXSR 0x02 /* Receiver soft reset */
#define FCR_TXSR 0x04 /* Transmitter soft reset */
#define MCR_DTR 0x01
#define MCR_RTS 0x02
#define MCR_DMA_EN 0x04
#define MCR_TX_DFR 0x08
#define LCR_WLS_MSK 0x03 /* character length select mask */
#define LCR_WLS_5 0x00 /* 5 bit character length */
#define LCR_WLS_6 0x01 /* 6 bit character length */
#define LCR_WLS_7 0x02 /* 7 bit character length */
#define LCR_WLS_8 0x03 /* 8 bit character length */
#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
#define LCR_PEN 0x08 /* Parity eneble */
#define LCR_EPS 0x10 /* Even Parity Select */
#define LCR_STKP 0x20 /* Stick Parity */
#define LCR_SBRK 0x40 /* Set Break */
#define LCR_BKSE 0x80 /* Bank select enable */
#define LSR_DR 0x01 /* Data ready */
#define LSR_OE 0x02 /* Overrun */
#define LSR_PE 0x04 /* Parity error */
#define LSR_FE 0x08 /* Framing error */
#define LSR_BI 0x10 /* Break */
#define LSR_THRE 0x20 /* Xmit holding register empty */
#define LSR_TEMT 0x40 /* Xmitter empty */
#define LSR_ERR 0x80 /* Error */
#ifdef CONFIG_OMAP1510
#define OSC_12M_SEL 0x01 /* selects 6.5 * current clk div */
#endif
/* useful defaults for LCR */
#define LCR_8N1 0x03
void NS16550_init (NS16550_t com_port, int baud_divisor);
void NS16550_putc (NS16550_t com_port, char c);
char NS16550_getc (NS16550_t com_port);
int NS16550_tstc (NS16550_t com_port);
void NS16550_reinit (NS16550_t com_port, int baud_divisor);

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include/pc_keyb.h
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/*
* include/linux/pc_keyb.h
*
* PC Keyboard And Keyboard Controller
*
* (c) 1997 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
*/
/*
* Configuration Switches
*/
#undef KBD_REPORT_ERR /* Report keyboard errors */
#define KBD_REPORT_UNKN /* Report unknown scan codes */
#define KBD_REPORT_TIMEOUTS /* Report keyboard timeouts */
#undef KBD_IS_FOCUS_9000 /* We have the brain-damaged FOCUS-9000 keyboard */
#undef INITIALIZE_MOUSE /* Define if your PS/2 mouse needs initialization. */
#define KBD_INIT_TIMEOUT 1000 /* Timeout in ms for initializing the keyboard */
#define KBC_TIMEOUT 250 /* Timeout in ms for sending to keyboard controller */
#define KBD_TIMEOUT 1000 /* Timeout in ms for keyboard command acknowledge */
/*
* Internal variables of the driver
*/
extern unsigned char pckbd_read_mask;
extern unsigned char aux_device_present;
/*
* Keyboard Controller Registers on normal PCs.
*/
#define KBD_STATUS_REG 0x64 /* Status register (R) */
#define KBD_CNTL_REG 0x64 /* Controller command register (W) */
#define KBD_DATA_REG 0x60 /* Keyboard data register (R/W) */
/*
* Keyboard Controller Commands
*/
#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
#define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
initiated by the auxiliary device */
#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
/*
* Keyboard Commands
*/
#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
#define KBD_CMD_DISABLE 0xF5 /* Disable scanning */
#define KBD_CMD_RESET 0xFF /* Reset */
/*
* Keyboard Replies
*/
#define KBD_REPLY_POR 0xAA /* Power on reset */
#define KBD_REPLY_ACK 0xFA /* Command ACK */
#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
/*
* Status Register Bits
*/
#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
#define KBD_STAT_SELFTEST 0x04 /* Self test successful */
#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
#define KBD_STAT_PERR 0x80 /* Parity error */
#define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF)
/*
* Controller Mode Register Bits
*/
#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
#define KBD_MODE_SYS 0x04 /* The system flag (?) */
#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
#define KBD_MODE_RFU 0x80
/*
* Mouse Commands
*/
#define AUX_SET_RES 0xE8 /* Set resolution */
#define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */
#define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */
#define AUX_GET_SCALE 0xE9 /* Get scaling factor */
#define AUX_SET_STREAM 0xEA /* Set stream mode */
#define AUX_SET_SAMPLE 0xF3 /* Set sample rate */
#define AUX_ENABLE_DEV 0xF4 /* Enable aux device */
#define AUX_DISABLE_DEV 0xF5 /* Disable aux device */
#define AUX_RESET 0xFF /* Reset aux device */
#define AUX_ACK 0xFA /* Command byte ACK. */
#define AUX_BUF_SIZE 2048 /* This might be better divisible by
three to make overruns stay in sync
but then the read function would need
a lock etc - ick */

528
include/pci.h
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/*
* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Andreas Heppel <aheppel@sysgo.de>
*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* aloong with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _PCI_H
#define _PCI_H
/*
* Under PCI, each device has 256 bytes of configuration address space,
* of which the first 64 bytes are standardized as follows:
*/
#define PCI_VENDOR_ID 0x00 /* 16 bits */
#define PCI_DEVICE_ID 0x02 /* 16 bits */
#define PCI_COMMAND 0x04 /* 16 bits */
#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
#define PCI_STATUS 0x06 /* 16 bits */
#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
#define PCI_STATUS_DEVSEL_FAST 0x000
#define PCI_STATUS_DEVSEL_MEDIUM 0x200
#define PCI_STATUS_DEVSEL_SLOW 0x400
#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
revision */
#define PCI_REVISION_ID 0x08 /* Revision ID */
#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
#define PCI_CLASS_DEVICE 0x0a /* Device class */
#define PCI_CLASS_CODE 0x0b /* Device class code */
#define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
#define PCI_HEADER_TYPE 0x0e /* 8 bits */
#define PCI_HEADER_TYPE_NORMAL 0
#define PCI_HEADER_TYPE_BRIDGE 1
#define PCI_HEADER_TYPE_CARDBUS 2
#define PCI_BIST 0x0f /* 8 bits */
#define PCI_BIST_CODE_MASK 0x0f /* Return result */
#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
/*
* Base addresses specify locations in memory or I/O space.
* Decoded size can be determined by writing a value of
* 0xffffffff to the register, and reading it back. Only
* 1 bits are decoded.
*/
#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
#define PCI_BASE_ADDRESS_SPACE_IO 0x01
#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
/* bit 1 is reserved if address_space = 1 */
/* Header type 0 (normal devices) */
#define PCI_CARDBUS_CIS 0x28
#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
#define PCI_SUBSYSTEM_ID 0x2e
#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
#define PCI_ROM_ADDRESS_ENABLE 0x01
#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
/* 0x35-0x3b are reserved */
#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
#define PCI_MIN_GNT 0x3e /* 8 bits */
#define PCI_MAX_LAT 0x3f /* 8 bits */
/* Header type 1 (PCI-to-PCI bridges) */
#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
#define PCI_IO_LIMIT 0x1d
#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
#define PCI_IO_RANGE_TYPE_16 0x00
#define PCI_IO_RANGE_TYPE_32 0x01
#define PCI_IO_RANGE_MASK ~0x0f
#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
#define PCI_MEMORY_LIMIT 0x22
#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
#define PCI_MEMORY_RANGE_MASK ~0x0f
#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
#define PCI_PREF_MEMORY_LIMIT 0x26
#define PCI_PREF_RANGE_TYPE_MASK 0x0f
#define PCI_PREF_RANGE_TYPE_32 0x00
#define PCI_PREF_RANGE_TYPE_64 0x01
#define PCI_PREF_RANGE_MASK ~0x0f
#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
#define PCI_PREF_LIMIT_UPPER32 0x2c
#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
#define PCI_IO_LIMIT_UPPER16 0x32
/* 0x34 same as for htype 0 */
/* 0x35-0x3b is reserved */
#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_BRIDGE_CONTROL 0x3e
#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
/* From 440ep */
#define PCI_ERREN 0x48 /* Error Enable */
#define PCI_ERRSTS 0x49 /* Error Status */
#define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */
#define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */
#define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */
#define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */
#define PCI_CAPID 0x58 /* Capability Identifier */
#define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */
#define PCI_PMC 0x5A /* Power Management Capabilities */
#define PCI_PMCSR 0x5C /* Power Management Control Status */
#define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */
#define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */
#define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */
/* Header type 2 (CardBus bridges) */
#define PCI_CB_CAPABILITY_LIST 0x14
/* 0x15 reserved */
#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
#define PCI_CB_MEMORY_BASE_0 0x1c
#define PCI_CB_MEMORY_LIMIT_0 0x20
#define PCI_CB_MEMORY_BASE_1 0x24
#define PCI_CB_MEMORY_LIMIT_1 0x28
#define PCI_CB_IO_BASE_0 0x2c
#define PCI_CB_IO_BASE_0_HI 0x2e
#define PCI_CB_IO_LIMIT_0 0x30
#define PCI_CB_IO_LIMIT_0_HI 0x32
#define PCI_CB_IO_BASE_1 0x34
#define PCI_CB_IO_BASE_1_HI 0x36
#define PCI_CB_IO_LIMIT_1 0x38
#define PCI_CB_IO_LIMIT_1_HI 0x3a
#define PCI_CB_IO_RANGE_MASK ~0x03
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_CB_BRIDGE_CONTROL 0x3e
#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
#define PCI_CB_BRIDGE_CTL_SERR 0x02
#define PCI_CB_BRIDGE_CTL_ISA 0x04
#define PCI_CB_BRIDGE_CTL_VGA 0x08
#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
#define PCI_CB_SUBSYSTEM_ID 0x42
#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
/* 0x48-0x7f reserved */
/* Capability lists */
#define PCI_CAP_LIST_ID 0 /* Capability ID */
#define PCI_CAP_ID_PM 0x01 /* Power Management */
#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
#define PCI_CAP_SIZEOF 4
/* Power Management Registers */
#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
#define PCI_PM_CTRL 4 /* PM control and status register */
#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
#define PCI_PM_DATA_REGISTER 7 /* (??) */
#define PCI_PM_SIZEOF 8
/* AGP registers */
#define PCI_AGP_VERSION 2 /* BCD version number */
#define PCI_AGP_RFU 3 /* Rest of capability flags */
#define PCI_AGP_STATUS 4 /* Status register */
#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
#define PCI_AGP_COMMAND 8 /* Control register */
#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
#define PCI_AGP_SIZEOF 12
/* PCI-X registers */
#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */
#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */
#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
/* Slot Identification */
#define PCI_SID_ESR 2 /* Expansion Slot Register */
#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
/* Message Signalled Interrupts registers */
#define PCI_MSI_FLAGS 2 /* Various flags */
#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
#define PCI_MSI_RFU 3 /* Rest of capability flags */
#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
#define PCI_MAX_PCI_DEVICES 32
#define PCI_MAX_PCI_FUNCTIONS 8
/* Include the ID list */
#include <pci_ids.h>
struct pci_region {
unsigned long bus_start; /* Start on the bus */
unsigned long phys_start; /* Start in physical address space */
unsigned long size; /* Size */
unsigned long flags; /* Resource flags */
unsigned long bus_lower;
};
#define PCI_REGION_MEM 0x00000000 /* PCI memory space */
#define PCI_REGION_IO 0x00000001 /* PCI IO space */
#define PCI_REGION_TYPE 0x00000001
#define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
#define PCI_REGION_MEMORY 0x00000100 /* System memory */
#define PCI_REGION_RO 0x00000200 /* Read-only memory */
extern __inline__ void pci_set_region(struct pci_region *reg,
unsigned long bus_start,
unsigned long phys_start,
unsigned long size,
unsigned long flags) {
reg->bus_start = bus_start;
reg->phys_start = phys_start;
reg->size = size;
reg->flags = flags;
}
typedef int pci_dev_t;
#define PCI_BUS(d) (((d) >> 16) & 0xff)
#define PCI_DEV(d) (((d) >> 11) & 0x1f)
#define PCI_FUNC(d) (((d) >> 8) & 0x7)
#define PCI_BDF(b,d,f) ((b) << 16 | (d) << 11 | (f) << 8)
#define PCI_ANY_ID (~0)
struct pci_device_id {
unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
};
struct pci_controller;
struct pci_config_table {
unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
unsigned int class; /* Class ID, or PCI_ANY_ID */
unsigned int bus; /* Bus number, or PCI_ANY_ID */
unsigned int dev; /* Device number, or PCI_ANY_ID */
unsigned int func; /* Function number, or PCI_ANY_ID */
void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
struct pci_config_table *);
unsigned long priv[3];
};
extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
struct pci_config_table *);
extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
struct pci_config_table *);
#define MAX_PCI_REGIONS 7
/*
* Structure of a PCI controller (host bridge)
*/
struct pci_controller {
struct pci_controller *next;
int first_busno;
int last_busno;
volatile unsigned int *cfg_addr;
volatile unsigned char *cfg_data;
struct pci_region regions[MAX_PCI_REGIONS];
int region_count;
struct pci_config_table *config_table;
void (*fixup_irq)(struct pci_controller *, pci_dev_t);
/* Low-level architecture-dependent routines */
int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
/* Used by auto config */
struct pci_region *pci_mem, *pci_io, *pci_prefetch;
/* Used by ppc405 autoconfig*/
struct pci_region *pci_fb;
int current_busno;
};
extern __inline__ void pci_set_ops(struct pci_controller *hose,
int (*read_byte)(struct pci_controller*,
pci_dev_t, int where, u8 *),
int (*read_word)(struct pci_controller*,
pci_dev_t, int where, u16 *),
int (*read_dword)(struct pci_controller*,
pci_dev_t, int where, u32 *),
int (*write_byte)(struct pci_controller*,
pci_dev_t, int where, u8),
int (*write_word)(struct pci_controller*,
pci_dev_t, int where, u16),
int (*write_dword)(struct pci_controller*,
pci_dev_t, int where, u32)) {
hose->read_byte = read_byte;
hose->read_word = read_word;
hose->read_dword = read_dword;
hose->write_byte = write_byte;
hose->write_word = write_word;
hose->write_dword = write_dword;
}
extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
extern unsigned long pci_hose_bus_to_phys(struct pci_controller* hose,
unsigned long addr, unsigned long flags);
extern unsigned long pci_hose_phys_to_bus(struct pci_controller* hose,
unsigned long addr, unsigned long flags);
#define pci_phys_to_bus(dev, addr, flags) \
pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
#define pci_bus_to_phys(dev, addr, flags) \
pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
#define pci_phys_to_mem(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
#define pci_mem_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
extern int pci_hose_read_config_byte(struct pci_controller *hose,
pci_dev_t dev, int where, u8 *val);
extern int pci_hose_read_config_word(struct pci_controller *hose,
pci_dev_t dev, int where, u16 *val);
extern int pci_hose_read_config_dword(struct pci_controller *hose,
pci_dev_t dev, int where, u32 *val);
extern int pci_hose_write_config_byte(struct pci_controller *hose,
pci_dev_t dev, int where, u8 val);
extern int pci_hose_write_config_word(struct pci_controller *hose,
pci_dev_t dev, int where, u16 val);
extern int pci_hose_write_config_dword(struct pci_controller *hose,
pci_dev_t dev, int where, u32 val);
extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
pci_dev_t dev, int where, u8 *val);
extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
pci_dev_t dev, int where, u16 *val);
extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
pci_dev_t dev, int where, u8 val);
extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
pci_dev_t dev, int where, u16 val);
extern void pci_register_hose(struct pci_controller* hose);
extern struct pci_controller* pci_bus_to_hose(int bus);
extern int pci_hose_scan(struct pci_controller *hose);
extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
extern void pciauto_region_init(struct pci_region* res);
extern void pciauto_region_align(struct pci_region *res, unsigned long size);
extern int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar);
extern void pciauto_setup_device(struct pci_controller *hose,
pci_dev_t dev, int bars_num,
struct pci_region *mem,
struct pci_region *prefetch,
struct pci_region *io);
int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code,
int wanted_prog_if, int index);
extern int pci_hose_config_device(struct pci_controller *hose,
pci_dev_t dev,
unsigned long io,
unsigned long mem,
unsigned long command);
#ifdef CONFIG_MPC824X
extern void pci_mpc824x_init (struct pci_controller *hose);
#endif
#ifdef CONFIG_MPC85xx
extern void pci_mpc85xx_init (struct pci_controller *hose);
#endif
void pci_init (void);
void pci_init_board(void);
void pciinfo (int, int);
#if defined(CONFIG_PCI) && defined(CONFIG_440)
# if defined(CFG_PCI_PRE_INIT)
int pci_pre_init (struct pci_controller * );
# endif
# if defined(CFG_PCI_TARGET_INIT)
void pci_target_init (struct pci_controller *);
# endif
# if defined(CFG_PCI_MASTER_INIT)
void pci_master_init (struct pci_controller *);
# endif
int is_pci_host (struct pci_controller *);
#if defined(CONFIG_440SPE)
void pcie_setup_hoses(void);
#endif
#endif
#endif /* _PCI_H */

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include/pci_ids.h
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include/post.h
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/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _POST_H
#define _POST_H
#ifndef __ASSEMBLY__
#include <common.h>
#endif
#ifdef CONFIG_POST
#define POST_POWERON 0x01 /* test runs on power-on booting */
#define POST_NORMAL 0x02 /* test runs on normal booting */
#define POST_SLOWTEST 0x04 /* test is slow, enabled by key press */
#define POST_POWERTEST 0x08 /* test runs after watchdog reset */
#define POST_COLDBOOT 0x80 /* first boot after power-on */
#define POST_ROM 0x0100 /* test runs in ROM */
#define POST_RAM 0x0200 /* test runs in RAM */
#define POST_MANUAL 0x0400 /* test runs on diag command */
#define POST_REBOOT 0x0800 /* test may cause rebooting */
#define POST_PREREL 0x1000 /* test runs before relocation */
#define POST_MEM (POST_RAM | POST_ROM)
#define POST_ALWAYS (POST_NORMAL | \
POST_SLOWTEST | \
POST_MANUAL | \
POST_POWERON )
#ifndef __ASSEMBLY__
struct post_test {
char *name;
char *cmd;
char *desc;
int flags;
int (*test) (int flags);
int (*init_f) (void);
void (*reloc) (void);
unsigned long testid;
};
int post_init_f (void);
void post_bootmode_init (void);
int post_bootmode_get (unsigned int * last_test);
void post_bootmode_clear (void);
void post_output_backlog ( void );
int post_run (char *name, int flags);
int post_info (char *name);
int post_log (char *format, ...);
void post_reloc (void);
unsigned long post_time_ms (unsigned long base);
extern struct post_test post_list[];
extern unsigned int post_list_size;
extern int post_hotkeys_pressed(void);
#endif /* __ASSEMBLY__ */
#define CFG_POST_RTC 0x00000001
#define CFG_POST_WATCHDOG 0x00000002
#define CFG_POST_MEMORY 0x00000004
#define CFG_POST_CPU 0x00000008
#define CFG_POST_I2C 0x00000010
#define CFG_POST_CACHE 0x00000020
#define CFG_POST_UART 0x00000040
#define CFG_POST_ETHER 0x00000080
#define CFG_POST_SPI 0x00000100
#define CFG_POST_USB 0x00000200
#define CFG_POST_SPR 0x00000400
#define CFG_POST_SYSMON 0x00000800
#define CFG_POST_DSP 0x00001000
#define CFG_POST_CODEC 0x00002000
#endif /* CONFIG_POST */
#endif /* _POST_H */

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include/scsi.h
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/*
* (C) Copyright 2001
* Denis Peter, MPL AG Switzerland
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef _SCSI_H
#define _SCSI_H
typedef struct SCSI_cmd_block{
unsigned char cmd[16]; /* command */
unsigned char sense_buf[64]; /* for request sense */
unsigned char status; /* SCSI Status */
unsigned char target; /* Target ID */
unsigned char lun; /* Target LUN */
unsigned char cmdlen; /* command len */
unsigned long datalen; /* Total data length */
unsigned char * pdata; /* pointer to data */
unsigned char msgout[12]; /* Messge out buffer (NOT USED) */
unsigned char msgin[12]; /* Message in buffer */
unsigned char sensecmdlen; /* Sense command len */
unsigned long sensedatalen; /* Sense data len */
unsigned char sensecmd[6]; /* Sense command */
unsigned long contr_stat; /* Controller Status */
unsigned long trans_bytes; /* tranfered bytes */
unsigned int priv;
}ccb;
/*-----------------------------------------------------------
**
** SCSI constants.
**
**-----------------------------------------------------------
*/
/*
** Messages
*/
#define M_COMPLETE (0x00)
#define M_EXTENDED (0x01)
#define M_SAVE_DP (0x02)
#define M_RESTORE_DP (0x03)
#define M_DISCONNECT (0x04)
#define M_ID_ERROR (0x05)
#define M_ABORT (0x06)
#define M_REJECT (0x07)
#define M_NOOP (0x08)
#define M_PARITY (0x09)
#define M_LCOMPLETE (0x0a)
#define M_FCOMPLETE (0x0b)
#define M_RESET (0x0c)
#define M_ABORT_TAG (0x0d)
#define M_CLEAR_QUEUE (0x0e)
#define M_INIT_REC (0x0f)
#define M_REL_REC (0x10)
#define M_TERMINATE (0x11)
#define M_SIMPLE_TAG (0x20)
#define M_HEAD_TAG (0x21)
#define M_ORDERED_TAG (0x22)
#define M_IGN_RESIDUE (0x23)
#define M_IDENTIFY (0x80)
#define M_X_MODIFY_DP (0x00)
#define M_X_SYNC_REQ (0x01)
#define M_X_WIDE_REQ (0x03)
#define M_X_PPR_REQ (0x04)
/*
** Status
*/
#define S_GOOD (0x00)
#define S_CHECK_COND (0x02)
#define S_COND_MET (0x04)
#define S_BUSY (0x08)
#define S_INT (0x10)
#define S_INT_COND_MET (0x14)
#define S_CONFLICT (0x18)
#define S_TERMINATED (0x20)
#define S_QUEUE_FULL (0x28)
#define S_ILLEGAL (0xff)
#define S_SENSE (0x80)
/*
* Sense_keys
*/
#define SENSE_NO_SENSE 0x0
#define SENSE_RECOVERED_ERROR 0x1
#define SENSE_NOT_READY 0x2
#define SENSE_MEDIUM_ERROR 0x3
#define SENSE_HARDWARE_ERROR 0x4
#define SENSE_ILLEGAL_REQUEST 0x5
#define SENSE_UNIT_ATTENTION 0x6
#define SENSE_DATA_PROTECT 0x7
#define SENSE_BLANK_CHECK 0x8
#define SENSE_VENDOR_SPECIFIC 0x9
#define SENSE_COPY_ABORTED 0xA
#define SENSE_ABORTED_COMMAND 0xB
#define SENSE_VOLUME_OVERFLOW 0xD
#define SENSE_MISCOMPARE 0xE
#define SCSI_CHANGE_DEF 0x40 /* Change Definition (Optional) */
#define SCSI_COMPARE 0x39 /* Compare (O) */
#define SCSI_COPY 0x18 /* Copy (O) */
#define SCSI_COP_VERIFY 0x3A /* Copy and Verify (O) */
#define SCSI_INQUIRY 0x12 /* Inquiry (MANDATORY) */
#define SCSI_LOG_SELECT 0x4C /* Log Select (O) */
#define SCSI_LOG_SENSE 0x4D /* Log Sense (O) */
#define SCSI_MODE_SEL6 0x15 /* Mode Select 6-byte (Device Specific) */
#define SCSI_MODE_SEL10 0x55 /* Mode Select 10-byte (Device Specific) */
#define SCSI_MODE_SEN6 0x1A /* Mode Sense 6-byte (Device Specific) */
#define SCSI_MODE_SEN10 0x5A /* Mode Sense 10-byte (Device Specific) */
#define SCSI_READ_BUFF 0x3C /* Read Buffer (O) */
#define SCSI_REQ_SENSE 0x03 /* Request Sense (MANDATORY) */
#define SCSI_SEND_DIAG 0x1D /* Send Diagnostic (O) */
#define SCSI_TST_U_RDY 0x00 /* Test Unit Ready (MANDATORY) */
#define SCSI_WRITE_BUFF 0x3B /* Write Buffer (O) */
/***************************************************************************
* %%% Commands Unique to Direct Access Devices %%%
***************************************************************************/
#define SCSI_COMPARE 0x39 /* Compare (O) */
#define SCSI_FORMAT 0x04 /* Format Unit (MANDATORY) */
#define SCSI_LCK_UN_CAC 0x36 /* Lock Unlock Cache (O) */
#define SCSI_PREFETCH 0x34 /* Prefetch (O) */
#define SCSI_MED_REMOVL 0x1E /* Prevent/Allow medium Removal (O) */
#define SCSI_READ6 0x08 /* Read 6-byte (MANDATORY) */
#define SCSI_READ10 0x28 /* Read 10-byte (MANDATORY) */
#define SCSI_RD_CAPAC 0x25 /* Read Capacity (MANDATORY) */
#define SCSI_RD_DEFECT 0x37 /* Read Defect Data (O) */
#define SCSI_READ_LONG 0x3E /* Read Long (O) */
#define SCSI_REASS_BLK 0x07 /* Reassign Blocks (O) */
#define SCSI_RCV_DIAG 0x1C /* Receive Diagnostic Results (O) */
#define SCSI_RELEASE 0x17 /* Release Unit (MANDATORY) */
#define SCSI_REZERO 0x01 /* Rezero Unit (O) */
#define SCSI_SRCH_DAT_E 0x31 /* Search Data Equal (O) */
#define SCSI_SRCH_DAT_H 0x30 /* Search Data High (O) */
#define SCSI_SRCH_DAT_L 0x32 /* Search Data Low (O) */
#define SCSI_SEEK6 0x0B /* Seek 6-Byte (O) */
#define SCSI_SEEK10 0x2B /* Seek 10-Byte (O) */
#define SCSI_SEND_DIAG 0x1D /* Send Diagnostics (MANDATORY) */
#define SCSI_SET_LIMIT 0x33 /* Set Limits (O) */
#define SCSI_START_STP 0x1B /* Start/Stop Unit (O) */
#define SCSI_SYNC_CACHE 0x35 /* Synchronize Cache (O) */
#define SCSI_VERIFY 0x2F /* Verify (O) */
#define SCSI_WRITE6 0x0A /* Write 6-Byte (MANDATORY) */
#define SCSI_WRITE10 0x2A /* Write 10-Byte (MANDATORY) */
#define SCSI_WRT_VERIFY 0x2E /* Write and Verify (O) */
#define SCSI_WRITE_LONG 0x3F /* Write Long (O) */
#define SCSI_WRITE_SAME 0x41 /* Write Same (O) */
/****************************************************************************
* decleration of functions which have to reside in the LowLevel Part Driver
*/
void scsi_print_error(ccb *pccb);
int scsi_exec(ccb *pccb);
void scsi_bus_reset(void);
void scsi_low_level_init(int busdevfunc);
/***************************************************************************
* functions residing inside cmd_scsi.c
*/
void scsi_init(void);
#define SCSI_IDENTIFY 0xC0 /* not used */
/* Hardware errors */
#define SCSI_SEL_TIME_OUT 0x00000101 /* Selection time out */
#define SCSI_HNS_TIME_OUT 0x00000102 /* Handshake */
#define SCSI_MA_TIME_OUT 0x00000103 /* Phase error */
#define SCSI_UNEXP_DIS 0x00000104 /* unexpected disconnect */
#define SCSI_INT_STATE 0x00010000 /* unknown Interrupt number is stored in 16 LSB */
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#endif /* _SCSI_H */

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include/status_led.h
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/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* The purpose of this code is to signal the operational status of a
* target which usually boots over the network; while running in
* PCBoot, a status LED is blinking. As soon as a valid BOOTP reply
* message has been received, the LED is turned off. The Linux
* kernel, once it is running, will start blinking the LED again,
* with another frequency.
*/
#ifndef _STATUS_LED_H_
#define _STATUS_LED_H_
#ifdef CONFIG_STATUS_LED
#define STATUS_LED_OFF 0
#define STATUS_LED_BLINKING 1
#define STATUS_LED_ON 2
void status_led_tick (unsigned long timestamp);
void status_led_set (int led, int state);
/***** TQM8xxL ********************************************************/
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_HMI10)
# define STATUS_LED_PAR im_cpm.cp_pbpar
# define STATUS_LED_DIR im_cpm.cp_pbdir
# define STATUS_LED_ODR im_cpm.cp_pbodr
# define STATUS_LED_DAT im_cpm.cp_pbdat
# define STATUS_LED_BIT 0x00000001
# define STATUS_LED_PERIOD (CFG_HZ / 2)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** MVS v1 **********************************************************/
#elif (defined(CONFIG_MVS) && CONFIG_MVS < 2)
# define STATUS_LED_PAR im_ioport.iop_pdpar
# define STATUS_LED_DIR im_ioport.iop_pddir
# undef STATUS_LED_ODR
# define STATUS_LED_DAT im_ioport.iop_pddat
# define STATUS_LED_BIT 0x00000001
# define STATUS_LED_PERIOD (CFG_HZ / 2)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** ETX_094 ********************************************************/
#elif defined(CONFIG_ETX094)
# define STATUS_LED_PAR im_ioport.iop_pdpar
# define STATUS_LED_DIR im_ioport.iop_pddir
# undef STATUS_LED_ODR
# define STATUS_LED_DAT im_ioport.iop_pddat
# define STATUS_LED_BIT 0x00000001
# define STATUS_LED_PERIOD (CFG_HZ / 2)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** GEN860T *********************************************************/
#elif defined(CONFIG_GEN860T)
# define STATUS_LED_PAR im_ioport.iop_papar
# define STATUS_LED_DIR im_ioport.iop_padir
# define STATUS_LED_ODR im_ioport.iop_paodr
# define STATUS_LED_DAT im_ioport.iop_padat
# define STATUS_LED_BIT 0x0800 /* Red LED 0 is on PA.4 */
# define STATUS_LED_PERIOD (CFG_HZ / 4)
# define STATUS_LED_STATE STATUS_LED_OFF
# define STATUS_LED_BIT1 0x0400 /* Grn LED 1 is on PA.5 */
# define STATUS_LED_PERIOD1 (CFG_HZ / 8)
# define STATUS_LED_STATE1 STATUS_LED_BLINKING
# define STATUS_LED_BIT2 0x0080 /* Red LED 2 is on PA.8 */
# define STATUS_LED_PERIOD2 (CFG_HZ / 4)
# define STATUS_LED_STATE2 STATUS_LED_OFF
# define STATUS_LED_BIT3 0x0040 /* Grn LED 3 is on PA.9 */
# define STATUS_LED_PERIOD3 (CFG_HZ / 4)
# define STATUS_LED_STATE3 STATUS_LED_OFF
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_LED_BOOT 1 /* Boot status on LED 1 */
/***** IVMS8 **********************************************************/
#elif defined(CONFIG_IVMS8)
# define STATUS_LED_PAR im_cpm.cp_pbpar
# define STATUS_LED_DIR im_cpm.cp_pbdir
# define STATUS_LED_ODR im_cpm.cp_pbodr
# define STATUS_LED_DAT im_cpm.cp_pbdat
# define STATUS_LED_BIT 0x00000010 /* LED 0 is on PB.27 */
# define STATUS_LED_PERIOD (1 * CFG_HZ)
# define STATUS_LED_STATE STATUS_LED_OFF
# define STATUS_LED_BIT1 0x00000020 /* LED 1 is on PB.26 */
# define STATUS_LED_PERIOD1 (1 * CFG_HZ)
# define STATUS_LED_STATE1 STATUS_LED_OFF
/* IDE LED usable for other purposes, too */
# define STATUS_LED_BIT2 0x00000008 /* LED 2 is on PB.28 */
# define STATUS_LED_PERIOD2 (1 * CFG_HZ)
# define STATUS_LED_STATE2 STATUS_LED_OFF
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_ILOCK_SWITCH 0x00800000 /* ILOCK switch in IRQ4 */
# define STATUS_ILOCK_PERIOD (CFG_HZ / 10) /* about every 100 ms */
# define STATUS_LED_YELLOW 0
# define STATUS_LED_GREEN 1
# define STATUS_LED_BOOT 2 /* IDE LED used for boot status */
/***** IVML24 *********************************************************/
#elif defined(CONFIG_IVML24)
# define STATUS_LED_PAR im_cpm.cp_pbpar
# define STATUS_LED_DIR im_cpm.cp_pbdir
# define STATUS_LED_ODR im_cpm.cp_pbodr
# define STATUS_LED_DAT im_cpm.cp_pbdat
# define STATUS_LED_BIT 0x00000010 /* LED 0 is on PB.27 */
# define STATUS_LED_PERIOD (1 * CFG_HZ)
# define STATUS_LED_STATE STATUS_LED_OFF
# define STATUS_LED_BIT1 0x00000020 /* LED 1 is on PB.26 */
# define STATUS_LED_PERIOD1 (1 * CFG_HZ)
# define STATUS_LED_STATE1 STATUS_LED_OFF
/* IDE LED usable for other purposes, too */
# define STATUS_LED_BIT2 0x00000008 /* LED 2 is on PB.28 */
# define STATUS_LED_PERIOD2 (1 * CFG_HZ)
# define STATUS_LED_STATE2 STATUS_LED_OFF
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_ILOCK_SWITCH 0x00004000 /* ILOCK is on PB.17 */
# define STATUS_ILOCK_PERIOD (CFG_HZ / 10) /* about every 100 ms */
# define STATUS_LED_YELLOW 0
# define STATUS_LED_GREEN 1
# define STATUS_LED_BOOT 2 /* IDE LED used for boot status */
/***** LANTEC *********************************************************/
#elif defined(CONFIG_LANTEC)
# define STATUS_LED_PAR im_ioport.iop_pdpar
# define STATUS_LED_DIR im_ioport.iop_pddir
# undef STATUS_LED_ODR
# define STATUS_LED_DAT im_ioport.iop_pddat
# if CONFIG_LATEC < 2
# define STATUS_LED_BIT 0x1000
# else
# define STATUS_LED_BIT 0x0800
# endif
# define STATUS_LED_PERIOD (CFG_HZ / 2)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** PCU E and CCM ************************************************/
#elif (defined(CONFIG_PCU_E) || defined(CONFIG_CCM))
# define STATUS_LED_PAR im_cpm.cp_pbpar
# define STATUS_LED_DIR im_cpm.cp_pbdir
# define STATUS_LED_ODR im_cpm.cp_pbodr
# define STATUS_LED_DAT im_cpm.cp_pbdat
# define STATUS_LED_BIT 0x00010000 /* green LED is on PB.15 */
# define STATUS_LED_PERIOD (CFG_HZ / 2)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** ICU862 ********************************************************/
#elif defined(CONFIG_ICU862)
# define STATUS_LED_PAR im_ioport.iop_papar
# define STATUS_LED_DIR im_ioport.iop_padir
# define STATUS_LED_ODR im_ioport.iop_paodr
# define STATUS_LED_DAT im_ioport.iop_padat
# define STATUS_LED_BIT 0x4000 /* LED 0 is on PA.1 */
# define STATUS_LED_PERIOD (CFG_HZ / 2)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_BIT1 0x1000 /* LED 1 is on PA.3 */
# define STATUS_LED_PERIOD1 (CFG_HZ)
# define STATUS_LED_STATE1 STATUS_LED_OFF
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** Someone else defines these *************************************/
#elif defined(STATUS_LED_PAR)
/*
* ADVICE: Define in your board configuration file rather than
* filling this file up with lots of custom board stuff.
*/
/***** NetVia ********************************************************/
#elif defined(CONFIG_NETVIA)
#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
#define STATUS_LED_PAR im_ioport.iop_pdpar
#define STATUS_LED_DIR im_ioport.iop_pddir
#undef STATUS_LED_ODR
#define STATUS_LED_DAT im_ioport.iop_pddat
# define STATUS_LED_BIT 0x0080 /* PD.8 */
# define STATUS_LED_PERIOD (CFG_HZ / 2)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_BIT1 0x0040 /* PD.9 */
# define STATUS_LED_PERIOD1 (CFG_HZ / 2)
# define STATUS_LED_STATE1 STATUS_LED_OFF
# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
#endif
/***** CMI ********************************************************/
#elif defined(CONFIG_CMI)
# define STATUS_LED_DIR im_mios.mios_mpiosm32ddr
# define STATUS_LED_DAT im_mios.mios_mpiosm32dr
# define STATUS_LED_BIT 0x2000 /* Select one of the 16 possible*/
/* MIOS outputs */
# define STATUS_LED_PERIOD (CFG_HZ / 2) /* Blinking periode is 500 ms */
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 0 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** KUP4K, KUP4X ****************************************************/
#elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) || defined(CONFIG_CCM)
# define STATUS_LED_PAR im_ioport.iop_papar
# define STATUS_LED_DIR im_ioport.iop_padir
# define STATUS_LED_ODR im_ioport.iop_paodr
# define STATUS_LED_DAT im_ioport.iop_padat
# define STATUS_LED_BIT 0x00000300 /* green + red PA[8]=yellow, PA[7]=red, PA[6]=green */
# define STATUS_LED_PERIOD (CFG_HZ / 2)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
#elif defined(CONFIG_SVM_SC8xx)
# define STATUS_LED_PAR im_cpm.cp_pbpar
# define STATUS_LED_DIR im_cpm.cp_pbdir
# define STATUS_LED_ODR im_cpm.cp_pbodr
# define STATUS_LED_DAT im_cpm.cp_pbdat
# define STATUS_LED_BIT 0x00000001
# define STATUS_LED_PERIOD (CFG_HZ / 2)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** RBC823 ********************************************************/
#elif defined(CONFIG_RBC823)
# define STATUS_LED_PAR im_ioport.iop_pcpar
# define STATUS_LED_DIR im_ioport.iop_pcdir
# undef STATUS_LED_ODR
# define STATUS_LED_DAT im_ioport.iop_pcdat
# define STATUS_LED_BIT 0x0002 /* LED 0 is on PC.14 */
# define STATUS_LED_PERIOD (CFG_HZ / 2)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_BIT1 0x0004 /* LED 1 is on PC.13 */
# define STATUS_LED_PERIOD1 (CFG_HZ)
# define STATUS_LED_STATE1 STATUS_LED_OFF
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** HMI10 **********************************************************/
#elif defined(CONFIG_HMI10)
# define STATUS_LED_PAR im_ioport.iop_papar
# define STATUS_LED_DIR im_ioport.iop_padir
# define STATUS_LED_ODR im_ioport.iop_paodr
# define STATUS_LED_DAT im_ioport.iop_padat
# define STATUS_LED_BIT 0x00000001 /* LED is on PA15 */
# define STATUS_LED_PERIOD (CFG_HZ / 2)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** NetPhone ********************************************************/
#elif defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
/* XXX empty just to avoid the error */
/***** STx XTc ********************************************************/
#elif defined(CONFIG_STXXTC)
/* XXX empty just to avoid the error */
/***** sbc8240 ********************************************************/
#elif defined(CONFIG_WRSBC8240)
/* XXX empty just to avoid the error */
/************************************************************************/
#elif defined(CONFIG_NIOS2)
/* XXX empty just to avoid the error */
/************************************************************************/
#elif defined(CONFIG_V38B)
# define STATUS_LED_BIT 0x0010 /* Timer7 GPIO */
# define STATUS_LED_PERIOD (CFG_HZ / 2)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
#else
# error Status LED configuration missing
#endif
/************************************************************************/
#ifndef CONFIG_BOARD_SPECIFIC_LED
# include <asm/status_led.h>
#endif
#endif /* CONFIG_STATUS_LED */
#endif /* _STATUS_LED_H_ */

31
include/systemace.h
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@ -1,31 +0,0 @@
#ifndef __SYSTEMACE_H
#define __SYSTEMACE_H
/*
* Copyright (c) 2004 Picture Elements, Inc.
* Stephen Williams (steve@picturel.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ident "$Id:$"
#ifdef CONFIG_SYSTEMACE
# include <part.h>
block_dev_desc_t * systemace_get_dev(int dev);
#endif /* CONFIG_SYSTEMACE */
#endif /* __SYSTEMACE_H */

148
include/universe.h
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@ -1,148 +0,0 @@
/*
* (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _universe_h
#define _universe_h
typedef struct _UNIVERSE UNIVERSE;
typedef struct _SLAVE_IMAGE SLAVE_IMAGE;
typedef struct _TDMA_CMD_PACKET TDMA_CMD_PACKET;
struct _SLAVE_IMAGE {
unsigned int ctl; /* Control */
unsigned int bs; /* Base */
unsigned int bd; /* Bound */
unsigned int to; /* Translation */
unsigned int reserved;
};
struct _UNIVERSE {
unsigned int pci_id;
unsigned int pci_csr;
unsigned int pci_class;
unsigned int pci_misc0;
unsigned int pci_bs;
unsigned int spare0[10];
unsigned int pci_misc1;
unsigned int spare1[48];
SLAVE_IMAGE lsi[4];
unsigned int spare2[8];
unsigned int scyc_ctl;
unsigned int scyc_addr;
unsigned int scyc_en;
unsigned int scyc_cmp;
unsigned int scyc_swp;
unsigned int lmisc;
unsigned int slsi;
unsigned int l_cmderr;
unsigned int laerr;
unsigned int spare3[27];
unsigned int dctl;
unsigned int dtbc;
unsigned int dla;
unsigned int spare4[1];
unsigned int dva;
unsigned int spare5[1];
unsigned int dcpp;
unsigned int spare6[1];
unsigned int dgcs;
unsigned int d_llue;
unsigned int spare7[54];
unsigned int lint_en;
unsigned int lint_stat;
unsigned int lint_map0;
unsigned int lint_map1;
unsigned int vint_en;
unsigned int vint_stat;
unsigned int vint_map0;
unsigned int vint_map1;
unsigned int statid;
unsigned int vx_statid[7];
unsigned int spare8[48];
unsigned int mast_ctl;
unsigned int misc_ctl;
unsigned int misc_stat;
unsigned int user_am;
unsigned int spare9[700];
SLAVE_IMAGE vsi[4];
unsigned int spare10[8];
unsigned int vrai_ctl;
unsigned int vrai_bs;
unsigned int spare11[2];
unsigned int vcsr_ctl;
unsigned int vcsr_to;
unsigned int v_amerr;
unsigned int vaerr;
unsigned int spare12[25];
unsigned int vcsr_clr;
unsigned int vcsr_set;
unsigned int vcsr_bs;
};
#define IRQ_VOWN 0x0001
#define IRQ_VIRQ1 0x0002
#define IRQ_VIRQ2 0x0004
#define IRQ_VIRQ3 0x0008
#define IRQ_VIRQ4 0x0010
#define IRQ_VIRQ5 0x0020
#define IRQ_VIRQ6 0x0040
#define IRQ_VIRQ7 0x0080
#define IRQ_DMA 0x0100
#define IRQ_LERR 0x0200
#define IRQ_VERR 0x0400
#define IRQ_res 0x0800
#define IRQ_IACK 0x1000
#define IRQ_SWINT 0x2000
#define IRQ_SYSFAIL 0x4000
#define IRQ_ACFAIL 0x8000
struct _TDMA_CMD_PACKET {
unsigned int dctl; /* DMA Control */
unsigned int dtbc; /* Transfer Byte Count */
unsigned int dlv; /* PCI Address */
unsigned int res1; /* Reserved */
unsigned int dva; /* Vme Address */
unsigned int res2; /* Reserved */
unsigned int dcpp; /* Pointer to Numed Cmd Packet with rPN */
unsigned int res3; /* Reserved */
};
#define VME_AM_A16 0x01
#define VME_AM_A24 0x02
#define VME_AM_A32 0x03
#define VME_AM_Axx 0x03
#define VME_AM_SUP 0x04
#define VME_AM_DATA 0x10
#define VME_AM_PROG 0x20
#define VME_AM_Mxx 0x30
#define VME_FLAG_D8 0x01
#define VME_FLAG_D16 0x02
#define VME_FLAG_D32 0x03
#define VME_FLAG_Dxx 0x03
#define PCI_MS_MEM 0x01
#define PCI_MS_IO 0x02
#define PCI_MS_CONFIG 0x03
#define PCI_MS_Mxx 0x03
#endif

19
include/video.h
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/*
** MPC823 Video Controller
** =======================
** (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
** AIRVENT SAM s.p.a - RIMINI(ITALY)
**
*/
#ifndef _VIDEO_H_
#define _VIDEO_H_
/* Video functions */
int video_init (void *videobase);
void video_putc (const char c);
void video_puts (const char *s);
void video_printf (const char *fmt, ...);
#endif

36
include/video_ad7179.h
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/*
* (C) Copyright 2003 Wolfgang Grandegger <wg@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _VIDEO_AD7179_H_
#define _VIDEO_AD7179_H_
/*
* The video encoder data are board specific now!
*/
#if defined(CONFIG_RRVISION)
#include "../board/RRvision/video_ad7179.h"
#else
#error "Please provide a board-specific video_ad7179.h"
#endif
#endif /* _VIDEO_AD7179_H_ */

23
include/video_easylogo.h
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/*
** video easylogo
** ==============
** (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
** AIRVENT SAM s.p.a - RIMINI(ITALY)
**
** This utility is still under construction!
*/
#ifndef _EASYLOGO_H_
#define _EASYLOGO_H_
typedef struct {
unsigned char *data;
int width;
int height;
int bpp;
int pixel_size;
int size;
} fastimage_t ;
#endif /* _EASYLOGO_H_ */

1951
include/video_logo.h
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