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Merge with /home/wd/git/u-boot/master 

Code cleanup.
This commit is contained in:
Wolfgang Denk 2006-03-06 23:18:48 +01:00
parent ac7d97dcbb bfc81252c0
commit 951a954b77
114 changed files with 4789 additions and 3604 deletions
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57
CHANGELOG
View File

@ -2,11 +2,66 @@
Changes since U-Boot 1.1.4:
======================================================================
* Merge the new NAND code (testing-NAND brach)
* Minor code cleanup
* Merge the new NAND code (testing-NAND brach); see doc/README.nand
Rewrite of NAND code based on what is in 2.6.12 Linux kernel
Patch by Ladislav Michl, 29 Jun 2005
* Add lowboot target to mcc200 board
Patch by Stefan Roese, 4 Mar 2006
* Fix problem with flash_get_size() from CFI driver update
Patch by Stefan Roese, 1 Mar 2006
* Make CFG_NO_FLASH work on ARM systems
Patch by Markus Klotzbuecher, 27 Feb 2006
* Update mcc200 config: Disable PCI and DoC, use 133 MHz IPB clock,
use hush shell.
* Convert mcc200 to use common CFI flash driver
Patch by Stefan Roese, 28 Feb 2006
* Add env-variable "unlock" to handle initial state of sectors
(locked/unlocked).
Only the U-Boot image and it's environment is protected,
all other sectors are unprotected (unlocked) if flash
hardware protection is used (CFG_FLASH_PROTECTION) and
the environment variable "unlock" is set to "yes".
Patch by Stefan Roese, 28 Feb 2006
* Update drivers/cfi_flash.c:
- find_sector() called in both versions of flash_write_cfiword()
Patch by Peter Pearse, 27th Feb 2006
* CFI support for a x8/x16 AMD/Spansion flash configured in x8 mode
Patch by Jose Maria Lopez, 16 Jan 2006
* Add support for AMD/Spansion Flashes in flash_write_cfibuffer
Patch by Alex Bastos and Thomas Schaefer, 2005-08-29
* Changes/fixes for drivers/cfi_flash.c:
We *should* check if there are any error bits if the previous call
returned ERR_OK (Otherwise we will have output an error message in
flash_status_check() already.) The original code would only check for
error bits if flash_status_check() returns ERR_TIMEOUT.
Patch by Marcus Hall, 23 Aug 2005
* Changes/fixes for drivers/cfi_flash.c:
- Add CFG_FLASH_PROTECT_CLEAR on drivers/cfi_flash.c
- Prohibit buffer write when buffer_size is 1 on drivers/cfi_flash.c
Patch by Sangmoon Kim, 19 Aug 2005
* Fixes for drivers/cfi_flash.c:
- Fix wrong timeout value usage in flash_status_check()
- Round write_tout up when converting to msec in flash_get_size()
- Remove clearing flash status at the end of flash_write_cfibuffer()
which sets Intel 28F640J3 flash back to command mode on CSB472
Patch by Tolunay Orkun, 02 July 2005
* Add basic support for the SMMACO4 Board from PanDaCom.
Patch by Heiko Schocher, 20 Feb 2006

12
MAKEALL
View File

@ -26,8 +26,8 @@ LIST_5xx=" \
LIST_5xxx=" \
cpci5200 icecube_5100 icecube_5200 EVAL5200 \
pf5200 PM520 Total5100 Total5200 \
Total5200_Rev2 TQM5200_auto o2dnt \
mcc200 o2dnt pf5200 PM520 \
Total5100 Total5200 Total5200_Rev2 TQM5200_auto \
"
#########################################################################
@ -177,10 +177,10 @@ LIST_ARM9=" \
ap920t ap922_XA10 ap926ejs ap946es \
ap966 cp920t cp922_XA10 cp926ejs \
cp946es cp966 lpd7a400 mp2usb \
mx1ads mx1fs2 omap1510inn omap1610h2 \
omap1610inn omap730p2 scb9328 smdk2400 \
smdk2410 trab VCMA9 versatile \
versatileab versatilepb voiceblue
mx1ads mx1fs2 netstar omap1510inn \
omap1610h2 omap1610inn omap730p2 scb9328 \
smdk2400 smdk2410 trab VCMA9 \
versatile versatileab versatilepb voiceblue
"
#########################################################################

19
Makefile
View File

@ -295,14 +295,23 @@ icecube_5100_config: unconfig
}
@./mkconfig -a IceCube ppc mpc5xxx icecube
inka4x0_config: unconfig
inka4x0_config: unconfig
@./mkconfig inka4x0 ppc mpc5xxx inka4x0
mcc200_config \
mcc200_lowboot_config: unconfig
@ >include/config.h
@[ -z "$(findstring lowboot_,$@)" ] || \
{ echo "TEXT_BASE = 0xFE000000" >board/mcc200/config.tmp ; \
echo "... with lowboot configuration" ; \
}
@./mkconfig mcc200 ppc mpc5xxx mcc200
o2dnt_config:
@./mkconfig -a o2dnt ppc mpc5xxx o2dnt
@./mkconfig o2dnt ppc mpc5xxx o2dnt
pf5200_config: unconfig
@./mkconfig -a pf5200 ppc mpc5xxx pf5200 esd
@./mkconfig pf5200 ppc mpc5xxx pf5200 esd
PM520_config \
PM520_DDR_config \
@ -1870,15 +1879,13 @@ clean:
rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image
rm -f board/trab/trab_fkt board/voiceblue/eeprom
rm -f board/integratorap/u-boot.lds board/integratorcp/u-boot.lds
rm -f u-boot.objdump-*
clobber: clean
find . -type f \( -name .depend \
-o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \
-print0 \
| xargs -0 rm -f
rm -f $(OBJS) *.bak tags include/version_autogenerated.h
rm -f $(OBJS) *.bak tags TAGS include/version_autogenerated.h
rm -fr *.*~
rm -f u-boot u-boot.map u-boot.hex $(ALL)
rm -f tools/crc32.c tools/environment.c tools/env/crc32.c

2
board/amcc/bamboo/bamboo.c
View File

@ -277,7 +277,7 @@ int board_early_init_f(void)
}
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
/*----------------------------------------------------------------------------+

3
board/amcc/bamboo/config.mk
View File

@ -32,3 +32,6 @@ endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
endif
# legacy nand support
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

5
board/dave/PPChameleonEVB/config.mk
View File

@ -27,5 +27,8 @@
# Reserve 320 kB for Monitor
TEXT_BASE = 0xFFFB0000
# Compile the new NAND code (needed iff #ifdef CONFIG_NEW_NAND_CODE)
# Compile the new NAND code (CFG_NAND_LEGACY mustn't be defined)
BOARDLIBS = drivers/nand/libnand.a
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
#BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

38
board/dave/PPChameleonEVB/nand.c
View File

@ -22,9 +22,8 @@
#include <common.h>
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#ifdef CONFIG_NEW_NAND_CODE
/* new NAND handling */
#include <nand.h>
@ -82,7 +81,7 @@ static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo)
break;
}
if (in32(GPIO0_IR) & rb_gpio_pin)
if (in32(GPIO0_IR) & rb_gpio_pin)
return 1;
return 0;
}
@ -90,7 +89,7 @@ static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo)
/*
* Board-specific NAND initialization. The following members of the
* argument are board-specific (per include/linux/mtd/nand_new.h):
* argument are board-specific (per include/linux/mtd/nand.h):
* - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
* - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
* - hwcontrol: hardwarespecific function for accesing control-lines
@ -115,33 +114,4 @@ void board_nand_init(struct nand_chip *nand)
nand->chip_delay = NAND_BIG_DELAY_US;
nand->options = NAND_SAMSUNG_LP_OPTIONS;
}
#else
/* old NAND handling */
extern ulong
nand_probe(ulong physadr);
void
nand_init(void)
{
ulong totlen = 0;
/*
The HI model is equipped with a large block NAND chip not supported yet
by U-Boot
(CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
*/
#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
totlen += nand_probe (CFG_NAND0_BASE);
#endif /* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */
debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE);
totlen += nand_probe (CFG_NAND1_BASE);
printf ("%3lu MB\n", totlen >>20);
}
#endif
#endif
#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */

1
board/delta/config.mk
View File

@ -6,4 +6,3 @@ TEXT_BASE = 0xa3008000
# Compile the new NAND code (needed iff #ifdef CONFIG_NEW_NAND_CODE)
BOARDLIBS = drivers/nand/libnand.a

230
board/delta/lowlevel_init.S
View File

@ -16,7 +16,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -32,33 +32,33 @@
DRAM_SIZE: .long CFG_DRAM_SIZE
/* wait for coprocessor write complete */
.macro CPWAIT reg
mrc p15,0,\reg,c2,c0,0
mov \reg,\reg
sub pc,pc,#4
.endm
.macro CPWAIT reg
mrc p15,0,\reg,c2,c0,0
mov \reg,\reg
sub pc,pc,#4
.endm
.macro wait time
ldr r2, =OSCR
mov r3, #0
str r3, [r2]
ldr r2, =OSCR
mov r3, #0
str r3, [r2]
0:
ldr r3, [r2]
cmp r3, \time
bls 0b
ldr r3, [r2]
cmp r3, \time
bls 0b
.endm
/*
* Memory setup
* Memory setup
*/
.globl lowlevel_init
lowlevel_init:
/* Set up GPIO pins first ----------------------------------------- */
mov r10, lr
/* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */
mov r10, lr
/* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */
ldr r0, =GPIO97
ldr r1, =0x801
str r1, [r0]
@ -66,24 +66,24 @@ lowlevel_init:
ldr r0, =GPIO98
ldr r1, =0x801
str r1, [r0]
/* tebrandt - ASCR, clear the RDH bit */
ldr r0, =ASCR
ldr r1, [r0]
bic r1, r1, #0x80000000
str r1, [r0]
/* tebrandt - ASCR, clear the RDH bit */
ldr r0, =ASCR
ldr r1, [r0]
bic r1, r1, #0x80000000
str r1, [r0]
/* ---------------------------------------------------------------- */
/* Enable memory interface */
/* Enable memory interface */
/* ---------------------------------------------------------------- */
/* ---------------------------------------------------------------- */
/* Step 1: Wait for at least 200 microsedonds to allow internal */
/* clocks to settle. Only necessary after hard reset... */
/* FIXME: can be optimized later */
/* Step 1: Wait for at least 200 microsedonds to allow internal */
/* clocks to settle. Only necessary after hard reset... */
/* FIXME: can be optimized later */
/* ---------------------------------------------------------------- */
; wait #300
; wait #300
mem_init:
#define NEW_SDRAM_INIT 1
@ -99,11 +99,11 @@ mem_init:
/* 2. Programm MDCNFG, leaving DMCEN de-asserted */
ldr r0, =MDCNFG
ldr r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13)
/* ldr r1, =0x80000403 */
/* ldr r1, =0x80000403 */
str r1, [r0]
ldr r1, [r0] /* delay until written */
/* 3. wait nop power up waiting period (200ms)
/* 3. wait nop power up waiting period (200ms)
* optimization: Steps 4+6 can be done during this
*/
wait #300
@ -127,7 +127,7 @@ mem_init:
ldr r1, =0x60000033
str r1, [r0]
wait #300
/* Configure MDREFR */
ldr r0, =MDREFR
ldr r1, =0x00000006
@ -142,48 +142,48 @@ mem_init:
#else /* NEW_SDRAM_INIT */
/* configure the MEMCLKCFG register */
ldr r1, =MEMCLKCFG
ldr r2, =0x00010001
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
ldr r1, =MEMCLKCFG
ldr r2, =0x00010001
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
/* set CSADRCFG[0] to data flash SRAM mode */
ldr r1, =CSADRCFG0
ldr r2, =0x00320809
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
ldr r1, =CSADRCFG0
ldr r2, =0x00320809
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
/* set CSADRCFG[1] to data flash SRAM mode */
ldr r1, =CSADRCFG1
ldr r2, =0x00320809
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
ldr r1, =CSADRCFG1
ldr r2, =0x00320809
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
/* set MSC 0 register for SRAM memory */
ldr r1, =MSC0
ldr r2, =0x11191119
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
ldr r1, =MSC0
ldr r2, =0x11191119
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
/* set CSADRCFG[2] to data flash SRAM mode */
ldr r1, =CSADRCFG2
ldr r2, =0x00320809
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
ldr r1, =CSADRCFG2
ldr r2, =0x00320809
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
/* set CSADRCFG[3] to VLIO mode */
ldr r1, =CSADRCFG3
ldr r2, =0x0032080B
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
ldr r1, =CSADRCFG3
ldr r2, =0x0032080B
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
/* set MSC 1 register for VLIO memory */
ldr r1, =MSC1
ldr r2, =0x123C1119
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
ldr r1, =MSC1
ldr r2, =0x123C1119
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
#if 0
/* This does not work in Zylonite. -SC */
@ -240,11 +240,11 @@ mem_init:
ldr r2, [r1]
/* Hardware DDR Read-Strobe Delay Calibration */
ldr r0, =DDR_HCAL @ DDR_HCAL
ldr r1, =0x803ffc07 @ the offset is correct? -SC
str r1, [r0]
ldr r0, =DDR_HCAL @ DDR_HCAL
ldr r1, =0x803ffc07 @ the offset is correct? -SC
str r1, [r0]
wait #5
ldr r1, [r0]
ldr r1, [r0]
/* Here we assume the hardware calibration alwasy be successful. -SC */
/* Set DMCEN bit in MDCNFG Register */
@ -254,20 +254,20 @@ mem_init:
str r1, [r0]
#endif /* NEW_SDRAM_INIT */
#ifndef CFG_SKIP_DRAM_SCRUB
/* scrub/init SDRAM if enabled/present */
ldr r8, =CFG_DRAM_BASE /* base address of SDRAM (CFG_DRAM_BASE) */
ldr r9, =CFG_DRAM_SIZE /* size of memory to scrub (CFG_DRAM_SIZE) */
mov r0, #0 /* scrub with 0x0000:0000 */
mov r1, #0
mov r2, #0
mov r2, #0
mov r3, #0
mov r4, #0
mov r4, #0
mov r5, #0
mov r6, #0
mov r6, #0
mov r7, #0
10: /* fastScrubLoop */
10: /* fastScrubLoop */
subs r9, r9, #32 /* 8 words/line */
stmia r8!, {r0-r7}
beq 15f
@ -281,25 +281,25 @@ mem_init:
/* Disable software and data breakpoints */
mov r0, #0
mcr p15,0,r0,c14,c8,0 // ibcr0
mcr p15,0,r0,c14,c9,0 // ibcr1
mcr p15,0,r0,c14,c4,0 // dbcon
mcr p15,0,r0,c14,c8,0 /* ibcr0 */
mcr p15,0,r0,c14,c9,0 /* ibcr1 */
mcr p15,0,r0,c14,c4,0 /* dbcon */
/* Enable all debug functionality */
mov r0,#0x80000000
mcr p14,0,r0,c10,c0,0 // dcsr
mcr p14,0,r0,c10,c0,0 /* dcsr */
endlowlevel_init:
mov pc, lr
mov pc, lr
/*
@********************************************************************************
@ DDR calibration
@
@
@ This function is used to calibrate DQS delay lines.
@ Monahans supports three ways to do it. One is software
@ Monahans supports three ways to do it. One is software
@ calibration. Two is hardware calibration. Three is hybrid
@ calibration.
@
@ -308,15 +308,15 @@ endlowlevel_init:
ddr_calibration:
@ Case 1: Write the correct delay value once
@ Configure DDR_SCAL Register
ldr r0, =DDR_SCAL @ DDR_SCAL
q ldr r1, =0xaf2f2f2f
str r1, [r0]
ldr r1, [r0]
@ Configure DDR_SCAL Register
ldr r0, =DDR_SCAL @ DDR_SCAL
q ldr r1, =0xaf2f2f2f
str r1, [r0]
ldr r1, [r0]
*/
/* @ Case 2: Software Calibration
@ Write test pattern to memory
ldr r5, =0x0faf0faf @ Data Pattern
ldr r5, =0x0faf0faf @ Data Pattern
ldr r4, =0xa0000000 @ DDR ram
str r5, [r4]
@ -328,11 +328,11 @@ ddr_loop1:
cmp r1, =0xf
ble end_loop
mov r3, r1
mov r0, r1, lsl #30
mov r0, r1, lsl #30
orr r3, r3, r0
mov r0, r1, lsl #22
mov r0, r1, lsl #22
orr r3, r3, r0
mov r0, r1, lsl #14
mov r0, r1, lsl #14
orr r3, r3, r0
orr r3, r3, =0x80000000
ldr r2, =DDR_SCAL
@ -346,16 +346,16 @@ ddr_loop2:
add r1, r1, =0x1
cmp r1, =0xf
ble end_loop
mov r3, r1
mov r0, r1, lsl #30
orr r3, r3, r0
mov r0, r1, lsl #22
orr r3, r3, r0
mov r0, r1, lsl #14
orr r3, r3, r0
orr r3, r3, =0x80000000
ldr r2, =DDR_SCAL
str r3, [r2]
mov r3, r1
mov r0, r1, lsl #30
orr r3, r3, r0
mov r0, r1, lsl #22
orr r3, r3, r0
mov r0, r1, lsl #14
orr r3, r3, r0
orr r3, r3, =0x80000000
ldr r2, =DDR_SCAL
str r3, [r2]
ldr r2, [r4]
cmp r2, r5
@ -364,22 +364,22 @@ ddr_loop2:
add r3, r6, r7
lsr r3, r3, =0x1
mov r0, r1, lsl #30
orr r3, r3, r0
mov r0, r1, lsl #22
orr r3, r3, r0
mov r0, r1, lsl #14
orr r3, r3, r0
orr r3, r3, =0x80000000
ldr r2, =DDR_SCAL
mov r0, r1, lsl #30
orr r3, r3, r0
mov r0, r1, lsl #22
orr r3, r3, r0
mov r0, r1, lsl #14
orr r3, r3, r0
orr r3, r3, =0x80000000
ldr r2, =DDR_SCAL
end_loop:
@ Case 3: Hardware Calibratoin
ldr r0, =DDR_HCAL @ DDR_HCAL
ldr r1, =0x803ffc07 @ the offset is correct? -SC
str r1, [r0]
ldr r0, =DDR_HCAL @ DDR_HCAL
ldr r1, =0x803ffc07 @ the offset is correct? -SC
str r1, [r0]
wait #5
ldr r1, [r0]
mov pc, lr
ldr r1, [r0]
mov pc, lr
*/

54
board/delta/nand.c
View File

@ -95,7 +95,7 @@ static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
unsigned long rest = len & 0x3;
unsigned long *long_buf;
int i;
DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf));
if(bytes_multi) {
for(i=0; i<bytes_multi; i+=4) {
@ -110,7 +110,7 @@ static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
}
/*
/*
* These functions are quite problematic for the DFC. Luckily they are
* not used in the current nand code, except for nand_command, which
* we've defined our own anyway. The problem is, that we always need
@ -152,7 +152,7 @@ static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
*long_buf = NDDB;
}
}
/* ...then the rest */
if(rest) {
unsigned long rest_data = NDDB;
@ -176,7 +176,7 @@ static u16 dfc_read_word(struct mtd_info *mtd)
static unsigned long read_buf = 0;
static int bytes_read = -1;
/*
/*
* read a byte from NDDB Because we can only read 4 bytes from NDDB at
* a time, we buffer the remaining bytes. The buffer is reset when a
* new command is sent to the chip.
@ -196,7 +196,7 @@ static u_char dfc_read_byte(struct mtd_info *mtd)
if(bytes_read < 0) {
read_buf = NDDB;
dummy = NDDB;
dummy = NDDB;
bytes_read = 0;
}
byte = (unsigned char) (read_buf>>(8 * bytes_read++));
@ -211,7 +211,7 @@ static u_char dfc_read_byte(struct mtd_info *mtd)
static unsigned long get_delta(unsigned long start)
{
unsigned long cur = OSCR;
if(cur < start) /* OSCR overflowed */
return (cur + (start^0xffffffff));
else
@ -239,14 +239,14 @@ static void dfc_clear_nddb()
static unsigned long dfc_wait_event(unsigned long event)
{
unsigned long ndsr, timeout, start = OSCR;
if(!event)
return 0xff000000;
else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
else
timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ;
while(1) {
ndsr = NDSR;
if(ndsr & event) {
@ -257,7 +257,7 @@ static unsigned long dfc_wait_event(unsigned long event)
DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x.\n", event);
return 0xff000000;
}
}
return ndsr;
}
@ -271,13 +271,13 @@ static void dfc_new_cmd()
while(retry++ <= CFG_NAND_SENDCMD_RETRY) {
/* Clear NDSR */
NDSR = 0xFFF;
/* set NDCR[NDRUN] */
if(!(NDCR & NDCR_ND_RUN))
NDCR |= NDCR_ND_RUN;
status = dfc_wait_event(NDSR_WRCMDREQ);
if(status & NDSR_WRCMDREQ)
return;
@ -303,7 +303,7 @@ static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
} else if(state == FL_ERASING) {
event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
}
ndsr = dfc_wait_event(event);
if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
@ -312,7 +312,7 @@ static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
}
/* cmdfunc send commands to the DFC */
static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
int column, int page_addr)
{
/* register struct nand_chip *this = mtd->priv; */
@ -404,7 +404,7 @@ static void dfc_gpio_init()
/* no idea what is done here, see zylonite.c */
GPIO4 = 0x1;
DF_ALE_WE1 = 0x00000001;
DF_ALE_WE2 = 0x00000001;
DF_nCS0 = 0x00000001;
@ -464,10 +464,10 @@ void board_nand_init(struct nand_chip *nand)
CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
#undef CFG_TIMING_TIGHT
#ifndef CFG_TIMING_TIGHT
tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
#ifndef CFG_TIMING_TIGHT
tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
DFC_MAX_tCH);
tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
DFC_MAX_tCS);
tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
DFC_MAX_tWH);
@ -485,9 +485,9 @@ void board_nand_init(struct nand_chip *nand)
DFC_MAX_tAR);
#else /* this is the tight timing */
tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
DFC_MAX_tCH);
tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
DFC_MAX_tCS);
tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
DFC_MAX_tWH);
@ -523,13 +523,11 @@ void board_nand_init(struct nand_chip *nand)
(tRP_high << 6) |
(tRH << 3) |
(tRP << 0);
NDTR1CS0 = (tR << 16) |
(tWHR << 4) |
(tAR << 0);
/* If it doesn't work (unlikely) think about:
* - ecc enable
* - chip select don't care
@ -544,7 +542,7 @@ void board_nand_init(struct nand_chip *nand)
* - ND_RDY : clears command buffer
*/
/* NDCR_NCSX | /\* Chip select busy don't care *\/ */
NDCR = (NDCR_SPARE_EN | /* use the spare area */
NDCR_DWIDTH_C | /* 16bit DFC data bus width */
NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
@ -557,17 +555,17 @@ void board_nand_init(struct nand_chip *nand)
NDCR_CS1_CMDDM |
NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */
NDCR_CS1_BBDM |
NDCR_DBERRM | /* double bit error ir masked */
NDCR_DBERRM | /* double bit error ir masked */
NDCR_SBERRM | /* single bit error ir masked */
NDCR_WRDREQM | /* write data request ir masked */
NDCR_RDDREQM | /* read data request ir masked */
NDCR_WRCMDREQM); /* write command request ir masked */
/* wait 10 us due to cmd buffer clear reset */
/* wait(10); */
nand->hwcontrol = dfc_hwcontrol;
/* nand->dev_ready = dfc_device_ready; */
nand->eccmode = NAND_ECC_SOFT;

2
board/esd/ash405/ash405.c
View File

@ -239,7 +239,7 @@ int testdram (void)
/* ------------------------------------------------------------------------- */
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)

3
board/esd/ash405/config.mk
View File

@ -26,3 +26,6 @@
#
TEXT_BASE = 0xFFFC0000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

2
board/esd/cms700/cms700.c
View File

@ -238,7 +238,7 @@ U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
/* ------------------------------------------------------------------------- */
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)

3
board/esd/cms700/config.mk
View File

@ -26,3 +26,6 @@
#
TEXT_BASE = 0xFFFC0000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

25
board/esd/common/auto_update.c
View File

@ -23,10 +23,15 @@
*/
#include <common.h>
#ifndef CFG_NAND_LEGACY
#error CFG_NAND_LEGACY not defined in a file using the legacy NAND support!
#endif
#include <command.h>
#include <image.h>
#include <asm/byteorder.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
#include <fat.h>
#include "auto_update.h"
@ -76,9 +81,9 @@ extern block_dev_desc_t *get_dev (char*, int);
#define NANDRW_JFFS2 0x02
#define NANDRW_JFFS2_SKIP 0x04
extern struct nand_chip nand_dev_desc[];
extern int nand_rw(struct nand_chip* nand, int cmd, size_t start, size_t len,
extern int nand_legacy_rw(struct nand_chip* nand, int cmd, size_t start, size_t len,
size_t * retlen, u_char * buf);
extern int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean);
extern int nand_legacy_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean);
#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
extern block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE];
@ -259,9 +264,9 @@ int au_do_update(int i, long sz)
} else {
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
printf("Updating NAND FLASH with image %s\n", au_image[i].name);
debug ("nand_erase(%lx, %lx);\n", start, end);
rc = nand_erase (nand_dev_desc, start, end - start + 1, 0);
debug ("nand_erase returned %x\n", rc);
debug ("nand_legacy_erase(%lx, %lx);\n", start, end);
rc = nand_legacy_erase (nand_dev_desc, start, end - start + 1, 0);
debug ("nand_legacy_erase returned %x\n", rc);
#endif
}
@ -286,10 +291,10 @@ int au_do_update(int i, long sz)
rc = flash_write((char *)addr, start, nbytes);
} else {
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
debug ("nand_rw(%p, %lx %x)\n", addr, start, nbytes);
rc = nand_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2,
debug ("nand_legacy_rw(%p, %lx %x)\n", addr, start, nbytes);
rc = nand_legacy_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2,
start, nbytes, (size_t *)&total, (uchar *)addr);
debug ("nand_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes);
debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes);
#endif
}
if (rc != 0) {
@ -304,7 +309,7 @@ int au_do_update(int i, long sz)
rc = crc32 (0, (uchar *)(start + off), ntohl(hdr->ih_size));
} else {
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
rc = nand_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP,
rc = nand_legacy_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP,
start, nbytes, (size_t *)&total, (uchar *)addr);
rc = crc32 (0, (uchar *)(addr + off), ntohl(hdr->ih_size));
#endif

1
board/esd/common/cmd_loadpci.c
View File

@ -120,4 +120,3 @@ U_BOOT_CMD(
);
#endif

4
board/esd/cpci2dp/cpci2dp.c
View File

@ -36,9 +36,9 @@ int board_early_init_f (void)
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | ((CFG_EEPROM_WP | CFG_PB_LED | CFG_SELF_RST | CFG_INTA_FAKE) << 5));
/* set output pins to high */
/* set output pins to high */
out32(GPIO0_OR, CFG_EEPROM_WP);
/* setup for output (LED=off) */
/* setup for output (LED=off) */
out32(GPIO0_TCR, CFG_EEPROM_WP | CFG_PB_LED);
/*

3
board/esd/cpci405/config.mk
View File

@ -38,3 +38,6 @@ TEXT_BASE = 0xFFFD0000
endif
endif
endif
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

1
board/esd/cpci750/cpci750.c
View File

@ -378,7 +378,6 @@ int misc_init_r ()
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[3]);
}
return 0;
}

192
board/esd/cpci750/pci.c
View File

@ -12,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -46,8 +46,8 @@ static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
#ifdef CONFIG_USE_CPCIDVI
typedef struct {
unsigned int base;
unsigned int init;
unsigned int base;
unsigned int init;
} GT_CPCIDVI_ROM_T;
static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0};
@ -133,20 +133,20 @@ static const unsigned int pci_p2p_configuration[] = {
/********************************************************************
* pciWriteConfigReg - Write to a PCI configuration register
* - Make sure the GT is configured as a master before writing
* to another device on the PCI.
* - The function takes care of Big/Little endian conversion.
* - Make sure the GT is configured as a master before writing
* to another device on the PCI.
* - The function takes care of Big/Little endian conversion.
*
*
* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec
* (or any other PCI device spec)
* pciDevNum: The device number needs to be addressed.
* (or any other PCI device spec)
* pciDevNum: The device number needs to be addressed.
*
* Configuration Address 0xCF8:
*
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
* |congif|Reserved| Bus |Device|Function|Register|00|
* |Enable| |Number|Number| Number | Number | | <=field Name
* |Enable| |Number|Number| Number | Number | | <=field Name
*
*********************************************************************/
void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
@ -180,20 +180,20 @@ void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
/********************************************************************
* pciReadConfigReg - Read from a PCI0 configuration register
* - Make sure the GT is configured as a master before reading
* from another device on the PCI.
* - The function takes care of Big/Little endian conversion.
* - Make sure the GT is configured as a master before reading
* from another device on the PCI.
* - The function takes care of Big/Little endian conversion.
* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
* spec)
* pciDevNum: The device number needs to be addressed.
* spec)
* pciDevNum: The device number needs to be addressed.
* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
* cause register to make sure the data is valid
* cause register to make sure the data is valid
*
* Configuration Address 0xCF8:
*
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
* |congif|Reserved| Bus |Device|Function|Register|00|
* |Enable| |Number|Number| Number | Number | | <=field Name
* |Enable| |Number|Number| Number | Number | | <=field Name
*
*********************************************************************/
unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
@ -228,21 +228,21 @@ unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
/********************************************************************
* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
* the agent is placed on another Bus. For more
* information read P2P in the PCI spec.
* the agent is placed on another Bus. For more
* information read P2P in the PCI spec.
*
* Inputs: unsigned int regOffset - The register offset as it apears in the
* GT spec (or any other PCI device spec).
* unsigned int pciDevNum - The device number needs to be addressed.
* unsigned int busNum - On which bus does the Target agent connect
* to.
* unsigned int data - data to be written.
* GT spec (or any other PCI device spec).
* unsigned int pciDevNum - The device number needs to be addressed.
* unsigned int busNum - On which bus does the Target agent connect
* to.
* unsigned int data - data to be written.
*
* Configuration Address 0xCF8:
*
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
* |congif|Reserved| Bus |Device|Function|Register|01|
* |Enable| |Number|Number| Number | Number | | <=field Name
* |Enable| |Number|Number| Number | Number | | <=field Name
*
* The configuration Address is configure as type-I (bits[1:0] = '01') due to
* PCI spec referring to P2P.
@ -273,23 +273,23 @@ void pciOverBridgeWriteConfigReg (PCI_HOST host,
/********************************************************************
* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where
* the agent target locate on another PCI bus.
* - Make sure the GT is configured as a master
* before reading from another device on the PCI.
* - The function takes care of Big/Little endian
* conversion.
* the agent target locate on another PCI bus.
* - Make sure the GT is configured as a master
* before reading from another device on the PCI.
* - The function takes care of Big/Little endian
* conversion.
* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
* spec). (configuration register offset.)
* pciDevNum: The device number needs to be addressed.
* busNum: the Bus number where the agent is place.
* spec). (configuration register offset.)
* pciDevNum: The device number needs to be addressed.
* busNum: the Bus number where the agent is place.
* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
* cause register to make sure the data is valid
* cause register to make sure the data is valid
*
* Configuration Address 0xCF8:
*
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
* |congif|Reserved| Bus |Device|Function|Register|01|
* |Enable| |Number|Number| Number | Number | | <=field Name
* |Enable| |Number|Number| Number | Number | | <=field Name
*
*********************************************************************/
unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
@ -393,7 +393,7 @@ static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
/********************************************************************
* pciGetBaseAddress - Gets the base address of a PCI.
* - If the PCI size is 0 then this base address has no meaning!!!
* - If the PCI size is 0 then this base address has no meaning!!!
*
*
* INPUT: Bus, Region - The bus and region we ask for its base address.
@ -501,13 +501,13 @@ void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
/********************************************************************
* pciSetRegionFeatures - This function modifys one of the 8 regions with
* feature bits given as an input.
* - Be advised to check the spec before modifying them.
* feature bits given as an input.
* - Be advised to check the spec before modifying them.
* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
* unsigned int features - See file: pci.h there are defintion for those
* region features.
* unsigned int baseAddress - The region base Address.
* unsigned int topAddress - The region top Address.
* unsigned int features - See file: pci.h there are defintion for those
* region features.
* unsigned int baseAddress - The region base Address.
* unsigned int topAddress - The region top Address.
* Returns: false if one of the parameters is erroneous true otherwise.
*********************************************************************/
bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
@ -541,7 +541,7 @@ bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
/********************************************************************
* pciDisableAccessRegion - Disable The given Region by writing MAX size
* to its low Address and MIN size to its high Address.
* to its low Address and MIN size to its high Address.
*
* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled.
* Returns: N/A.
@ -588,12 +588,12 @@ bool pciArbiterDisable (PCI_HOST host)
* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
*
* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent.
* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
* Returns: true
*********************************************************************/
bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
@ -619,17 +619,17 @@ bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
/********************************************************************
* pciParkingDisable - Park on last option disable, with this function you can
* disable the park on last mechanism for each agent.
* disabling this option for all agents results parking
* on the internal master.
* disable the park on last mechanism for each agent.
* disabling this option for all agents results parking
* on the internal master.
*
* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent.
* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
* Returns: true
*********************************************************************/
bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
@ -655,11 +655,11 @@ bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
/********************************************************************
* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
* respond to grant assertion within a window specified in
* the input value: 'brokenValue'.
* respond to grant assertion within a window specified in
* the input value: 'brokenValue'.
*
* Inputs: unsigned char brokenValue - A value which limits the Master to hold the
* grant without asserting frame.
* grant without asserting frame.
* Returns: Error for illegal broken value otherwise true.
*********************************************************************/
bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
@ -678,9 +678,9 @@ bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
/********************************************************************
* pciDisableBrokenAgentDetection - This function disable the Broken agent
* Detection mechanism.
* NOTE: This operation may cause a dead lock on the
* pci0 arbitration.
* Detection mechanism.
* NOTE: This operation may cause a dead lock on the
* pci0 arbitration.
*
* Inputs: N/A
* Returns: true.
@ -697,15 +697,15 @@ bool pciDisableBrokenAgentDetection (PCI_HOST host)
/********************************************************************
* pciP2PConfig - This function set the PCI_n P2P configurate.
* For more information on the P2P read PCI spec.
* For more information on the P2P read PCI spec.
*
* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
* Boundry.
* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
* Boundry.
* unsigned int busNum - The CPI bus number to which the PCI interface
* is connected.
* unsigned int devNum - The PCI interface's device number.
* Boundry.
* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
* Boundry.
* unsigned int busNum - The CPI bus number to which the PCI interface
* is connected.
* unsigned int devNum - The PCI interface's device number.
*
* Returns: true.
*********************************************************************/
@ -723,15 +723,15 @@ bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
/********************************************************************
* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
* supports Cache Coherency in the PCI_n interface.
* supports Cache Coherency in the PCI_n interface.
* Inputs: region - One of the four regions.
* snoopType - There is four optional Types:
* 1. No Snoop.
* 2. Snoop to WT region.
* 3. Snoop to WB region.
* 4. Snoop & Invalidate to WB region.
* baseAddress - Base Address of this region.
* regionLength - Region length.
* snoopType - There is four optional Types:
* 1. No Snoop.
* 2. Snoop to WT region.
* 3. Snoop to WB region.
* 4. Snoop & Invalidate to WB region.
* baseAddress - Base Address of this region.
* regionLength - Region length.
* Returns: false if one of the parameters is wrong otherwise return true.
*********************************************************************/
bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
@ -754,7 +754,7 @@ bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
GT_REG_WRITE (snoopXtopAddress, 0);
return true;
}
baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
data = (baseAddress >> 20) | snoopType << 12;
GT_REG_WRITE (snoopXbaseAddress, data);
snoopHigh = (snoopHigh & 0xfff00000) >> 20;
@ -827,7 +827,7 @@ static void gt_setup_ide (struct pci_controller *hose,
static void gt_setup_cpcidvi (struct pci_controller *hose,
pci_dev_t dev, struct pci_config_table *entry)
{
u32 bar_value, pci_response;
u32 bar_value, pci_response;
pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response);
pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
@ -843,30 +843,30 @@ static void gt_setup_cpcidvi (struct pci_controller *hose,
unsigned char gt_cpcidvi_in8(unsigned int offset)
{
unsigned char data;
unsigned char data;
if (gt_cpcidvi_rom.init == 0) {
return(0);
}
data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base);
return(data);
return(0);
}
data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base);
return(data);
}
void gt_cpcidvi_out8(unsigned int offset, unsigned char data)
{
unsigned int off;
unsigned int off;
if (gt_cpcidvi_rom.init == 0) {
return;
}
return;
}
off = data;
off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base;
in8(off);
return;
in8(off);
return;
}
#endif
/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */
/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */
/* and is curently not called *. */
#if 0
static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)

3
board/esd/hh405/config.mk
View File

@ -29,3 +29,6 @@
TEXT_BASE = 0xFFF80000
#TEXT_BASE = 0xFFFC0000
#TEXT_BASE = 0x00FC0000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

2
board/esd/hh405/hh405.c
View File

@ -697,7 +697,7 @@ void ide_set_reset(int on)
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)

3
board/esd/hub405/config.mk
View File

@ -26,3 +26,6 @@
#
TEXT_BASE = 0xFFFC0000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

2
board/esd/hub405/hub405.c
View File

@ -265,7 +265,7 @@ int testdram (void)
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)

3
board/esd/plu405/config.mk
View File

@ -27,3 +27,6 @@
TEXT_BASE = 0xFFFC0000
#TEXT_BASE = 0x00FC0000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

2
board/esd/plu405/plu405.c
View File

@ -269,7 +269,7 @@ void ide_set_reset(int on)
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)

3
board/esd/voh405/config.mk
View File

@ -26,3 +26,6 @@
#
TEXT_BASE = 0xFFF80000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

2
board/esd/voh405/voh405.c
View File

@ -343,7 +343,7 @@ void ide_set_reset(int on)
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)

3
board/esd/wuh405/config.mk
View File

@ -26,3 +26,6 @@
#
TEXT_BASE = 0xFFFC0000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

2
board/esd/wuh405/wuh405.c
View File

@ -239,7 +239,7 @@ int testdram (void)
/* ------------------------------------------------------------------------- */
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)

2
board/g2000/g2000.c
View File

@ -185,7 +185,7 @@ int testdram (void)
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)

46
board/mcc200/Makefile Normal file
View File

@ -0,0 +1,46 @@
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := $(BOARD).o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

43
board/mcc200/config.mk Normal file
View File

@ -0,0 +1,43 @@
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# MCC200 board:
#
# Valid values for TEXT_BASE are:
#
# 0xFFF00000 boot high (standard configuration)
# 0xFE000000 boot low
# 0x00100000 boot from RAM (for testing only)
#
sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
## Standard: boot high
TEXT_BASE = 0xFFF00000
## For testing: boot from RAM
# TEXT_BASE = 0x00100000
endif
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board

276
board/mcc200/mcc200.c Normal file
View File

@ -0,0 +1,276 @@
/*
* (C) Copyright 2003-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
#include "mt48lc8m32b2-6-7.h"
extern flash_info_t flash_info[]; /* FLASH chips info */
ulong flash_get_size (ulong base, int banknum);
#ifndef CFG_RAMBOOT
static void sdram_start (int hi_addr)
{
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
/* unlock mode register */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
__asm__ volatile ("sync");
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set mode register: extended mode */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
__asm__ volatile ("sync");
/* set mode register: reset DLL */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
__asm__ volatile ("sync");
#endif
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
/* auto refresh */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
__asm__ volatile ("sync");
/* set mode register */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
__asm__ volatile ("sync");
/* normal operation */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
__asm__ volatile ("sync");
}
#endif
/*
* ATTENTION: Although partially referenced initdram does NOT make real use
* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
* is something else than 0x00000000.
*/
long int initdram (int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
#ifndef CFG_RAMBOOT
ulong test1, test2;
/* setup SDRAM chip selects */
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
__asm__ volatile ("sync");
/* setup config registers */
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set tap delay */
*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
__asm__ volatile ("sync");
#endif
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
sdram_start(1);
test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
} else {
dramsize = test2;
}
/* memory smaller than 1MB is impossible */
if (dramsize < (1 << 20)) {
dramsize = 0;
}
/* set SDRAM CS0 size according to the amount of RAM found */
if (dramsize > 0) {
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
} else {
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
}
/* let SDRAM CS1 start right after CS0 */
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
/* find RAM size using SDRAM CS1 only */
if (!dramsize)
sdram_start(0);
test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
if (!dramsize) {
sdram_start(1);
test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
}
if (test1 > test2) {
sdram_start(0);
dramsize2 = test1;
} else {
dramsize2 = test2;
}
/* memory smaller than 1MB is impossible */
if (dramsize2 < (1 << 20)) {
dramsize2 = 0;
}
/* set SDRAM CS1 size according to the amount of RAM found */
if (dramsize2 > 0) {
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
} else {
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
}
#else /* CFG_RAMBOOT */
/* retrieve size of memory connected to SDRAM CS0 */
dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
if (dramsize >= 0x13) {
dramsize = (1 << (dramsize - 0x13)) << 20;
} else {
dramsize = 0;
}
/* retrieve size of memory connected to SDRAM CS1 */
dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
if (dramsize2 >= 0x13) {
dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
} else {
dramsize2 = 0;
}
#endif /* CFG_RAMBOOT */
return dramsize + dramsize2;
}
int checkboard (void)
{
puts ("Board: MCC200\n");
return 0;
}
int misc_init_r (void)
{
DECLARE_GLOBAL_DATA_PTR;
/*
* Adjust flash start and offset to detected values
*/
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
/*
* Check if boot FLASH isn't max size
*/
if (gd->bd->bi_flashsize < (0 - CFG_FLASH_BASE)) {
/* adjust mapping */
*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
START_REG(gd->bd->bi_flashstart);
*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize);
/*
* Re-check to get correct base address
*/
flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
/*
* Re-do flash protection upon new addresses
*/
flash_protect (FLAG_PROTECT_CLEAR,
gd->bd->bi_flashstart, 0xffffffff,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
/* Monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
/* Environment protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
/* Redundant environment protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
}
return (0);
}
#ifdef CONFIG_PCI
static struct pci_controller hose;
extern void pci_mpc5xxx_init(struct pci_controller *);
void pci_init_board(void)
{
pci_mpc5xxx_init(&hose);
}
#endif
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
void init_ide_reset (void)
{
debug ("init_ide_reset\n");
}
void ide_set_reset (int idereset)
{
debug ("ide_reset(%d)\n", idereset);
}
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
#if (CONFIG_COMMANDS & CFG_CMD_DOC)
extern void doc_probe (ulong physadr);
void doc_init (void)
{
doc_probe (CFG_DOC_BASE);
}
#endif

37
board/mcc200/mt46v16m16-75.h Normal file
View File

@ -0,0 +1,37 @@
/*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define SDRAM_DDR 1 /* is DDR */
#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONTROL 0x714f0f00
#define SDRAM_CONFIG1 0x73722930
#define SDRAM_CONFIG2 0x47770000
#define SDRAM_TAPDELAY 0x10000000
#else
#error CONFIG_MPC5200 not defined
#endif

43
board/mcc200/mt48lc16m16a2-75.h Normal file
View File

@ -0,0 +1,43 @@
/*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define SDRAM_DDR 0 /* is SDR */
#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x00CD0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xD2322800
#define SDRAM_CONFIG2 0x8AD70000
#elif defined(CONFIG_MGT5100)
/* Settings for XLB = 66 MHz */
#define SDRAM_MODE 0x008D0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xC2222600
#define SDRAM_CONFIG2 0x88B70004
#define SDRAM_ADDRSEL 0x02000000
#else
#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
#endif

12
board/mcc200/mt48lc8m32b2-6-7.h Normal file
View File

@ -0,0 +1,12 @@
/*
* Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform
*/
#define SDRAM_DDR 0 /* is SDR */
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */
#define SDRAM_CONTROL 0x504f0000 /* Control Register MBAR + 0x0104 */
#define SDRAM_CONFIG1 0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */
#define SDRAM_CONFIG2 0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */

125
board/mcc200/u-boot.lds Normal file
View File

@ -0,0 +1,125 @@
/*
* (C) Copyright 2003-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc5xxx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

3
board/netphone/config.mk
View File

@ -26,3 +26,6 @@
#
TEXT_BASE = 0x40000000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

2
board/netphone/netphone.c
View File

@ -599,7 +599,7 @@ int board_early_init_f(void)
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern ulong nand_probe(ulong physadr);
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];

3
board/netstar/config.mk
View File

@ -10,6 +10,5 @@
# XXX TEXT_BASE = 0x20012000
TEXT_BASE = 0x13FC0000
# Compile the new NAND code (needed iff #ifdef CONFIG_NEW_NAND_CODE)
# Compile the new NAND code
BOARDLIBS = drivers/nand/libnand.a

4
board/netstar/setup.S
View File

@ -129,8 +129,8 @@ MUX_CONFIG_OFFSETS:
.byte 0x0c @ COMP_MODE_CTRL_0
.byte 0xff
.globl platformsetup
platformsetup:
.globl lowlevel_init
lowlevel_init:
/* Improve performance a bit... */
mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register
mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register

3
board/netta2/config.mk
View File

@ -26,3 +26,6 @@
#
TEXT_BASE = 0x40000000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

2
board/netta2/netta2.c
View File

@ -597,7 +597,7 @@ int board_early_init_f(void)
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern ulong nand_probe(ulong physadr);
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];

3
board/netvia/config.mk
View File

@ -26,3 +26,6 @@
#
TEXT_BASE = 0x40000000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

2
board/netvia/netvia.c
View File

@ -418,7 +418,7 @@ int board_early_init_f(void)
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern ulong nand_probe(ulong physadr);
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];

2
board/omap2420h4/omap2420h4.c
View File

@ -32,7 +32,7 @@
#include <i2c.h>
#include <asm/mach-types.h>
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
#endif

3
board/sixnet/config.mk
View File

@ -26,3 +26,6 @@
#
TEXT_BASE = 0xF8000000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

2
board/sixnet/sixnet.c
View File

@ -34,7 +34,7 @@
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
#endif

2
board/stxxtc/stxxtc.c
View File

@ -576,7 +576,7 @@ int board_early_init_f(void)
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern ulong nand_probe(ulong physadr);
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];

2
board/tqm85xx/tqm85xx.c
View File

@ -296,7 +296,7 @@ int misc_init_r (void)
/* Monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE, 0xffffffff,
CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
/* Environment protection ON by default */

364
board/zylonite/lowlevel_init.S
View File

@ -16,7 +16,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -32,140 +32,140 @@
DRAM_SIZE: .long CFG_DRAM_SIZE
/* wait for coprocessor write complete */
.macro CPWAIT reg
mrc p15,0,\reg,c2,c0,0
mov \reg,\reg
sub pc,pc,#4
.endm
.macro CPWAIT reg
mrc p15,0,\reg,c2,c0,0
mov \reg,\reg
sub pc,pc,#4
.endm
.macro wait time
ldr r2, =OSCR
mov r3, #0
str r3, [r2]
ldr r2, =OSCR
mov r3, #0
str r3, [r2]
0:
ldr r3, [r2]
cmp r3, \time
bls 0b
ldr r3, [r2]
cmp r3, \time
bls 0b
.endm
/*
* Memory setup
* Memory setup
*/
.globl lowlevel_init
lowlevel_init:
/* Set up GPIO pins first ----------------------------------------- */
mov r10, lr
/* Configure GPIO Pins 41 - 48 as UART1 / altern. Fkt. 2 */
ldr r0, =0x40E10438 @ GPIO41 FFRXD
ldr r1, =0x802
str r1, [r0]
mov r10, lr
ldr r0, =0x40E1043C @ GPIO42 FFTXD
ldr r1, =0x802
str r1, [r0]
/* Configure GPIO Pins 41 - 48 as UART1 / altern. Fkt. 2 */
ldr r0, =0x40E10438 @ GPIO41 FFRXD
ldr r1, =0x802
str r1, [r0]
ldr r0, =0x40E10440 @ GPIO43 FFCTS
ldr r1, =0x802
str r1, [r0]
ldr r0, =0x40E1043C @ GPIO42 FFTXD
ldr r1, =0x802
str r1, [r0]
ldr r0, =0x40E10444 @ GPIO 44 FFDCD
ldr r1, =0x802
str r1, [r0]
ldr r0, =0x40E10440 @ GPIO43 FFCTS
ldr r1, =0x802
str r1, [r0]
ldr r0, =0x40E10448 @ GPIO 45 FFDSR
ldr r1, =0x802
str r1, [r0]
ldr r0, =0x40E10444 @ GPIO 44 FFDCD
ldr r1, =0x802
str r1, [r0]
ldr r0, =0x40E1044C @ GPIO 46 FFRI
ldr r1, =0x802
str r1, [r0]
ldr r0, =0x40E10448 @ GPIO 45 FFDSR
ldr r1, =0x802
str r1, [r0]
ldr r0, =0x40E10450 @ GPIO 47 FFDTR
ldr r1, =0x802
str r1, [r0]
ldr r0, =0x40E1044C @ GPIO 46 FFRI
ldr r1, =0x802
str r1, [r0]
ldr r0, =0x40E10454 @ GPIO 48
ldr r1, =0x802
str r1, [r0]
ldr r0, =0x40E10450 @ GPIO 47 FFDTR
ldr r1, =0x802
str r1, [r0]
ldr r0, =0x40E10454 @ GPIO 48
ldr r1, =0x802
str r1, [r0]
/* tebrandt - ASCR, clear the RDH bit */
ldr r0, =ASCR
ldr r1, [r0]
bic r1, r1, #0x80000000
str r1, [r0]
/* tebrandt - ASCR, clear the RDH bit */
ldr r0, =ASCR
ldr r1, [r0]
bic r1, r1, #0x80000000
str r1, [r0]
/* ---------------------------------------------------------------- */
/* Enable memory interface */
/* */
/* The sequence below is based on the recommended init steps */
/* Enable memory interface */
/* */
/* The sequence below is based on the recommended init steps */
/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
/* Chapter 10. */
/* Chapter 10. */
/* ---------------------------------------------------------------- */
/* ---------------------------------------------------------------- */
/* Step 1: Wait for at least 200 microsedonds to allow internal */
/* clocks to settle. Only necessary after hard reset... */
/* FIXME: can be optimized later */
/* Step 1: Wait for at least 200 microsedonds to allow internal */
/* clocks to settle. Only necessary after hard reset... */
/* FIXME: can be optimized later */
/* ---------------------------------------------------------------- */
/* mk: replaced with wait macro */
/* ldr r3, =OSCR /\* reset the OS Timer Count to zero *\/ */
/* mov r2, #0 */
/* str r2, [r3] */
/* ldr r4, =0x300 /\* really 0x2E1 is about 200usec, *\/ */
/* /\* so 0x300 should be plenty *\/ */
/* ldr r3, =OSCR /\* reset the OS Timer Count to zero *\/ */
/* mov r2, #0 */
/* str r2, [r3] */
/* ldr r4, =0x300 /\* really 0x2E1 is about 200usec, *\/ */
/* /\* so 0x300 should be plenty *\/ */
/* 1: */
/* ldr r2, [r3] */
/* cmp r4, r2 */
/* bgt 1b */
/* ldr r2, [r3] */
/* cmp r4, r2 */
/* bgt 1b */
wait #300
mem_init:
/* configure the MEMCLKCFG register */
ldr r1, =MEMCLKCFG
ldr r2, =0x00010001
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
ldr r1, =MEMCLKCFG
ldr r2, =0x00010001
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
/* set CSADRCFG[0] to data flash SRAM mode */
ldr r1, =CSADRCFG0
ldr r2, =0x00320809
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
ldr r1, =CSADRCFG0
ldr r2, =0x00320809
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
/* set CSADRCFG[1] to data flash SRAM mode */
ldr r1, =CSADRCFG1
ldr r2, =0x00320809
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
ldr r1, =CSADRCFG1
ldr r2, =0x00320809
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
/* set MSC 0 register for SRAM memory */
ldr r1, =MSC0
ldr r2, =0x11191119
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
ldr r1, =MSC0
ldr r2, =0x11191119
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
/* set CSADRCFG[2] to data flash SRAM mode */
ldr r1, =CSADRCFG2
ldr r2, =0x00320809
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
ldr r1, =CSADRCFG2
ldr r2, =0x00320809
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
/* set CSADRCFG[3] to VLIO mode */
ldr r1, =CSADRCFG3
ldr r2, =0x0032080B
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
ldr r1, =CSADRCFG3
ldr r2, =0x0032080B
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
/* set MSC 1 register for VLIO memory */
ldr r1, =MSC1
ldr r2, =0x123C1119
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
ldr r1, =MSC1
ldr r2, =0x123C1119
str r2, [r1] @ WRITE
ldr r2, [r1] @ DELAY UNTIL WRITTEN
#if 0
/* This does not work in Zylonite. -SC */
@ -222,11 +222,11 @@ mem_init:
ldr r2, [r1]
/* Hardware DDR Read-Strobe Delay Calibration */
ldr r0, =DDR_HCAL @ DDR_HCAL
ldr r1, =0x803ffc07 @ the offset is correct? -SC
str r1, [r0]
ldr r0, =DDR_HCAL @ DDR_HCAL
ldr r1, =0x803ffc07 @ the offset is correct? -SC
str r1, [r0]
wait #5
ldr r1, [r0]
ldr r1, [r0]
/* Here we assume the hardware calibration alwasy be successful. -SC */
/* Set DMCEN bit in MDCNFG Register */
@ -236,21 +236,21 @@ mem_init:
str r1, [r0]
/* scrub/init SDRAM if enabled/present */
/* ldr r11, =0xa0000000 /\* base address of SDRAM (CFG_DRAM_BASE) *\/ */
/* ldr r12, =0x04000000 /\* size of memory to scrub (CFG_DRAM_SIZE) *\/ */
/* mov r8,r12 /\* save DRAM size (mk: why???) *\/ */
ldr r8, =0xa0000000 /* base address of SDRAM (CFG_DRAM_BASE) */
ldr r9, =0x04000000 /* size of memory to scrub (CFG_DRAM_SIZE) */
/* ldr r11, =0xa0000000 /\* base address of SDRAM (CFG_DRAM_BASE) *\/ */
/* ldr r12, =0x04000000 /\* size of memory to scrub (CFG_DRAM_SIZE) *\/ */
/* mov r8,r12 /\* save DRAM size (mk: why???) *\/ */
ldr r8, =0xa0000000 /* base address of SDRAM (CFG_DRAM_BASE) */
ldr r9, =0x04000000 /* size of memory to scrub (CFG_DRAM_SIZE) */
mov r0, #0 /* scrub with 0x0000:0000 */
mov r1, #0
mov r2, #0
mov r2, #0
mov r3, #0
mov r4, #0
mov r4, #0
mov r5, #0
mov r6, #0
mov r6, #0
mov r7, #0
10: /* fastScrubLoop */
subs r9, r9, #32 // 32 bytes/line
10: /* fastScrubLoop */
subs r9, r9, #32 /* 32 bytes/line */
stmia r8!, {r0-r7}
beq 15f
b 10b
@ -262,34 +262,30 @@ mem_init:
/* Disable software and data breakpoints */
mov r0, #0
mcr p15,0,r0,c14,c8,0 // ibcr0
mcr p15,0,r0,c14,c9,0 // ibcr1
mcr p15,0,r0,c14,c4,0 // dbcon
mcr p15,0,r0,c14,c8,0 /* ibcr0 */
mcr p15,0,r0,c14,c9,0 /* ibcr1 */
mcr p15,0,r0,c14,c4,0 /* dbcon */
/* Enable all debug functionality */
mov r0,#0x80000000
mcr p14,0,r0,c10,c0,0 // dcsr
mcr p14,0,r0,c10,c0,0 /* dcsr */
/* We are finished with Intel's memory controller initialisation */
/* ---------------------------------------------------------------- */
/* End lowlevel_init */
/* End lowlevel_init */
/* ---------------------------------------------------------------- */
endlowlevel_init:
mov pc, lr
mov pc, lr
/*
@********************************************************************************
@ DDR calibration
@
@
@ This function is used to calibrate DQS delay lines.
@ Monahans supports three ways to do it. One is software
@ Monahans supports three ways to do it. One is software
@ calibration. Two is hardware calibration. Three is hybrid
@ calibration.
@
@ -298,78 +294,78 @@ endlowlevel_init:
ddr_calibration:
@ Case 1: Write the correct delay value once
@ Configure DDR_SCAL Register
ldr r0, =DDR_SCAL @ DDR_SCAL
q ldr r1, =0xaf2f2f2f
str r1, [r0]
ldr r1, [r0]
@ Configure DDR_SCAL Register
ldr r0, =DDR_SCAL @ DDR_SCAL
q ldr r1, =0xaf2f2f2f
str r1, [r0]
ldr r1, [r0]
*/
/* @ Case 2: Software Calibration
@ Write test pattern to memory
ldr r5, =0x0faf0faf @ Data Pattern
ldr r4, =0xa0000000 @ DDR ram
str r5, [r4]
ldr r5, =0x0faf0faf @ Data Pattern
ldr r4, =0xa0000000 @ DDR ram
str r5, [r4]
mov r1, =0x0 @ delay count
mov r6, =0x0
mov r7, =0x0
mov r1, =0x0 @ delay count
mov r6, =0x0
mov r7, =0x0
ddr_loop1:
add r1, r1, =0x1
cmp r1, =0xf
ble end_loop
mov r3, r1
mov r0, r1, lsl #30
orr r3, r3, r0
mov r0, r1, lsl #22
orr r3, r3, r0
mov r0, r1, lsl #14
orr r3, r3, r0
orr r3, r3, =0x80000000
ldr r2, =DDR_SCAL
str r3, [r2]
add r1, r1, =0x1
cmp r1, =0xf
ble end_loop
mov r3, r1
mov r0, r1, lsl #30
orr r3, r3, r0
mov r0, r1, lsl #22
orr r3, r3, r0
mov r0, r1, lsl #14
orr r3, r3, r0
orr r3, r3, =0x80000000
ldr r2, =DDR_SCAL
str r3, [r2]
ldr r2, [r4]
cmp r2, r5
bne ddr_loop1
mov r6, r1
ldr r2, [r4]
cmp r2, r5
bne ddr_loop1
mov r6, r1
ddr_loop2:
add r1, r1, =0x1
cmp r1, =0xf
ble end_loop
mov r3, r1
mov r0, r1, lsl #30
orr r3, r3, r0
mov r0, r1, lsl #22
orr r3, r3, r0
mov r0, r1, lsl #14
orr r3, r3, r0
orr r3, r3, =0x80000000
ldr r2, =DDR_SCAL
str r3, [r2]
add r1, r1, =0x1
cmp r1, =0xf
ble end_loop
mov r3, r1
mov r0, r1, lsl #30
orr r3, r3, r0
mov r0, r1, lsl #22
orr r3, r3, r0
mov r0, r1, lsl #14
orr r3, r3, r0
orr r3, r3, =0x80000000
ldr r2, =DDR_SCAL
str r3, [r2]
ldr r2, [r4]
cmp r2, r5
be ddr_loop2
mov r7, r2
ldr r2, [r4]
cmp r2, r5
be ddr_loop2
mov r7, r2
add r3, r6, r7
lsr r3, r3, =0x1
mov r0, r1, lsl #30
orr r3, r3, r0
mov r0, r1, lsl #22
orr r3, r3, r0
mov r0, r1, lsl #14
orr r3, r3, r0
orr r3, r3, =0x80000000
ldr r2, =DDR_SCAL
add r3, r6, r7
lsr r3, r3, =0x1
mov r0, r1, lsl #30
orr r3, r3, r0
mov r0, r1, lsl #22
orr r3, r3, r0
mov r0, r1, lsl #14
orr r3, r3, r0
orr r3, r3, =0x80000000
ldr r2, =DDR_SCAL
end_loop:
@ Case 3: Hardware Calibratoin
ldr r0, =DDR_HCAL @ DDR_HCAL
ldr r1, =0x803ffc07 @ the offset is correct? -SC
str r1, [r0]
wait #5
ldr r1, [r0]
mov pc, lr
ldr r0, =DDR_HCAL @ DDR_HCAL
ldr r1, =0x803ffc07 @ the offset is correct? -SC
str r1, [r0]
wait #5
ldr r1, [r0]
mov pc, lr
*/

2
common/Makefile
View File

@ -37,7 +37,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o \
cmd_i2c.o cmd_ide.o cmd_immap.o cmd_itest.o cmd_jffs2.o \
cmd_load.o cmd_log.o \
cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \
cmd_nand.o cmd_nand_new.o cmd_net.o cmd_nvedit.o \
cmd_nand.o cmd_net.o cmd_nvedit.o \
cmd_pci.o cmd_pcmcia.o cmd_portio.o \
cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_universe.o \
cmd_usb.o cmd_vfd.o \

3
common/cmd_doc.c
View File

@ -22,8 +22,9 @@
#if (CONFIG_COMMANDS & CFG_CMD_DOC)
#include <linux/mtd/nftl.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
#include <linux/mtd/nand_ids.h>
#include <linux/mtd/doc2000.h>
#include <linux/mtd/nftl.h>

17
common/cmd_jffs2.c
View File

@ -91,7 +91,6 @@
#include <command.h>
#include <malloc.h>
#include <jffs2/jffs2.h>
#include <linux/mtd/nand.h>
#include <linux/list.h>
#include <linux/ctype.h>
@ -99,10 +98,14 @@
#include <cramfs/cramfs_fs.h>
#ifdef CONFIG_NEW_NAND_CODE
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#ifdef CFG_NAND_LEGACY
#include <linux/mtd/nand_legacy.h>
#else /* !CFG_NAND_LEGACY */
#include <linux/mtd/nand.h>
#include <nand.h>
#endif
#endif /* !CFG_NAND_LEGACY */
#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
/* enable/disable debugging messages */
#define DEBUG_JFFS
#undef DEBUG_JFFS
@ -467,7 +470,7 @@ static int part_del(struct mtd_device *dev, struct part_info *part)
}
}
#ifndef CONFIG_NEW_NAND_CODE
#ifdef CFG_NAND_LEGACY
jffs2_free_cache(part);
#endif
list_del(&part->link);
@ -496,7 +499,7 @@ static void part_delall(struct list_head *head)
list_for_each_safe(entry, n, head) {
part_tmp = list_entry(entry, struct part_info, link);
#ifndef CONFIG_NEW_NAND_CODE
#ifdef CFG_NAND_LEGACY
jffs2_free_cache(part_tmp);
#endif
list_del(entry);
@ -732,7 +735,7 @@ static int device_validate(u8 type, u8 num, u32 *size)
} else if (type == MTD_DEV_TYPE_NAND) {
#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND)
if (num < CFG_MAX_NAND_DEVICE) {
#ifdef CONFIG_NEW_NAND_CODE
#ifndef CFG_NAND_LEGACY
*size = nand_info[num].size;
#else
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];

1957
common/cmd_nand.c
View File

File diff suppressed because it is too large Load Diff

364
common/cmd_nand_new.c
View File

@ -1,364 +0,0 @@
#include <common.h>
#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined CONFIG_NEW_NAND_CODE
#include <command.h>
#include <watchdog.h>
#include <malloc.h>
#include <asm/byteorder.h>
#ifdef CONFIG_SHOW_BOOT_PROGRESS
# include <status_led.h>
# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
#else
# define SHOW_BOOT_PROGRESS(arg)
#endif
#include <jffs2/jffs2.h>
#include <nand.h>
extern nand_info_t nand_info[]; /* info for NAND chips */
static int nand_dump_oob(nand_info_t *nand, ulong off)
{
return 0;
}
static int nand_dump(nand_info_t *nand, ulong off)
{
int i;
u_char *buf, *p;
buf = malloc(nand->oobblock + nand->oobsize);
if (!buf) {
puts("No memory for page buffer\n");
return 1;
}
off &= ~(nand->oobblock - 1);
i = nand_read_raw(nand, buf, off, nand->oobblock, nand->oobsize);
if (i < 0) {
printf("Error (%d) reading page %08x\n", i, off);
free(buf);
return 1;
}
printf("Page %08x dump:\n", off);
i = nand->oobblock >> 4; p = buf;
while (i--) {
printf( "\t%02x %02x %02x %02x %02x %02x %02x %02x"
" %02x %02x %02x %02x %02x %02x %02x %02x\n",
p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],
p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15]);
p += 16;
}
puts("OOB:\n");
i = nand->oobsize >> 3;
while (i--) {
printf( "\t%02x %02x %02x %02x %02x %02x %02x %02x\n",
p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
p += 8;
}
free(buf);
return 0;
}
/* ------------------------------------------------------------------------- */
static void
arg_off_size(int argc, char *argv[], ulong *off, ulong *size, ulong totsize)
{
*off = 0;
*size = 0;
#if defined(CONFIG_JFFS2_NAND) && defined(CFG_JFFS_CUSTOM_PART)
if (argc >= 1 && strcmp(argv[0], "partition") == 0) {
int part_num;
struct part_info *part;
const char *partstr;
if (argc >= 2)
partstr = argv[1];
else
partstr = getenv("partition");
if (partstr)
part_num = (int)simple_strtoul(partstr, NULL, 10);
else
part_num = 0;
part = jffs2_part_info(part_num);
if (part == NULL) {
printf("\nInvalid partition %d\n", part_num);
return;
}
*size = part->size;
*off = (ulong)part->offset;
} else
#endif
{
if (argc >= 1)
*off = (ulong)simple_strtoul(argv[0], NULL, 16);
else
*off = 0;
if (argc >= 2)
*size = (ulong)simple_strtoul(argv[1], NULL, 16);
else
*size = totsize - *off;
}
}
int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
int i, dev, ret;
ulong addr, off, size;
char *cmd, *s;
nand_info_t *nand;
/* at least two arguments please */
if (argc < 2)
goto usage;
cmd = argv[1];
if (strcmp(cmd, "info") == 0) {
putc('\n');
for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) {
if (nand_info[i].name)
printf("Device %d: %s\n", i, nand_info[i].name);
}
return 0;
}
if (strcmp(cmd, "device") == 0) {
if (argc < 3) {
if ((nand_curr_device < 0) ||
(nand_curr_device >= CFG_MAX_NAND_DEVICE))
puts("\nno devices available\n");
else
printf("\nDevice %d: %s\n", nand_curr_device,
nand_info[nand_curr_device].name);
return 0;
}
dev = (int)simple_strtoul(argv[2], NULL, 10);
if (dev < 0 || dev >= CFG_MAX_NAND_DEVICE || !nand_info[dev].name) {
puts("No such device\n");
return 1;
}
printf("Device %d: %s", dev, nand_info[dev].name);
puts("... is now current device\n");
nand_curr_device = dev;
return 0;
}
if (strcmp(cmd, "bad") != 0 && strcmp(cmd, "erase") != 0 &&
strncmp(cmd, "dump", 4) != 0 &&
strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0)
goto usage;
/* the following commands operate on the current device */
if (nand_curr_device < 0 || nand_curr_device >= CFG_MAX_NAND_DEVICE ||
!nand_info[nand_curr_device].name) {
puts("\nno devices available\n");
return 1;
}
nand = &nand_info[nand_curr_device];
if (strcmp(cmd, "bad") == 0) {
printf("\nDevice %d bad blocks:\n", nand_curr_device);
for (off = 0; off < nand->size; off += nand->erasesize)
if (nand_block_isbad(nand, off))
printf(" %08x\n", off);
return 0;
}
if (strcmp(cmd, "erase") == 0) {
arg_off_size(argc - 2, argv + 2, &off, &size, nand->size);
if (off == 0 && size == 0)
return 1;
printf("\nNAND erase: device %d offset 0x%x, size 0x%x ",
nand_curr_device, off, size);
ret = nand_erase(nand, off, size);
printf("%s\n", ret ? "ERROR" : "OK");
return ret == 0 ? 0 : 1;
}
if (strncmp(cmd, "dump", 4) == 0) {
if (argc < 3)
goto usage;
s = strchr(cmd, '.');
off = (int)simple_strtoul(argv[2], NULL, 16);
if (s != NULL && strcmp(s, ".oob") == 0)
ret = nand_dump_oob(nand, off);
else
ret = nand_dump(nand, off);
return ret == 0 ? 1 : 0;
}
/* read write */
if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) {
if (argc < 4)
goto usage;
/*
s = strchr(cmd, '.');
clean = CLEAN_NONE;
if (s != NULL) {
if (strcmp(s, ".jffs2") == 0 || strcmp(s, ".e") == 0
|| strcmp(s, ".i"))
clean = CLEAN_JFFS2;
}
*/
addr = (ulong)simple_strtoul(argv[2], NULL, 16);
arg_off_size(argc - 3, argv + 3, &off, &size, nand->size);
if (off == 0 && size == 0)
return 1;
i = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */
printf("\nNAND %s: device %d offset %u, size %u ... ",
i ? "read" : "write", nand_curr_device, off, size);
if (i)
ret = nand_read(nand, off, &size, (u_char *)addr);
else
ret = nand_write(nand, off, &size, (u_char *)addr);
printf(" %d bytes %s: %s\n", size,
i ? "read" : "written", ret ? "ERROR" : "OK");
return ret == 0 ? 0 : 1;
}
usage:
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
U_BOOT_CMD(nand, 5, 1, do_nand,
"nand - NAND sub-system\n",
"info - show available NAND devices\n"
"nand device [dev] - show or set current device\n"
"nand read[.jffs2] - addr off size\n"
"nand write[.jffs2] - addr off size - read/write `size' bytes starting\n"
" at offset `off' to/from memory address `addr'\n"
"nand erase [clean] [off size] - erase `size' bytes from\n"
" offset `off' (entire device if not specified)\n"
"nand bad - show bad blocks\n"
"nand dump[.oob] off - dump page\n"
"nand scrub - really clean NAND erasing bad blocks (UNSAFE)\n"
"nand markbad off - mark bad block at offset (UNSAFE)\n"
"nand biterr off - make a bit error at offset (UNSAFE)\n");
int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
char *boot_device = NULL;
char *ep;
int dev;
int r;
ulong addr, cnt, offset = 0;
image_header_t *hdr;
nand_info_t *nand;
switch (argc) {
case 1:
addr = CFG_LOAD_ADDR;
boot_device = getenv("bootdevice");
break;
case 2:
addr = simple_strtoul(argv[1], NULL, 16);
boot_device = getenv("bootdevice");
break;
case 3:
addr = simple_strtoul(argv[1], NULL, 16);
boot_device = argv[2];
break;
case 4:
addr = simple_strtoul(argv[1], NULL, 16);
boot_device = argv[2];
offset = simple_strtoul(argv[3], NULL, 16);
break;
default:
printf("Usage:\n%s\n", cmdtp->usage);
SHOW_BOOT_PROGRESS(-1);
return 1;
}
if (!boot_device) {
puts("\n** No boot device **\n");
SHOW_BOOT_PROGRESS(-1);
return 1;
}
dev = simple_strtoul(boot_device, &ep, 16);
if (dev < 0 || dev >= CFG_MAX_NAND_DEVICE || !nand_info[dev].name) {
printf("\n** Device %d not available\n", dev);
SHOW_BOOT_PROGRESS(-1);
return 1;
}
nand = &nand_info[dev];
printf("\nLoading from device %d: %s (offset 0x%lx)\n",
dev, nand->name, offset);
cnt = nand->oobblock;
r = nand_read(nand, offset, &cnt, (u_char *) addr);
if (r) {
printf("** Read error on %d\n", dev);
SHOW_BOOT_PROGRESS(-1);
return 1;
}
hdr = (image_header_t *) addr;
if (ntohl(hdr->ih_magic) != IH_MAGIC) {
printf("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic);
SHOW_BOOT_PROGRESS(-1);
return 1;
}
print_image_hdr(hdr);
cnt = (ntohl(hdr->ih_size) + sizeof (image_header_t));
r = nand_read(nand, offset, &cnt, (u_char *) addr);
if (r) {
printf("** Read error on %d\n", dev);
SHOW_BOOT_PROGRESS(-1);
return 1;
}
/* Loading ok, update default load address */
load_addr = addr;
/* Check if we should attempt an auto-start */
if (((ep = getenv("autostart")) != NULL) && (strcmp(ep, "yes") == 0)) {
char *local_args[2];
extern int do_bootm(cmd_tbl_t *, int, int, char *[]);
local_args[0] = argv[0];
local_args[1] = NULL;
printf("Automatic boot of image at addr 0x%08lx ...\n", addr);
do_bootm(cmdtp, 0, 1, local_args);
return 1;
}
return 0;
}
U_BOOT_CMD(nboot, 4, 1, do_nandboot,
"nboot - boot from NAND device\n", "loadAddr dev\n");
#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */

49
common/env_nand.c
View File

@ -36,7 +36,7 @@
#include <command.h>
#include <environment.h>
#include <linux/stddef.h>
#include <linux/mtd/nand.h>
#include <nand.h>
#if ((CONFIG_COMMANDS&(CFG_CMD_ENV|CFG_CMD_NAND)) == (CFG_CMD_ENV|CFG_CMD_NAND))
#define CMD_SAVEENV
@ -55,16 +55,12 @@
#error CONFIG_INFERNO not supported yet
#endif
/* references to names in cmd_nand.c */
#define NANDRW_READ 0x01
#define NANDRW_WRITE 0x00
#define NANDRW_JFFS2 0x02
extern struct nand_chip nand_dev_desc[];
int nand_rw (struct nand_chip* nand, int cmd,
int nand_legacy_rw (struct nand_chip* nand, int cmd,
size_t start, size_t len,
size_t * retlen, u_char * buf);
int nand_erase(struct nand_chip* nand, size_t ofs,
size_t len, int clean);
/* info for NAND chips, defined in drivers/nand/nand.c */
extern nand_info_t nand_info[];
/* references to names in env_common.c */
extern uchar default_environment[];
@ -110,34 +106,43 @@ int env_init(void)
}
#ifdef CMD_SAVEENV
/*
* The legacy NAND code saved the environment in the first NAND device i.e.,
* nand_dev_desc + 0. This is also the behaviour using the new NAND code.
*/
int saveenv(void)
{
int total, ret = 0;
puts ("Erasing Nand...");
if (nand_erase(nand_dev_desc + 0, CFG_ENV_OFFSET, CFG_ENV_SIZE, 0))
return 1;
puts ("Writing to Nand... ");
ret = nand_rw(nand_dev_desc + 0,
NANDRW_WRITE | NANDRW_JFFS2, CFG_ENV_OFFSET, CFG_ENV_SIZE,
&total, (u_char*)env_ptr);
if (ret || total != CFG_ENV_SIZE)
puts ("Erasing Nand...");
if (nand_erase(&nand_info[0], CFG_NEW_OFFSET, CFG_ENV_SIZE))
return 1;
puts ("done\n");
return ret;
puts ("Writing to Nand... ");
total = CFG_ENV_SIZE;
ret = nand_write(&nand_info[0], CFG_ENV_OFFSET, &total,
(u_char*) env_ptr);
if (ret || total != CFG_ENV_SIZE)
return 1;
puts ("done\n");
return ret;
}
#endif /* CMD_SAVEENV */
/*
* The legacy NAND code saved the environment in the first NAND device i.e.,
* nand_dev_desc + 0. This is also the behaviour using the new NAND code.
*/
void env_relocate_spec (void)
{
#if !defined(ENV_IS_EMBEDDED)
int ret, total;
ret = nand_rw(nand_dev_desc + 0,
NANDRW_READ | NANDRW_JFFS2, CFG_ENV_OFFSET, CFG_ENV_SIZE,
&total, (u_char*)env_ptr);
total = CFG_ENV_SIZE;
ret = nand_read(&nand_info[0], CFG_ENV_OFFSET, &total,
(u_char*) env_ptr);
if (ret || total != CFG_ENV_SIZE)
return use_default();

3
cpu/mpc5xxx/fec.c
View File

@ -880,8 +880,9 @@ int mpc5xxx_fec_initialize(bd_t * bis)
fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
#if defined(CONFIG_CANMB) || defined(CONFIG_HMI1001) || \
defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \
defined(CONFIG_MCC200) || defined(CONFIG_O2DNT) || \
defined(CONFIG_PM520) || defined(CONFIG_TOP5200) || \
defined(CONFIG_TQM5200) || defined(CONFIG_O2DNT)
defined(CONFIG_TQM5200)
# ifndef CONFIG_FEC_10MBIT
fec->xcv_type = MII100;
# else

1
cpu/pxa/cpu.c
View File

@ -162,4 +162,3 @@ void set_GPIO_mode(int gpio_mode)
GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2));
}
#endif /* CONFIG_CPU_MONAHANS */

86
cpu/pxa/start.S
View File

@ -6,8 +6,8 @@
* Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
* Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
* Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
* Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
* Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
*
* See file CREDITS for list of people who contributed to this
* project.
@ -117,13 +117,13 @@ reset:
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */
beq stack_setup
cmp r0, r1 /* don't reloc during debug */
beq stack_setup
ldr r2, _armboot_start
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
@ -135,19 +135,19 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
mov r2, #0x00000000 /* clear */
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
mov r2, #0x00000000 /* clear */
clbss_l:str r2, [r0] /* clear loop... */
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
ble clbss_l
@ -173,8 +173,8 @@ _start_armboot: .word start_armboot
#undef OWER
#undef OIER
#endif
/* Interrupt-Controller base address */
/* Interrupt-Controller base address */
IC_BASE: .word 0x40d00000
#define ICMR 0x04
@ -189,7 +189,7 @@ OSTIMER_BASE: .word 0x40a00000
#define OWER 0x18
#define OIER 0x1C
/* Clock Manager Registers */
/* Clock Manager Registers */
#ifdef CFG_CPUSPEED
CC_BASE: .word 0x41300000
#define CCCR 0x00
@ -197,7 +197,6 @@ cpuspeed: .word CFG_CPUSPEED
#else
#error "You have to define CFG_CPUSPEED!!"
#endif
/* takes care the CP15 update has taken place */
.macro CPWAIT reg
@ -206,40 +205,36 @@ cpuspeed: .word CFG_CPUSPEED
sub pc,pc,#4
.endm
cpu_init_crit:
/* mask all IRQs */
#ifndef CONFIG_CPU_MONAHANS
ldr r0, IC_BASE
mov r1, #0x00
str r1, [r0, #ICMR]
#else
/* Step 1 - Enable CP6 permission */
mrc p15, 0, r1, c15, c1, 0 @ read CPAR
orr r1, r1, #0x40
mcr p15, 0, r1, c15, c1, 0
CPWAIT r1
mrc p15, 0, r1, c15, c1, 0 @ read CPAR
orr r1, r1, #0x40
mcr p15, 0, r1, c15, c1, 0
CPWAIT r1
/* Step 2 - Mask ICMR & ICMR2 */
mov r1, #0
mcr p6, 0, r1, c1, c0, 0 @ ICMR
mcr p6, 0, r1, c7, c0, 0 @ ICMR2
/* Step 2 - Mask ICMR & ICMR2 */
mov r1, #0
mcr p6, 0, r1, c1, c0, 0 @ ICMR
mcr p6, 0, r1, c7, c0, 0 @ ICMR2
/* turn off all clocks but the ones we will definitly require */
ldr r1, =CKENA
ldr r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC)
str r2, [r1]
ldr r1, =CKENB
ldr r2, =(CKENB_6_IRQ)
str r2, [r1]
ldr r1, =CKENA
ldr r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC)
str r2, [r1]
ldr r1, =CKENB
ldr r2, =(CKENB_6_IRQ)
str r2, [r1]
#endif
#ifndef CONFIG_CPU_MONAHANS
#ifdef CFG_CPUSPEED
/* set clock speed tbd@mk: required for monahans? */
ldr r0, CC_BASE
ldr r1, cpuspeed
@ -248,10 +243,9 @@ cpu_init_crit:
mcr p14, 0, r0, c6, c0, 0
setspeed_done:
#endif /* CFG_CPUSPEED */
#endif /* CONFIG_CPU_MONAHANS */
/*
* before relocating, we have to setup RAM timing
@ -263,7 +257,7 @@ setspeed_done:
mov lr, ip
/* Memory interfaces are working. Disable MMU and enable I-cache. */
/* mk: hmm, this is not in the monahans docs, leave it now but
/* mk: hmm, this is not in the monahans docs, leave it now but
* check here if it doesn't work :-) */
ldr r0, =0x2001 /* enable access to all coproc. */
@ -330,7 +324,7 @@ setspeed_done:
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
@ -457,17 +451,17 @@ fiq:
#endif
/****************************************************************************/
/* */
/* */
/* Reset function: the PXA250 doesn't have a reset function, so we have to */
/* perform a watchdog timeout for a soft reset. */
/* */
/* perform a watchdog timeout for a soft reset. */
/* */
/****************************************************************************/
.align 5
.globl reset_cpu
/* FIXME: this code is PXA250 specific. How is this handled on */
/* other XScale processors? */
/* FIXME: this code is PXA250 specific. How is this handled on */
/* other XScale processors? */
reset_cpu:
@ -475,13 +469,13 @@ reset_cpu:
ldr r0, OSTIMER_BASE
ldr r1, [r0, #OWER]
orr r1, r1, #0x0001 /* bit0: WME */
orr r1, r1, #0x0001 /* bit0: WME */
str r1, [r0, #OWER]
/* OS timer does only wrap every 1165 seconds, so we have to set */
/* the match register as well. */
/* the match register as well. */
ldr r1, [r0, #OSCR] /* read OS timer */
ldr r1, [r0, #OSCR] /* read OS timer */
add r1, r1, #0x800 /* let OSMR3 match after */
add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */
str r1, [r0, #OSMR3]

34
doc/README.nand
View File

@ -1,5 +1,9 @@
NAND FLASH commands and notes
See NOTE below!!!
# (C) Copyright 2003
# Dave Ellis, SIXNET, dge@sixnetio.com
#
@ -173,3 +177,33 @@ More Definitions:
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
NOTE:
=====
We now use a complete rewrite of the NAND code based on what is in
2.6.12 Linux kernel.
The old NAND handling code has been re-factored and is now confined
to only board-specific files and - unfortunately - to the DoC code
(see below). A new configuration variable has been introduced:
CFG_NAND_LEGACY, which has to be defined in the board config file if
that board uses legacy code. If CFG_NAND_LEGACY is defined, the board
specific config.mk file should also have "BOARDLIBS =
drivers/nand_legacy/libnand_legacy.a". For boards using the new NAND
approach (PPChameleon and netstar at the moment) no variable is
necessary, but the config.mk should have "BOARDLIBS =
drivers/nand/libnand.a".
The necessary changes have been made to all affected boards, and no
build breakage has been introduced, except for NETTA and NETTA_ISDN
targets from MAKEALL. This is due to the fact that these two boards
use JFFS, which has been adopted to use the new NAND, and at the same
time use NAND in legacy mode. The breakage will disappear when the
board-specific code is changed to the new NAND.
As mentioned above, the legacy code is still used by the DoC subsystem.
The consequence of this is that the legacy NAND can't be removed from
the tree until the DoC is ported to use the new NAND support (or boards
with DoC will break).

226
drivers/cfi_flash.c
View File

@ -104,12 +104,15 @@
#define AMD_CMD_ERASE_SECTOR 0x30
#define AMD_CMD_UNLOCK_START 0xAA
#define AMD_CMD_UNLOCK_ACK 0x55
#define AMD_CMD_WRITE_TO_BUFFER 0x25
#define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29
#define AMD_STATUS_TOGGLE 0x40
#define AMD_STATUS_ERROR 0x20
#define AMD_ADDR_ERASE_START 0x555
#define AMD_ADDR_START 0x555
#define AMD_ADDR_ACK 0x2AA
#define AMD_ADDR_ERASE_START ((info->portwidth == FLASH_CFI_8BIT) ? 0xAAA : 0x555)
#define AMD_ADDR_START ((info->portwidth == FLASH_CFI_8BIT) ? 0xAAA : 0x555)
#define AMD_ADDR_ACK ((info->portwidth == FLASH_CFI_8BIT) ? 0x555 : 0x2AA)
#define FLASH_OFFSET_CFI 0x55
#define FLASH_OFFSET_CFI_RESP 0x10
@ -175,6 +178,13 @@ static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* FLASH chips info */
#endif
/*
* Check if chip width is defined. If not, start detecting with 8bit.
*/
#ifndef CFG_FLASH_CFI_WIDTH
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
#endif
/*-----------------------------------------------------------------------
* Functions
@ -190,10 +200,10 @@ static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, u
static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
static int flash_detect_cfi (flash_info_t * info);
ulong flash_get_size (ulong base, int banknum);
static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
ulong tout, char *prompt);
ulong flash_get_size (ulong base, int banknum);
#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
static flash_info_t *flash_get_info(ulong base);
#endif
@ -328,6 +338,7 @@ ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
return retval;
}
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
@ -345,6 +356,24 @@ unsigned long flash_init (void)
i, flash_info[i].size, flash_info[i].size << 20);
#endif /* CFG_FLASH_QUIET_TEST */
}
#ifdef CFG_FLASH_PROTECTION
else {
char *s = getenv("unlock");
if (((s = getenv("unlock")) != NULL) && (strcmp(s, "yes") == 0)) {
/*
* Only the U-Boot image and it's environment is protected,
* all other sectors are unprotected (unlocked) if flash
* hardware protection is used (CFG_FLASH_PROTECTION) and
* the environment variable "unlock" is set to "yes".
*/
flash_protect (FLAG_PROTECT_CLEAR,
flash_info[i].start[0],
flash_info[i].start[0] + flash_info[i].size - 1,
&flash_info[i]);
}
}
#endif /* CFG_FLASH_PROTECTION */
}
/* Monitor protection ON by default */
@ -565,7 +594,22 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
buffered_size = (info->portwidth / info->chipwidth);
buffered_size *= info->buffer_size;
while (cnt >= info->portwidth) {
i = buffered_size > cnt ? cnt : buffered_size;
/* prohibit buffer write when buffer_size is 1 */
if (info->buffer_size == 1) {
cword.l = 0;
for (i = 0; i < info->portwidth; i++)
flash_add_byte (info, &cword, *src++);
if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
return rc;
wp += info->portwidth;
cnt -= info->portwidth;
continue;
}
/* write buffer until next buffered_size aligned boundary */
i = buffered_size - (wp % buffered_size);
if (i > cnt)
i = cnt;
if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
return rc;
i -= i & (info->portwidth - 1);
@ -705,7 +749,7 @@ static int flash_status_check (flash_info_t * info, flash_sect_t sector,
/* Wait for command completion */
start = get_timer (0);
while (flash_is_busy (info, sector)) {
if (get_timer (start) > info->erase_blk_tout * CFG_HZ) {
if (get_timer (start) > tout) {
printf ("Flash %s timeout at address %lx data %lx\n",
prompt, info->start[sector],
flash_read_long (info, sector, 0));
@ -729,7 +773,7 @@ static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
switch (info->vendor) {
case CFI_CMDSET_INTEL_EXTENDED:
case CFI_CMDSET_INTEL_STANDARD:
if ((retcode != ERR_OK)
if ((retcode == ERR_OK)
&& !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
retcode = ERR_INVAL;
printf ("Flash %s error at address %lx\n", prompt,
@ -985,7 +1029,7 @@ static int flash_detect_cfi (flash_info_t * info)
{
debug ("flash detect cfi\n");
for (info->portwidth = FLASH_CFI_8BIT;
for (info->portwidth = CFG_FLASH_CFI_WIDTH;
info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
for (info->chipwidth = FLASH_CFI_BY8;
info->chipwidth <= info->portwidth;
@ -1106,8 +1150,9 @@ ulong flash_get_size (ulong base, int banknum)
info->erase_blk_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT)));
tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT);
info->buffer_write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)));
tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT);
info->write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT))) / 1000;
tmp = (1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT)) *
(1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT));
info->write_tout = tmp / 1000 + (tmp % 1000 ? 1 : 0); /* round up when converting to ms */
info->flash_id = FLASH_MAN_CFI;
if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) {
info->portwidth >>= 1; /* XXX - Need to test on x8/x16 in parallel. */
@ -1118,13 +1163,26 @@ ulong flash_get_size (ulong base, int banknum)
return (info->size);
}
/* loop through the sectors from the highest address
* when the passed address is greater or equal to the sector address
* we have a match
*/
static flash_sect_t find_sector (flash_info_t * info, ulong addr)
{
flash_sect_t sector;
for (sector = info->sector_count - 1; sector >= 0; sector--) {
if (addr >= info->start[sector])
break;
}
return sector;
}
/*-----------------------------------------------------------------------
*/
static int flash_write_cfiword (flash_info_t * info, ulong dest,
cfiword_t cword)
{
cfiptr_t ctladdr;
cfiptr_t cptr;
int flag;
@ -1188,26 +1246,12 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest,
if (flag)
enable_interrupts ();
return flash_full_status_check (info, 0, info->write_tout, "write");
return flash_full_status_check (info, find_sector (info, dest),
info->write_tout, "write");
}
#ifdef CFG_FLASH_USE_BUFFER_WRITE
/* loop through the sectors from the highest address
* when the passed address is greater or equal to the sector address
* we have a match
*/
static flash_sect_t find_sector (flash_info_t * info, ulong addr)
{
flash_sect_t sector;
for (sector = info->sector_count - 1; sector >= 0; sector--) {
if (addr >= info->start[sector])
break;
}
return sector;
}
static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
int len)
{
@ -1216,66 +1260,106 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
int retcode;
volatile cfiptr_t src;
volatile cfiptr_t dst;
/* buffered writes in the AMD chip set is not supported yet */
if((info->vendor == CFI_CMDSET_AMD_STANDARD) ||
(info->vendor == CFI_CMDSET_AMD_EXTENDED))
return ERR_INVAL;
src.cp = cp;
dst.cp = (uchar *) dest;
sector = find_sector (info, dest);
flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
if ((retcode =
flash_status_check (info, sector, info->buffer_write_tout,
"write to buffer")) == ERR_OK) {
/* reduce the number of loops by the width of the port */
switch (info->portwidth) {
case FLASH_CFI_8BIT:
cnt = len;
break;
case FLASH_CFI_16BIT:
cnt = len >> 1;
break;
case FLASH_CFI_32BIT:
cnt = len >> 2;
break;
case FLASH_CFI_64BIT:
cnt = len >> 3;
break;
default:
return ERR_INVAL;
break;
}
flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
while (cnt-- > 0) {
switch (info->vendor) {
case CFI_CMDSET_INTEL_STANDARD:
case CFI_CMDSET_INTEL_EXTENDED:
src.cp = cp;
dst.cp = (uchar *) dest;
sector = find_sector (info, dest);
flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
if ((retcode = flash_status_check (info, sector, info->buffer_write_tout,
"write to buffer")) == ERR_OK) {
/* reduce the number of loops by the width of the port */
switch (info->portwidth) {
case FLASH_CFI_8BIT:
*dst.cp++ = *src.cp++;
cnt = len;
break;
case FLASH_CFI_16BIT:
*dst.wp++ = *src.wp++;
cnt = len >> 1;
break;
case FLASH_CFI_32BIT:
*dst.lp++ = *src.lp++;
cnt = len >> 2;
break;
case FLASH_CFI_64BIT:
*dst.llp++ = *src.llp++;
cnt = len >> 3;
break;
default:
return ERR_INVAL;
break;
}
flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
while (cnt-- > 0) {
switch (info->portwidth) {
case FLASH_CFI_8BIT:
*dst.cp++ = *src.cp++;
break;
case FLASH_CFI_16BIT:
*dst.wp++ = *src.wp++;
break;
case FLASH_CFI_32BIT:
*dst.lp++ = *src.lp++;
break;
case FLASH_CFI_64BIT:
*dst.llp++ = *src.llp++;
break;
default:
return ERR_INVAL;
break;
}
}
flash_write_cmd (info, sector, 0,
FLASH_CMD_WRITE_BUFFER_CONFIRM);
retcode = flash_full_status_check (info, sector,
info->buffer_write_tout,
"buffer write");
}
flash_write_cmd (info, sector, 0,
FLASH_CMD_WRITE_BUFFER_CONFIRM);
retcode =
flash_full_status_check (info, sector,
info->buffer_write_tout,
"buffer write");
return retcode;
case CFI_CMDSET_AMD_STANDARD:
case CFI_CMDSET_AMD_EXTENDED:
src.cp = cp;
dst.cp = (uchar *) dest;
sector = find_sector (info, dest);
flash_unlock_seq(info,0);
flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_TO_BUFFER);
switch (info->portwidth) {
case FLASH_CFI_8BIT:
cnt = len;
flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
while (cnt-- > 0) *dst.cp++ = *src.cp++;
break;
case FLASH_CFI_16BIT:
cnt = len >> 1;
flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
while (cnt-- > 0) *dst.wp++ = *src.wp++;
break;
case FLASH_CFI_32BIT:
cnt = len >> 2;
flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
while (cnt-- > 0) *dst.lp++ = *src.lp++;
break;
case FLASH_CFI_64BIT:
cnt = len >> 3;
flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
while (cnt-- > 0) *dst.llp++ = *src.llp++;
break;
default:
return ERR_INVAL;
}
flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM);
retcode = flash_full_status_check (info, sector, info->buffer_write_tout,
"buffer write");
return retcode;
default:
debug ("Unknown Command Set\n");
return ERR_INVAL;
}
flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
return retcode;
}
#endif /* CFG_FLASH_USE_BUFFER_WRITE */
#endif /* CFG_FLASH_CFI */

436
drivers/i8042.c
View File

@ -12,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -33,7 +33,7 @@
extern u8 gt_cpcidvi_in8(u32 offset);
extern void gt_cpcidvi_out8(u32 offset, u8 data);
#define in8(a) gt_cpcidvi_in8(a)
#define in8(a) gt_cpcidvi_in8(a)
#define out8(a, b) gt_cpcidvi_out8(a,b)
#endif
@ -49,10 +49,10 @@ static int cursor_state = 0;
/* locals */
static int kbd_input = -1; /* no input yet */
static int kbd_mapping = KBD_US; /* default US keyboard */
static int kbd_flags = NORMAL; /* after reset */
static int kbd_state = 0; /* unshift code */
static int kbd_input = -1; /* no input yet */
static int kbd_mapping = KBD_US; /* default US keyboard */
static int kbd_flags = NORMAL; /* after reset */
static int kbd_state = 0; /* unshift code */
static void kbd_conv_char (unsigned char scan_code);
static void kbd_led_set (void);
@ -68,230 +68,230 @@ static int kbd_reset (void);
static unsigned char kbd_fct_map [144] =
{ /* kbd_fct_map table for scan code */
0, AS, AS, AS, AS, AS, AS, AS, /* scan 0- 7 */
AS, AS, AS, AS, AS, AS, AS, AS, /* scan 8- F */
AS, AS, AS, AS, AS, AS, AS, AS, /* scan 10-17 */
AS, AS, AS, AS, AS, CN, AS, AS, /* scan 18-1F */
AS, AS, AS, AS, AS, AS, AS, AS, /* scan 20-27 */
AS, AS, SH, AS, AS, AS, AS, AS, /* scan 28-2F */
AS, AS, AS, AS, AS, AS, SH, AS, /* scan 30-37 */
AS, AS, CP, 0, 0, 0, 0, 0, /* scan 38-3F */
0, 0, 0, 0, 0, NM, ST, ES, /* scan 40-47 */
ES, ES, ES, ES, ES, ES, ES, ES, /* scan 48-4F */
ES, ES, ES, ES, 0, 0, AS, 0, /* scan 50-57 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
AS, 0, 0, AS, 0, 0, AS, 0, /* scan 70-77 */
0, AS, 0, 0, 0, AS, 0, 0, /* scan 78-7F */
AS, CN, AS, AS, AK, ST, EX, EX, /* enhanced */
AS, EX, EX, AS, EX, AS, EX, EX /* enhanced */
0, AS, AS, AS, AS, AS, AS, AS, /* scan 0- 7 */
AS, AS, AS, AS, AS, AS, AS, AS, /* scan 8- F */
AS, AS, AS, AS, AS, AS, AS, AS, /* scan 10-17 */
AS, AS, AS, AS, AS, CN, AS, AS, /* scan 18-1F */
AS, AS, AS, AS, AS, AS, AS, AS, /* scan 20-27 */
AS, AS, SH, AS, AS, AS, AS, AS, /* scan 28-2F */
AS, AS, AS, AS, AS, AS, SH, AS, /* scan 30-37 */
AS, AS, CP, 0, 0, 0, 0, 0, /* scan 38-3F */
0, 0, 0, 0, 0, NM, ST, ES, /* scan 40-47 */
ES, ES, ES, ES, ES, ES, ES, ES, /* scan 48-4F */
ES, ES, ES, ES, 0, 0, AS, 0, /* scan 50-57 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
AS, 0, 0, AS, 0, 0, AS, 0, /* scan 70-77 */
0, AS, 0, 0, 0, AS, 0, 0, /* scan 78-7F */
AS, CN, AS, AS, AK, ST, EX, EX, /* enhanced */
AS, EX, EX, AS, EX, AS, EX, EX /* enhanced */
};
static unsigned char kbd_key_map [2][5][144] =
{
{ /* US keyboard */
{ /* unshift code */
0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */
'7', '8', '9', '0', '-', '=', 0x08, '\t', /* scan 8- F */
'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', /* scan 10-17 */
'o', 'p', '[', ']', '\r', CN, 'a', 's', /* scan 18-1F */
'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* scan 20-27 */
'\'', '`', SH, '\\', 'z', 'x', 'c', 'v', /* scan 28-2F */
'b', 'n', 'm', ',', '.', '/', SH, '*', /* scan 30-37 */
' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */
'8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
'2', '3', '0', '.', 0, 0, 0, 0, /* scan 50-57 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
'\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */
'7', '8', '9', '0', '-', '=', 0x08, '\t', /* scan 8- F */
'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', /* scan 10-17 */
'o', 'p', '[', ']', '\r', CN, 'a', 's', /* scan 18-1F */
'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* scan 20-27 */
'\'', '`', SH, '\\', 'z', 'x', 'c', 'v', /* scan 28-2F */
'b', 'n', 'm', ',', '.', '/', SH, '*', /* scan 30-37 */
' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */
'8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
'2', '3', '0', '.', 0, 0, 0, 0, /* scan 50-57 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
'\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
},
{ /* shift code */
0, 0x1b, '!', '@', '#', '$', '%', '^', /* scan 0- 7 */
'&', '*', '(', ')', '_', '+', 0x08, '\t', /* scan 8- F */
'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', /* scan 10-17 */
'O', 'P', '{', '}', '\r', CN, 'A', 'S', /* scan 18-1F */
'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', /* scan 20-27 */
'"', '~', SH, '|', 'Z', 'X', 'C', 'V', /* scan 28-2F */
'B', 'N', 'M', '<', '>', '?', SH, '*', /* scan 30-37 */
' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */
'8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
'2', '3', '0', '.', 0, 0, 0, 0, /* scan 50-57 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
'\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
0, 0x1b, '!', '@', '#', '$', '%', '^', /* scan 0- 7 */
'&', '*', '(', ')', '_', '+', 0x08, '\t', /* scan 8- F */
'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', /* scan 10-17 */
'O', 'P', '{', '}', '\r', CN, 'A', 'S', /* scan 18-1F */
'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', /* scan 20-27 */
'"', '~', SH, '|', 'Z', 'X', 'C', 'V', /* scan 28-2F */
'B', 'N', 'M', '<', '>', '?', SH, '*', /* scan 30-37 */
' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */
'8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
'2', '3', '0', '.', 0, 0, 0, 0, /* scan 50-57 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
'\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
},
{ /* control code */
0xff, 0x1b, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, /* scan 0- 7 */
0x1e, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff, '\t', /* scan 8- F */
0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09, /* scan 10-17 */
0x0f, 0x10, 0x1b, 0x1d, '\r', CN, 0x01, 0x13, /* scan 18-1F */
0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0c, 0xff, /* scan 20-27 */
0xff, 0x1c, SH, 0xff, 0x1a, 0x18, 0x03, 0x16, /* scan 28-2F */
0x02, 0x0e, 0x0d, 0xff, 0xff, 0xff, SH, 0xff, /* scan 30-37 */
0xff, 0xff, CP, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */
0xff, 0xff, 0xff, 0xff, 0xff, NM, ST, 0xff, /* scan 40-47 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */
'\r', CN, '/', '*', ' ', ST, 0xff, 0xff, /* extended */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */
0xff, 0x1b, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, /* scan 0- 7 */
0x1e, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff, '\t', /* scan 8- F */
0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09, /* scan 10-17 */
0x0f, 0x10, 0x1b, 0x1d, '\r', CN, 0x01, 0x13, /* scan 18-1F */
0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0c, 0xff, /* scan 20-27 */
0xff, 0x1c, SH, 0xff, 0x1a, 0x18, 0x03, 0x16, /* scan 28-2F */
0x02, 0x0e, 0x0d, 0xff, 0xff, 0xff, SH, 0xff, /* scan 30-37 */
0xff, 0xff, CP, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */
0xff, 0xff, 0xff, 0xff, 0xff, NM, ST, 0xff, /* scan 40-47 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */
'\r', CN, '/', '*', ' ', ST, 0xff, 0xff, /* extended */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */
},
{ /* non numeric code */
0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */
'7', '8', '9', '0', '-', '=', 0x08, '\t', /* scan 8- F */
'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', /* scan 10-17 */
'o', 'p', '[', ']', '\r', CN, 'a', 's', /* scan 18-1F */
'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* scan 20-27 */
'\'', '`', SH, '\\', 'z', 'x', 'c', 'v', /* scan 28-2F */
'b', 'n', 'm', ',', '.', '/', SH, '*', /* scan 30-37 */
' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
0, 0, 0, 0, 0, NM, ST, 'w', /* scan 40-47 */
'x', 'y', 'l', 't', 'u', 'v', 'm', 'q', /* scan 48-4F */
'r', 's', 'p', 'n', 0, 0, 0, 0, /* scan 50-57 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
'\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */
'7', '8', '9', '0', '-', '=', 0x08, '\t', /* scan 8- F */
'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', /* scan 10-17 */
'o', 'p', '[', ']', '\r', CN, 'a', 's', /* scan 18-1F */
'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* scan 20-27 */
'\'', '`', SH, '\\', 'z', 'x', 'c', 'v', /* scan 28-2F */
'b', 'n', 'm', ',', '.', '/', SH, '*', /* scan 30-37 */
' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
0, 0, 0, 0, 0, NM, ST, 'w', /* scan 40-47 */
'x', 'y', 'l', 't', 'u', 'v', 'm', 'q', /* scan 48-4F */
'r', 's', 'p', 'n', 0, 0, 0, 0, /* scan 50-57 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
'\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
},
{ /* right alt mode - not used in US keyboard */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 0 - 7 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 8 - F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10 -17 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 18 -1F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20 -27 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28 -2F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30 -37 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38 -3F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40 -47 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48 -4F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50 -57 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58 -5F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60 -67 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68 -6F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70 -77 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78 -7F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* extended */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 0 - 7 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 8 - F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10 -17 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 18 -1F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20 -27 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28 -2F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30 -37 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38 -3F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40 -47 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48 -4F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50 -57 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58 -5F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60 -67 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68 -6F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70 -77 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78 -7F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* extended */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */
}
},
{ /* german keyboard */
{ /* unshift code */
0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */
'7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 8- F */
'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */
'o', 'p', 0x81, '+', '\r', CN, 'a', 's', /* scan 18-1F */
'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */
0x84, '^', SH, '#', 'y', 'x', 'c', 'v', /* scan 28-2F */
'b', 'n', 'm', ',', '.', '-', SH, '*', /* scan 30-37 */
' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */
'8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
'2', '3', '0', ',', 0, 0, '<', 0, /* scan 50-57 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
'\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */
'7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 8- F */
'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */
'o', 'p', 0x81, '+', '\r', CN, 'a', 's', /* scan 18-1F */
'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */
0x84, '^', SH, '#', 'y', 'x', 'c', 'v', /* scan 28-2F */
'b', 'n', 'm', ',', '.', '-', SH, '*', /* scan 30-37 */
' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */
'8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
'2', '3', '0', ',', 0, 0, '<', 0, /* scan 50-57 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
'\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
},
{ /* shift code */
0, 0x1b, '!', '"', 0x15, '$', '%', '&', /* scan 0- 7 */
'/', '(', ')', '=', '?', '`', 0x08, '\t', /* scan 8- F */
'Q', 'W', 'E', 'R', 'T', 'Z', 'U', 'I', /* scan 10-17 */
'O', 'P', 0x9a, '*', '\r', CN, 'A', 'S', /* scan 18-1F */
'D', 'F', 'G', 'H', 'J', 'K', 'L', 0x99, /* scan 20-27 */
0x8e, 0xf8, SH, '\'', 'Y', 'X', 'C', 'V', /* scan 28-2F */
'B', 'N', 'M', ';', ':', '_', SH, '*', /* scan 30-37 */
' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */
'8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
'2', '3', '0', ',', 0, 0, '>', 0, /* scan 50-57 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
'\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
0, 0x1b, '!', '"', 0x15, '$', '%', '&', /* scan 0- 7 */
'/', '(', ')', '=', '?', '`', 0x08, '\t', /* scan 8- F */
'Q', 'W', 'E', 'R', 'T', 'Z', 'U', 'I', /* scan 10-17 */
'O', 'P', 0x9a, '*', '\r', CN, 'A', 'S', /* scan 18-1F */
'D', 'F', 'G', 'H', 'J', 'K', 'L', 0x99, /* scan 20-27 */
0x8e, 0xf8, SH, '\'', 'Y', 'X', 'C', 'V', /* scan 28-2F */
'B', 'N', 'M', ';', ':', '_', SH, '*', /* scan 30-37 */
' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */
'8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
'2', '3', '0', ',', 0, 0, '>', 0, /* scan 50-57 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
'\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
},
{ /* control code */
0xff, 0x1b, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, /* scan 0- 7 */
0x1e, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff, '\t', /* scan 8- F */
0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09, /* scan 10-17 */
0x0f, 0x10, 0x1b, 0x1d, '\r', CN, 0x01, 0x13, /* scan 18-1F */
0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0c, 0xff, /* scan 20-27 */
0xff, 0x1c, SH, 0xff, 0x1a, 0x18, 0x03, 0x16, /* scan 28-2F */
0x02, 0x0e, 0x0d, 0xff, 0xff, 0xff, SH, 0xff, /* scan 30-37 */
0xff, 0xff, CP, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */
0xff, 0xff, 0xff, 0xff, 0xff, NM, ST, 0xff, /* scan 40-47 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */
'\r', CN, '/', '*', ' ', ST, 0xff, 0xff, /* extended */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */
0xff, 0x1b, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, /* scan 0- 7 */
0x1e, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff, '\t', /* scan 8- F */
0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09, /* scan 10-17 */
0x0f, 0x10, 0x1b, 0x1d, '\r', CN, 0x01, 0x13, /* scan 18-1F */
0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0c, 0xff, /* scan 20-27 */
0xff, 0x1c, SH, 0xff, 0x1a, 0x18, 0x03, 0x16, /* scan 28-2F */
0x02, 0x0e, 0x0d, 0xff, 0xff, 0xff, SH, 0xff, /* scan 30-37 */
0xff, 0xff, CP, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */
0xff, 0xff, 0xff, 0xff, 0xff, NM, ST, 0xff, /* scan 40-47 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */
'\r', CN, '/', '*', ' ', ST, 0xff, 0xff, /* extended */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */
},
{ /* non numeric code */
0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */
'7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 8- F */
'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */
'o', 'p', 0x81, '+', '\r', CN, 'a', 's', /* scan 18-1F */
'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */
0x84, '^', SH, 0, 'y', 'x', 'c', 'v', /* scan 28-2F */
'b', 'n', 'm', ',', '.', '-', SH, '*', /* scan 30-37 */
' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
0, 0, 0, 0, 0, NM, ST, 'w', /* scan 40-47 */
'x', 'y', 'l', 't', 'u', 'v', 'm', 'q', /* scan 48-4F */
'r', 's', 'p', 'n', 0, 0, '<', 0, /* scan 50-57 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
'\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */
'7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 8- F */
'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */
'o', 'p', 0x81, '+', '\r', CN, 'a', 's', /* scan 18-1F */
'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */
0x84, '^', SH, 0, 'y', 'x', 'c', 'v', /* scan 28-2F */
'b', 'n', 'm', ',', '.', '-', SH, '*', /* scan 30-37 */
' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
0, 0, 0, 0, 0, NM, ST, 'w', /* scan 40-47 */
'x', 'y', 'l', 't', 'u', 'v', 'm', 'q', /* scan 48-4F */
'r', 's', 'p', 'n', 0, 0, '<', 0, /* scan 50-57 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
'\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
},
{ /* Right alt mode - is used in German keyboard */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 0 - 7 */
'{', '[', ']', '}', '\\', 0xff, 0xff, 0xff, /* scan 8 - F */
'@', 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10 -17 */
0xff, 0xff, 0xff, '~', 0xff, 0xff, 0xff, 0xff, /* scan 18 -1F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20 -27 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28 -2F */
0xff, 0xff, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30 -37 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38 -3F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40 -47 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48 -4F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, '|', 0xff, /* scan 50 -57 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58 -5F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60 -67 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68 -6F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70 -77 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78 -7F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* extended */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 0 - 7 */
'{', '[', ']', '}', '\\', 0xff, 0xff, 0xff, /* scan 8 - F */
'@', 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10 -17 */
0xff, 0xff, 0xff, '~', 0xff, 0xff, 0xff, 0xff, /* scan 18 -1F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20 -27 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28 -2F */
0xff, 0xff, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30 -37 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38 -3F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40 -47 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48 -4F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, '|', 0xff, /* scan 50 -57 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58 -5F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60 -67 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68 -6F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70 -77 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78 -7F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* extended */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */
}
}
};
@ -328,8 +328,8 @@ int i8042_kbd_init (void)
#ifdef CONFIG_USE_CPCIDVI
if ((penv = getenv ("console")) != NULL) {
if (strncmp (penv, "serial", 7) == 0) {
return -1;
if (strncmp (penv, "serial", 7) == 0) {
return -1;
}
}
#endif
@ -345,9 +345,9 @@ int i8042_kbd_init (void)
{
if (kbd_reset() == 0)
{
kbd_mapping = keymap;
kbd_flags = NORMAL;
kbd_state = 0;
kbd_mapping = keymap;
kbd_flags = NORMAL;
kbd_state = 0;
kbd_led_set();
return 0;
}
@ -359,7 +359,7 @@ int i8042_kbd_init (void)
/*******************************************************************************
*
* i8042_tstc - test if keyboard input is available
* option: cursor blinking if called in a loop
* option: cursor blinking if called in a loop
*/
int i8042_tstc (void)
{
@ -395,7 +395,7 @@ int i8042_tstc (void)
/*******************************************************************************
*
* i8042_getc - wait till keyboard input is available
* option: turn on/off cursor while waiting
* option: turn on/off cursor while waiting
*/
int i8042_getc (void)
{
@ -448,8 +448,8 @@ static void kbd_conv_char (unsigned char scan_code)
{
if (scan_code == 0xe1)
{
kbd_flags ^= BRK; /* reset the break flag */
kbd_flags ^= E1; /* bitwise EXOR with E1 flag */
kbd_flags ^= BRK; /* reset the break flag */
kbd_flags ^= E1; /* bitwise EXOR with E1 flag */
}
return;
}
@ -560,7 +560,7 @@ static void kbd_caps (unsigned char scan_code)
if ((kbd_flags & BRK) == NORMAL)
{
kbd_flags ^= CAPS;
kbd_led_set (); /* update keyboard LED */
kbd_led_set (); /* update keyboard LED */
}
}
@ -573,7 +573,7 @@ static void kbd_num (unsigned char scan_code)
{
kbd_flags ^= NUM;
kbd_state = (kbd_flags & NUM) ? AS : NM;
kbd_led_set (); /* update keyboard LED */
kbd_led_set (); /* update keyboard LED */
}
}
@ -585,7 +585,7 @@ static void kbd_scroll (unsigned char scan_code)
if ((kbd_flags & BRK) == NORMAL)
{
kbd_flags ^= STP;
kbd_led_set (); /* update keyboard LED */
kbd_led_set (); /* update keyboard LED */
if (kbd_flags & STP)
kbd_input = 0x13;
else
@ -615,9 +615,9 @@ static void kbd_alt (unsigned char scan_code)
static void kbd_led_set (void)
{
kbd_input_empty();
out8 (I8042_DATA_REG, 0xed); /* SET LED command */
out8 (I8042_DATA_REG, 0xed); /* SET LED command */
kbd_input_empty();
out8 (I8042_DATA_REG, (kbd_flags & 0x7)); /* LED bits only */
out8 (I8042_DATA_REG, (kbd_flags & 0x7)); /* LED bits only */
}

7
drivers/nand/diskonchip.c
View File

@ -20,7 +20,11 @@
*/
#include <common.h>
#ifdef CONFIG_NEW_NAND_CODE
#ifdef CFG_NAND_LEGACY
#error CFG_NAND_LEGACY defined in a file not using the legacy NAND support!
#endif
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/sched.h>
@ -1782,4 +1786,3 @@ module_exit(cleanup_nanddoc);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
MODULE_DESCRIPTION("M-Systems DiskOnChip 2000, Millennium and Millennium Plus device driver\n");
#endif /* CONFIG_NEW_NAND_CODE */

7
drivers/nand/nand.c
View File

@ -23,7 +23,10 @@
#include <common.h>
#ifdef CONFIG_NEW_NAND_CODE
#ifdef CFG_NAND_LEGACY
#error CFG_NAND_LEGACY defined in a file not using the legacy NAND support!
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <nand.h>
@ -72,5 +75,3 @@ void nand_init(void)
}
#endif
#endif /* CONFIG_NEW_NAND_CODE */

11
drivers/nand/nand_base.c
View File

@ -71,7 +71,10 @@
#endif
#include <common.h>
#ifdef CONFIG_NEW_NAND_CODE
#ifdef CFG_NAND_LEGACY
#error CFG_NAND_LEGACY defined in a file not using the legacy NAND support!
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
@ -864,10 +867,10 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
break;
}
}
/* XXX nand device 1 on dave (PPChameleonEVB) needs more time */
#ifdef PPCHAMELON_NAND_TIMER_HACK
reset_timer();
while (get_timer(0) < 10);
#endif /* PPCHAMELON_NAND_TIMER_HACK */
return this->read_byte(mtd);
}
@ -2663,5 +2666,3 @@ void nand_release (struct mtd_info *mtd)
}
#endif
#endif /* CONFIG_NEW_NAND_CODE */

7
drivers/nand/nand_bbt.c
View File

@ -54,7 +54,10 @@
#include <common.h>
#ifdef CONFIG_NEW_NAND_CODE
#ifdef CFG_NAND_LEGACY
#error CFG_NAND_LEGACY defined in a file not using the legacy NAND support!
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <malloc.h>
@ -1051,5 +1054,3 @@ int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt)
}
#endif
#endif /* CONFIG_NEW_NAND_CODE */

7
drivers/nand/nand_ecc.c
View File

@ -37,7 +37,10 @@
#include <common.h>
#ifdef CONFIG_NEW_NAND_CODE
#ifdef CFG_NAND_LEGACY
#error CFG_NAND_LEGACY defined in a file not using the legacy NAND support!
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include<linux/mtd/mtd.h>
@ -243,5 +246,3 @@ int nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_cha
}
#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */
#endif /* CONFIG_NEW_NAND_CODE */

7
drivers/nand/nand_ids.c
View File

@ -13,7 +13,10 @@
#include <common.h>
#ifdef CONFIG_NEW_NAND_CODE
#ifdef CFG_NAND_LEGACY
#error CFG_NAND_LEGACY defined in a file not using the legacy NAND support!
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
@ -127,5 +130,3 @@ struct nand_manufacturers nand_manuf_ids[] = {
{0x0, "Unknown"}
};
#endif
#endif /* CONFIG_NEW_NAND_CODE */

16
drivers/nand_legacy/Makefile Normal file
View File

@ -0,0 +1,16 @@
include $(TOPDIR)/config.mk
LIB := libnand_legacy.a
OBJS := nand_legacy.o
all: $(LIB)
$(LIB): $(OBJS)
$(AR) crv $@ $(OBJS)
#########################################################################
.depend: Makefile $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
sinclude .depend

1615
drivers/nand_legacy/nand_legacy.c Normal file
View File

File diff suppressed because it is too large Load Diff

24
fs/jffs2/jffs2_1pass.c
View File

@ -143,7 +143,8 @@
/* keeps pointer to currentlu processed partition */
static struct part_info *current_part;
#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CONFIG_NEW_NAND_CODE)
#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <nand.h>
/*
* Support for jffs2 on top of NAND-flash
*
@ -154,9 +155,8 @@ static struct part_info *current_part;
*
*/
/* this one defined in cmd_nand.c */
int read_jffs2_nand(size_t start, size_t len,
size_t * retlen, u_char * buf, int nanddev);
/* info for NAND chips, defined in drivers/nand/nand.c */
extern nand_info_t nand_info[];
#define NAND_PAGE_SIZE 512
#define NAND_PAGE_SHIFT 9
@ -167,6 +167,7 @@ int read_jffs2_nand(size_t start, size_t len,
#endif
#define NAND_CACHE_SIZE (NAND_CACHE_PAGES*NAND_PAGE_SIZE)
#ifdef CFG_NAND_LEGACY
static u8* nand_cache = NULL;
static u32 nand_cache_off = (u32)-1;
@ -174,7 +175,7 @@ static int read_nand_cached(u32 off, u32 size, u_char *buf)
{
struct mtdids *id = current_part->dev->id;
u32 bytes_read = 0;
size_t retlen;
ulong retlen;
int cpy_bytes;
while (bytes_read < size) {
@ -191,8 +192,10 @@ static int read_nand_cached(u32 off, u32 size, u_char *buf)
return -1;
}
}
if (read_jffs2_nand(nand_cache_off, NAND_CACHE_SIZE,
&retlen, nand_cache, id->num) < 0 ||
retlen = NAND_CACHE_SIZE;
if (nand_read(&nand_info[id->num], nand_cache_off,
&retlen, nand_cache) != 0 ||
retlen != NAND_CACHE_SIZE) {
printf("read_nand_cached: error reading nand off %#x size %d bytes\n",
nand_cache_off, NAND_CACHE_SIZE);
@ -248,6 +251,7 @@ static void put_fl_mem_nand(void *buf)
{
free(buf);
}
#endif /* CFG_NAND_LEGACY */
#endif /* #if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) */
@ -290,7 +294,7 @@ static inline void *get_fl_mem(u32 off, u32 size, void *ext_buf)
return get_fl_mem_nor(off);
#endif
#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CONFIG_NEW_NAND_CODE)
#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
if (id->type == MTD_DEV_TYPE_NAND)
return get_fl_mem_nand(off, size, ext_buf);
#endif
@ -308,7 +312,7 @@ static inline void *get_node_mem(u32 off)
return get_node_mem_nor(off);
#endif
#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CONFIG_NEW_NAND_CODE)
#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
if (id->type == MTD_DEV_TYPE_NAND)
return get_node_mem_nand(off);
#endif
@ -319,7 +323,7 @@ static inline void *get_node_mem(u32 off)
static inline void put_fl_mem(void *buf)
{
#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CONFIG_NEW_NAND_CODE)
#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
struct mtdids *id = current_part->dev->id;
if (id->type == MTD_DEV_TYPE_NAND)

2
fs/jffs2/jffs2_nand_1pass.c
View File

@ -1,6 +1,6 @@
#include <common.h>
#if defined(CONFIG_NEW_NAND_CODE) && (CONFIG_COMMANDS & CFG_CMD_JFFS2)
#if !defined(CFG_NAND_LEGACY) && (CONFIG_COMMANDS & CFG_CMD_JFFS2)
#include <malloc.h>
#include <linux/stat.h>

4
include/asm-arm/arch-pxa/pxa-regs.h
View File

@ -1009,7 +1009,7 @@ typedef void (*ExcpHndlr) (void) ;
* - GPIO
* - Data Flash DF_* pins defined.
*/
#define GPIO0 __REG(0x40e10124)
#define GPIO0 __REG(0x40e10124)
#define GPIO1 __REG(0x40e10128)
#define GPIO2 __REG(0x40e1012c)
#define GPIO3 __REG(0x40e10130)
@ -2058,8 +2058,6 @@ typedef void (*ExcpHndlr) (void) ;
#define MDCNFG_DCSE1 0x2 /* SDRAM CS 1 Enable */
#define MDCNFG_DCSE0 0x1 /* SDRAM CS 0 Enable */
/* Data Flash Controller Registers */

3
include/configs/ASH405.h
View File

@ -132,6 +132,9 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_NAND_LEGACY
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512

4
include/configs/BMW.h
View File

@ -69,6 +69,10 @@
CFG_CMD_DOC | \
CFG_CMD_ELF | \
0 )
/* CFG_CMD_DOC required legacy NAND support */
#define CFG_NAND_LEGACY
#if 0
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | \
CFG_CMD_PCI | CFG_CMD_DOC | CFG_CMD_DATE)

2
include/configs/CMS700.h
View File

@ -81,6 +81,8 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */

2
include/configs/CPCI405.h
View File

@ -79,6 +79,8 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */

2
include/configs/CPCI4052.h
View File

@ -100,6 +100,8 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */

3
include/configs/CPCI405AB.h
View File

@ -87,6 +87,9 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */

2
include/configs/CPCI405DT.h
View File

@ -98,6 +98,8 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */

218
include/configs/CPCI750.h
View File

@ -12,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -57,7 +57,7 @@
#define CONFIG_CPCI750 1 /* this is an CPCI750 board */
#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */
#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */
#undef CONFIG_ECC /* enable ECC support */
@ -84,19 +84,19 @@
* for your console driver.
*
* what to do:
* to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
* to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
* cable onto the second DUART channel, change the CFG_DUART port from 1
* to 0 below.
*
* to use the MPSC, #define CONFIG_MPSC. If you have wired up another
* mpsc channel, change CONFIG_MPSC_PORT to the desired value.
*/
#define CONFIG_MPSC
#define CONFIG_MPSC
#define CONFIG_MPSC_PORT 0
/* to change the default ethernet port, use this define (options: 0, 1, 2) */
#define CONFIG_NET_MULTI
#define MV_ETH_DEVS 1
#define MV_ETH_DEVS 1
#define CONFIG_ETHER_PORT 0
#undef CONFIG_ETHER_PORT_MII /* use RMII */
@ -118,38 +118,38 @@
#define CONFIG_SERIAL "AA000001"
#define CONFIG_SERVERIP "10.0.0.79"
#define CONFIG_ROOTPATH "/export/nfs_cpci750/%s"
#define CONFIG_ROOTPATH "/export/nfs_cpci750/%s"
#define CONFIG_TESTDRAMDATA y
#define CONFIG_TESTDRAMADDRESS n
#define CONFIG_TESTDRAMADDRESS n
#define CONFIG_TESETDRAMWALK n
/* ----------------------------------------------------------------------------- */
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_ALTIVEC /* undef to disable */
#undef CONFIG_ALTIVEC /* undef to disable */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
CONFIG_BOOTP_BOOTFILESIZE)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_ASKENV \
| CFG_CMD_I2C \
| CFG_CMD_I2C \
| CFG_CMD_CACHE \
| CFG_CMD_EEPROM \
| CFG_CMD_PCI \
| CFG_CMD_PCI \
| CFG_CMD_ELF \
| CFG_CMD_DATE \
| CFG_CMD_NET \
| CFG_CMD_PING \
| CFG_CMD_IDE \
| CFG_CMD_FAT \
| CFG_CMD_EXT2 \
| CFG_CMD_NET \
| CFG_CMD_PING \
| CFG_CMD_IDE \
| CFG_CMD_FAT \
| CFG_CMD_EXT2 \
)
#define CONFIG_DOS_PARTITION
@ -159,7 +159,7 @@
#define CONFIG_USE_CPCIDVI
#ifdef CONFIG_USE_CPCIDVI
#ifdef CONFIG_USE_CPCIDVI
#define CONFIG_VIDEO
#define CONFIG_VIDEO_CT69000
#define CONFIG_CFB_CONSOLE
@ -174,23 +174,23 @@
*/
#define CFG_I2C_EEPROM_ADDR_LEN 2
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_SPEED 80000 /* I2C speed default */
#define CFG_I2C_SPEED 80000 /* I2C speed default */
#define CFG_GT_DUAL_CPU /* also for JTAG even with one cpu */
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
/*#define CFG_MEMTEST_START 0x00400000*/ /* memtest works on */
/*#define CFG_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */
/*#define CFG_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */
/*#define CFG_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */
/*
#define CFG_DRAM_TEST
@ -198,21 +198,21 @@
* CFG_DRAM_TEST - enables the following tests.
*
* CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
* Environment variable 'test_dram_data' must be
* set to 'y'.
* Environment variable 'test_dram_data' must be
* set to 'y'.
* CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
* addressable. Environment variable
* 'test_dram_address' must be set to 'y'.
* addressable. Environment variable
* 'test_dram_address' must be set to 'y'.
* CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
* This test takes about 6 minutes to test 64 MB.
* Environment variable 'test_dram_walk' must be
* set to 'y'.
* This test takes about 6 minutes to test 64 MB.
* Environment variable 'test_dram_walk' must be
* set to 'y'.
*/
#define CFG_DRAM_TEST
#if defined(CFG_DRAM_TEST)
#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
/*#define CFG_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */
#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
#define CFG_DRAM_TEST_DATA
#define CFG_DRAM_TEST_ADDRESS
#define CFG_DRAM_TEST_WALK
@ -221,10 +221,10 @@
#define CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */
#undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */
#define CFG_LOAD_ADDR 0x00300000 /* default load address */
#define CFG_LOAD_ADDR 0x00300000 /* default load address */
#define CFG_HZ 1000 /* decr freq: 1ms ticks */
#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */
#define CFG_HZ 1000 /* decr freq: 1ms ticks */
#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */
#define CFG_BUS_CLK CFG_BUS_HZ
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
@ -251,7 +251,7 @@
* To an unused memory region. The stack will remain in cache until RAM
* is initialized
*/
#undef CFG_INIT_RAM_LOCK
#undef CFG_INIT_RAM_LOCK
/* #define CFG_INIT_RAM_ADDR 0x40000000*/ /* unused memory region */
/* #define CFG_INIT_RAM_ADDR 0xfba00000*/ /* unused memory region */
#define CFG_INIT_RAM_ADDR 0xf1080000 /* unused memory region */
@ -261,7 +261,7 @@
#define RELOCATE_INTERNAL_RAM_ADDR
#ifdef RELOCATE_INTERNAL_RAM_ADDR
/*#define CFG_INTERNAL_RAM_ADDR 0xfba00000*/
/*#define CFG_INTERNAL_RAM_ADDR 0xfba00000*/
#define CFG_INTERNAL_RAM_ADDR 0xf1080000
#endif
@ -270,16 +270,16 @@
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_BASE 0x00000000
/* Dummies for BAT 4-7 */
#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */
#define CFG_SDRAM2_BASE 0x20000000
#define CFG_SDRAM3_BASE 0x30000000
#define CFG_SDRAM4_BASE 0x40000000
#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */
#define CFG_SDRAM2_BASE 0x20000000
#define CFG_SDRAM3_BASE 0x30000000
#define CFG_SDRAM4_BASE 0x40000000
#define CFG_RESET_ADDRESS 0xfff00100
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MONITOR_BASE 0xfff00000
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */
/*-----------------------------------------------------------------------
* FLASH related
@ -289,15 +289,15 @@
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_FLASH_BASE 0xfc000000 /* start of flash banks */
#define CFG_FLASH_BASE 0xfc000000 /* start of flash banks */
#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */
#define CFG_FLASH_INCREMENT 0x01000000 /* size of flash bank */
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \
CFG_FLASH_BASE + 1*CFG_FLASH_INCREMENT, \
CFG_FLASH_BASE + 2*CFG_FLASH_INCREMENT, \
CFG_FLASH_BASE + 3*CFG_FLASH_INCREMENT }
#define CFG_FLASH_EMPTY_INFO 1 /* show if bank is empty */
#define CFG_FLASH_INCREMENT 0x01000000 /* size of flash bank */
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \
CFG_FLASH_BASE + 1*CFG_FLASH_INCREMENT, \
CFG_FLASH_BASE + 2*CFG_FLASH_INCREMENT, \
CFG_FLASH_BASE + 3*CFG_FLASH_INCREMENT }
#define CFG_FLASH_EMPTY_INFO 1 /* show if bank is empty */
/* areas to map different things with the GT in physical space */
#define CFG_DRAM_BANKS 4
@ -308,20 +308,20 @@
/* Peripheral Device section */
/*******************************************************/
/* We have on the cpci750 Board : */
/* GT-Chipset Register Area */
/* GT-Chipset internal SRAM 256k */
/* SRAM on external device module */
/* Real time clock on external device module */
/* dobble UART on external device module */
/* Data flash on external device module */
/* Boot flash on external device module */
/* We have on the cpci750 Board : */
/* GT-Chipset Register Area */
/* GT-Chipset internal SRAM 256k */
/* SRAM on external device module */
/* Real time clock on external device module */
/* dobble UART on external device module */
/* Data flash on external device module */
/* Boot flash on external device module */
/*******************************************************/
#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
#define CFG_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */
#define CFG_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */
#undef MARVEL_STANDARD_CFG
#ifndef MARVEL_STANDARD_CFG
#undef MARVEL_STANDARD_CFG
#ifndef MARVEL_STANDARD_CFG
/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
#define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */
/*#define CFG_DEV_BASE 0xfc000000*/ /* GT Devices CS start here */
@ -333,11 +333,11 @@
#define CFG_DEV2_SPACE 0xfe000000 /* DEV_CS2 flash 3 */
#define CFG_DEV3_SPACE 0xf0000000 /* DEV_CS3 nvram/can */
#define CFG_BOOT_SIZE _16M /* cpci750 flash 0 */
#define CFG_DEV0_SIZE _16M /* cpci750 flash 1 */
#define CFG_DEV1_SIZE _16M /* cpci750 flash 2 */
#define CFG_DEV2_SIZE _16M /* cpci750 flash 3 */
#define CFG_DEV3_SIZE _16M /* cpci750 nvram/can */
#define CFG_BOOT_SIZE _16M /* cpci750 flash 0 */
#define CFG_DEV0_SIZE _16M /* cpci750 flash 1 */
#define CFG_DEV1_SIZE _16M /* cpci750 flash 2 */
#define CFG_DEV2_SIZE _16M /* cpci750 flash 3 */
#define CFG_DEV3_SIZE _16M /* cpci750 nvram/can */
/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
#endif
@ -346,22 +346,22 @@
#define CFG_DEV0_PAR 0x8FDFFFFF /* 16 bit flash */
#define CFG_DEV1_PAR 0x8FDFFFFF /* 16 bit flash */
#define CFG_DEV2_PAR 0x8FDFFFFF /* 16 bit flash */
#define CFG_DEV3_PAR 0x8FCFFFFF /* nvram/can */
#define CFG_DEV3_PAR 0x8FCFFFFF /* nvram/can */
#define CFG_BOOT_PAR 0x8FDFFFFF /* 16 bit flash */
/* c 4 a 8 2 4 1 c */
/* 33 22|2222|22 22|111 1|11 11|1 1 | | */
/* c 4 a 8 2 4 1 c */
/* 33 22|2222|22 22|111 1|11 11|1 1 | | */
/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
/* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
/* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
/* MPP Control MV64360 Appendix P P. 632*/
#define CFG_MPP_CONTROL_0 0x00002222 /* */
#define CFG_MPP_CONTROL_1 0x11110000 /* */
#define CFG_MPP_CONTROL_2 0x11111111 /* */
#define CFG_MPP_CONTROL_3 0x00001111 /* */
/* #define CFG_SERIAL_PORT_MUX 0x00000102*/ /* */
#define CFG_MPP_CONTROL_0 0x00002222 /* */
#define CFG_MPP_CONTROL_1 0x11110000 /* */
#define CFG_MPP_CONTROL_2 0x11111111 /* */
#define CFG_MPP_CONTROL_3 0x00001111 /* */
/* #define CFG_SERIAL_PORT_MUX 0x00000102*/ /* */
#define CFG_GPP_LEVEL_CONTROL 0xffffffff /* 1111 1111 1111 1111 1111 1111 1111 1111*/
@ -378,12 +378,12 @@
ECC disable
non registered DRAM */
/* 31:26 25:22 21:20 19 18 17 16 */
/* 100001 0000 010 0 0 0 0 */
/* 100001 0000 010 0 0 0 0 */
/* refresh_count=0x400
phisical interleaving disable
virtual interleaving enable */
/* 15 14 13:0 */
/* 0 1 0x400 */
/* 0 1 0x400 */
# define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/
@ -392,14 +392,14 @@
*-----------------------------------------------------------------------
*/
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */
/* PCI MEMORY MAP section */
#define CFG_PCI0_MEM_BASE 0x80000000
@ -433,21 +433,21 @@
* IDE/ATA stuff
*-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
#undef CONFIG_IDE_LED /* no led for ide supported */
#define CONFIG_IDE_RESET /* no reset for ide supported */
#define CONFIG_IDE_PREINIT /* check for units */
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
#undef CONFIG_IDE_LED /* no led for ide supported */
#define CONFIG_IDE_RESET /* no reset for ide supported */
#define CONFIG_IDE_PREINIT /* check for units */
#define CFG_IDE_MAXBUS 2 /* max. 1 IDE busses */
#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */
#define CFG_IDE_MAXBUS 2 /* max. 1 IDE busses */
#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */
#define CFG_ATA_BASE_ADDR 0
#define CFG_ATA_IDE0_OFFSET 0
#define CFG_ATA_IDE1_OFFSET 0
#define CFG_ATA_BASE_ADDR 0
#define CFG_ATA_IDE0_OFFSET 0
#define CFG_ATA_IDE1_OFFSET 0
#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
/*----------------------------------------------------------------------
@ -551,7 +551,7 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
@ -563,23 +563,23 @@
#define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */
#if 0
#define CFG_ENV_IS_IN_FLASH 0
#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
#define CFG_ENV_IS_IN_FLASH 0
#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x10000
#define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
#endif
#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
#define CFG_EEPROM_PAGE_WRITE_BITS 5
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
#define CFG_I2C_EEPROM_ADDR 0x050
#define CFG_I2C_EEPROM_ADDR 0x050
#define CFG_ENV_OFFSET 0x200 /* environment starts at the beginning of the EEPROM */
#define CFG_ENV_SIZE 0x600 /* 2048 bytes may be used for env vars*/
#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-0x40)
#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-0x40)
/*-----------------------------------------------------------------------
* Cache Configuration
@ -601,7 +601,7 @@
#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
#define L2_INIT 0
#else
#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
#endif
@ -612,9 +612,9 @@
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_BOARD_ASM_INIT 1
#define CFG_BOARD_ASM_INIT 1
#endif /* __CONFIG_H */

2
include/configs/CPU86.h
View File

@ -178,6 +178,8 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
/*
* Miscellaneous configurable options
*/

2
include/configs/CPU87.h
View File

@ -189,6 +189,8 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
/*
* Miscellaneous configurable options
*/

2
include/configs/GEN860T.h
View File

@ -284,6 +284,8 @@
*/
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
/*
* Verbose help from command monitor.
*/

2
include/configs/HH405.h
View File

@ -130,6 +130,8 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
#undef CONFIG_BZIP2 /* include support for bzip2 compressed images */
#undef CONFIG_WATCHDOG /* watchdog disabled */

2
include/configs/HUB405.h
View File

@ -135,6 +135,8 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_NAND_LEGACY
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512

2
include/configs/MIP405.h
View File

@ -87,6 +87,8 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
/**************************************************************

1
include/configs/NETPHONE.h
View File

@ -491,6 +491,7 @@
/****************************************************************/
/* NAND */
#define CFG_NAND_LEGACY
#define CFG_NAND_BASE NAND_BASE
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CONFIG_MTD_NAND_VERIFY_WRITE

1
include/configs/NETTA2.h
View File

@ -491,6 +491,7 @@
/****************************************************************/
/* NAND */
#define CFG_NAND_LEGACY
#define CFG_NAND_BASE NAND_BASE
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CONFIG_MTD_NAND_VERIFY_WRITE

2
include/configs/NETVIA.h
View File

@ -387,6 +387,8 @@
/*****************************************************************************/
#define CFG_NAND_LEGACY
#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
/* NAND */

1
include/configs/PCIPPC2.h
View File

@ -77,6 +77,7 @@
*/
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
/*
* Miscellaneous configurable options

1
include/configs/PCIPPC6.h
View File

@ -79,6 +79,7 @@
*/
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
/*
* Miscellaneous configurable options

2
include/configs/PIP405.h
View File

@ -69,6 +69,8 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
/**************************************************************

2
include/configs/PLU405.h
View File

@ -160,6 +160,8 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_NAND_LEGACY
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512

2
include/configs/PM520.h
View File

@ -101,6 +101,8 @@
#define ADD_DOC_CMD 0
#else
#define ADD_DOC_CMD CFG_CMD_DOC
/* DoC requires legacy NAND for now */
#define CFG_NAND_LEGACY
#endif
/*

2
include/configs/PM826.h
View File

@ -180,6 +180,8 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
/*
* Disk-On-Chip configuration
*/

1
include/configs/PM828.h
View File

@ -183,6 +183,7 @@
/*
* Disk-On-Chip configuration
*/
#define CFG_NAND_LEGACY
#define CFG_DOC_SHORT_TIMEOUT
#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */

105
include/configs/PPChameleonEVB.h
View File

@ -188,36 +188,31 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
/*
* nand device 1 on dave (PPChameleonEVB) needs more time,
* so we just introduce additional wait in nand_wait(),
* effectively for both devices.
*/
#define PPCHAMELON_NAND_TIMER_HACK
/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
#define CONFIG_NEW_NAND_CODE
#define CFG_NAND0_BASE 0xFF400000
#define CFG_NAND1_BASE 0xFF000000
#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, CFG_NAND1_BASE }
#define NAND_BIG_DELAY_US 25
#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
#define SECTORSIZE 512
#define NAND_NO_RB
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CFG_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CFG_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
#define CFG_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
#define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
#ifdef CONFIG_NEW_NAND_CODE
#define MACRO_NAND_DISABLE_CE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
@ -293,83 +288,17 @@
break; \
} \
} while(0)
#else
#define NAND_DISABLE_CE(nand) do \
{ \
switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
{ \
case CFG_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
break; \
case CFG_NAND1_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
break; \
} \
} while(0)
#define NAND_ENABLE_CE(nand) do \
{ \
switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
{ \
case CFG_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
break; \
case CFG_NAND1_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
break; \
} \
} while(0)
#if 0
#define SECTORSIZE 512
#define NAND_NO_RB
#define NAND_CTL_CLRALE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
case CFG_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
break; \
case CFG_NAND1_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
break; \
} \
} while(0)
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_CTL_SETALE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
case CFG_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
break; \
case CFG_NAND1_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
break; \
} \
} while(0)
#define NAND_CTL_CLRCLE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
case CFG_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
break; \
case CFG_NAND1_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
break; \
} \
} while(0)
#define NAND_CTL_SETCLE(nandptr) do { \
switch((unsigned long)nandptr) { \
case CFG_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
break; \
case CFG_NAND1_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
break; \
} \
} while(0)
#endif /* !CONFIG_NEW_NAND_CODE */
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#ifdef NAND_NO_RB
/* constant delay (see also tR in the datasheet) */
@ -385,7 +314,7 @@
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#endif
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------

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