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Merge with /home/wd/git/u-boot/master 

Code cleanup.
This commit is contained in:
Wolfgang Denk 2006-03-06 23:18:48 +01:00
parent ac7d97dcbb bfc81252c0
commit 951a954b77
114 changed files with 4789 additions and 3604 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

57
CHANGELOG
View File

@ -2,11 +2,66 @@
Changes since U-Boot 1.1.4:
======================================================================
* Merge the new NAND code (testing-NAND brach)
* Minor code cleanup
* Merge the new NAND code (testing-NAND brach); see doc/README.nand
Rewrite of NAND code based on what is in 2.6.12 Linux kernel
Patch by Ladislav Michl, 29 Jun 2005
* Add lowboot target to mcc200 board
Patch by Stefan Roese, 4 Mar 2006
* Fix problem with flash_get_size() from CFI driver update
Patch by Stefan Roese, 1 Mar 2006
* Make CFG_NO_FLASH work on ARM systems
Patch by Markus Klotzbuecher, 27 Feb 2006
* Update mcc200 config: Disable PCI and DoC, use 133 MHz IPB clock,
use hush shell.
* Convert mcc200 to use common CFI flash driver
Patch by Stefan Roese, 28 Feb 2006
* Add env-variable "unlock" to handle initial state of sectors
(locked/unlocked).
Only the U-Boot image and it's environment is protected,
all other sectors are unprotected (unlocked) if flash
hardware protection is used (CFG_FLASH_PROTECTION) and
the environment variable "unlock" is set to "yes".
Patch by Stefan Roese, 28 Feb 2006
* Update drivers/cfi_flash.c:
- find_sector() called in both versions of flash_write_cfiword()
Patch by Peter Pearse, 27th Feb 2006
* CFI support for a x8/x16 AMD/Spansion flash configured in x8 mode
Patch by Jose Maria Lopez, 16 Jan 2006
* Add support for AMD/Spansion Flashes in flash_write_cfibuffer
Patch by Alex Bastos and Thomas Schaefer, 2005-08-29
* Changes/fixes for drivers/cfi_flash.c:
We *should* check if there are any error bits if the previous call
returned ERR_OK (Otherwise we will have output an error message in
flash_status_check() already.) The original code would only check for
error bits if flash_status_check() returns ERR_TIMEOUT.
Patch by Marcus Hall, 23 Aug 2005
* Changes/fixes for drivers/cfi_flash.c:
- Add CFG_FLASH_PROTECT_CLEAR on drivers/cfi_flash.c
- Prohibit buffer write when buffer_size is 1 on drivers/cfi_flash.c
Patch by Sangmoon Kim, 19 Aug 2005
* Fixes for drivers/cfi_flash.c:
- Fix wrong timeout value usage in flash_status_check()
- Round write_tout up when converting to msec in flash_get_size()
- Remove clearing flash status at the end of flash_write_cfibuffer()
which sets Intel 28F640J3 flash back to command mode on CSB472
Patch by Tolunay Orkun, 02 July 2005
* Add basic support for the SMMACO4 Board from PanDaCom.
Patch by Heiko Schocher, 20 Feb 2006

12
MAKEALL
View File

@ -26,8 +26,8 @@ LIST_5xx=" \
LIST_5xxx=" \
cpci5200 icecube_5100 icecube_5200 EVAL5200 \
pf5200 PM520 Total5100 Total5200 \
Total5200_Rev2 TQM5200_auto o2dnt \
mcc200 o2dnt pf5200 PM520 \
Total5100 Total5200 Total5200_Rev2 TQM5200_auto \
"
#########################################################################
@ -177,10 +177,10 @@ LIST_ARM9=" \
ap920t ap922_XA10 ap926ejs ap946es \
ap966 cp920t cp922_XA10 cp926ejs \
cp946es cp966 lpd7a400 mp2usb \
mx1ads mx1fs2 omap1510inn omap1610h2 \
omap1610inn omap730p2 scb9328 smdk2400 \
smdk2410 trab VCMA9 versatile \
versatileab versatilepb voiceblue
mx1ads mx1fs2 netstar omap1510inn \
omap1610h2 omap1610inn omap730p2 scb9328 \
smdk2400 smdk2410 trab VCMA9 \
versatile versatileab versatilepb voiceblue
"
#########################################################################

17
Makefile
View File

@ -298,11 +298,20 @@ icecube_5100_config: unconfig
inka4x0_config: unconfig
@./mkconfig inka4x0 ppc mpc5xxx inka4x0
mcc200_config \
mcc200_lowboot_config: unconfig
@ >include/config.h
@[ -z "$(findstring lowboot_,$@)" ] || \
{ echo "TEXT_BASE = 0xFE000000" >board/mcc200/config.tmp ; \
echo "... with lowboot configuration" ; \
}
@./mkconfig mcc200 ppc mpc5xxx mcc200
o2dnt_config:
@./mkconfig -a o2dnt ppc mpc5xxx o2dnt
@./mkconfig o2dnt ppc mpc5xxx o2dnt
pf5200_config: unconfig
@./mkconfig -a pf5200 ppc mpc5xxx pf5200 esd
@./mkconfig pf5200 ppc mpc5xxx pf5200 esd
PM520_config \
PM520_DDR_config \
@ -1870,15 +1879,13 @@ clean:
rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image
rm -f board/trab/trab_fkt board/voiceblue/eeprom
rm -f board/integratorap/u-boot.lds board/integratorcp/u-boot.lds
rm -f u-boot.objdump-*
clobber: clean
find . -type f \( -name .depend \
-o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \
-print0 \
| xargs -0 rm -f
rm -f $(OBJS) *.bak tags include/version_autogenerated.h
rm -f $(OBJS) *.bak tags TAGS include/version_autogenerated.h
rm -fr *.*~
rm -f u-boot u-boot.map u-boot.hex $(ALL)
rm -f tools/crc32.c tools/environment.c tools/env/crc32.c

2
board/amcc/bamboo/bamboo.c
View File

@ -277,7 +277,7 @@ int board_early_init_f(void)
}
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
/*----------------------------------------------------------------------------+

3
board/amcc/bamboo/config.mk
View File

@ -32,3 +32,6 @@ endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
endif
# legacy nand support
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

5
board/dave/PPChameleonEVB/config.mk
View File

@ -27,5 +27,8 @@
# Reserve 320 kB for Monitor
TEXT_BASE = 0xFFFB0000
# Compile the new NAND code (needed iff #ifdef CONFIG_NEW_NAND_CODE)
# Compile the new NAND code (CFG_NAND_LEGACY mustn't be defined)
BOARDLIBS = drivers/nand/libnand.a
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
#BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

36
board/dave/PPChameleonEVB/nand.c
View File

@ -22,9 +22,8 @@
#include <common.h>
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#ifdef CONFIG_NEW_NAND_CODE
/* new NAND handling */
#include <nand.h>
@ -90,7 +89,7 @@ static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo)
/*
* Board-specific NAND initialization. The following members of the
* argument are board-specific (per include/linux/mtd/nand_new.h):
* argument are board-specific (per include/linux/mtd/nand.h):
* - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
* - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
* - hwcontrol: hardwarespecific function for accesing control-lines
@ -115,33 +114,4 @@ void board_nand_init(struct nand_chip *nand)
nand->chip_delay = NAND_BIG_DELAY_US;
nand->options = NAND_SAMSUNG_LP_OPTIONS;
}
#else
/* old NAND handling */
extern ulong
nand_probe(ulong physadr);
void
nand_init(void)
{
ulong totlen = 0;
/*
The HI model is equipped with a large block NAND chip not supported yet
by U-Boot
(CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
*/
#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
totlen += nand_probe (CFG_NAND0_BASE);
#endif /* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */
debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE);
totlen += nand_probe (CFG_NAND1_BASE);
printf ("%3lu MB\n", totlen >>20);
}
#endif
#endif
#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */

1
board/delta/config.mk
View File

@ -6,4 +6,3 @@ TEXT_BASE = 0xa3008000
# Compile the new NAND code (needed iff #ifdef CONFIG_NEW_NAND_CODE)
BOARDLIBS = drivers/nand/libnand.a

8
board/delta/lowlevel_init.S
View File

@ -281,13 +281,13 @@ mem_init:
/* Disable software and data breakpoints */
mov r0, #0
mcr p15,0,r0,c14,c8,0 // ibcr0
mcr p15,0,r0,c14,c9,0 // ibcr1
mcr p15,0,r0,c14,c4,0 // dbcon
mcr p15,0,r0,c14,c8,0 /* ibcr0 */
mcr p15,0,r0,c14,c9,0 /* ibcr1 */
mcr p15,0,r0,c14,c4,0 /* dbcon */
/* Enable all debug functionality */
mov r0,#0x80000000
mcr p14,0,r0,c10,c0,0 // dcsr
mcr p14,0,r0,c10,c0,0 /* dcsr */
endlowlevel_init:

2
board/delta/nand.c
View File

@ -528,8 +528,6 @@ void board_nand_init(struct nand_chip *nand)
(tWHR << 4) |
(tAR << 0);
/* If it doesn't work (unlikely) think about:
* - ecc enable
* - chip select don't care

2
board/esd/ash405/ash405.c
View File

@ -239,7 +239,7 @@ int testdram (void)
/* ------------------------------------------------------------------------- */
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)

3
board/esd/ash405/config.mk
View File

@ -26,3 +26,6 @@
#
TEXT_BASE = 0xFFFC0000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

2
board/esd/cms700/cms700.c
View File

@ -238,7 +238,7 @@ U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
/* ------------------------------------------------------------------------- */
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)

3
board/esd/cms700/config.mk
View File

@ -26,3 +26,6 @@
#
TEXT_BASE = 0xFFFC0000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

25
board/esd/common/auto_update.c
View File

@ -23,10 +23,15 @@
*/
#include <common.h>
#ifndef CFG_NAND_LEGACY
#error CFG_NAND_LEGACY not defined in a file using the legacy NAND support!
#endif
#include <command.h>
#include <image.h>
#include <asm/byteorder.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
#include <fat.h>
#include "auto_update.h"
@ -76,9 +81,9 @@ extern block_dev_desc_t *get_dev (char*, int);
#define NANDRW_JFFS2 0x02
#define NANDRW_JFFS2_SKIP 0x04
extern struct nand_chip nand_dev_desc[];
extern int nand_rw(struct nand_chip* nand, int cmd, size_t start, size_t len,
extern int nand_legacy_rw(struct nand_chip* nand, int cmd, size_t start, size_t len,
size_t * retlen, u_char * buf);
extern int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean);
extern int nand_legacy_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean);
#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
extern block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE];
@ -259,9 +264,9 @@ int au_do_update(int i, long sz)
} else {
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
printf("Updating NAND FLASH with image %s\n", au_image[i].name);
debug ("nand_erase(%lx, %lx);\n", start, end);
rc = nand_erase (nand_dev_desc, start, end - start + 1, 0);
debug ("nand_erase returned %x\n", rc);
debug ("nand_legacy_erase(%lx, %lx);\n", start, end);
rc = nand_legacy_erase (nand_dev_desc, start, end - start + 1, 0);
debug ("nand_legacy_erase returned %x\n", rc);
#endif
}
@ -286,10 +291,10 @@ int au_do_update(int i, long sz)
rc = flash_write((char *)addr, start, nbytes);
} else {
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
debug ("nand_rw(%p, %lx %x)\n", addr, start, nbytes);
rc = nand_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2,
debug ("nand_legacy_rw(%p, %lx %x)\n", addr, start, nbytes);
rc = nand_legacy_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2,
start, nbytes, (size_t *)&total, (uchar *)addr);
debug ("nand_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes);
debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes);
#endif
}
if (rc != 0) {
@ -304,7 +309,7 @@ int au_do_update(int i, long sz)
rc = crc32 (0, (uchar *)(start + off), ntohl(hdr->ih_size));
} else {
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
rc = nand_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP,
rc = nand_legacy_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP,
start, nbytes, (size_t *)&total, (uchar *)addr);
rc = crc32 (0, (uchar *)(addr + off), ntohl(hdr->ih_size));
#endif

1
board/esd/common/cmd_loadpci.c
View File

@ -120,4 +120,3 @@ U_BOOT_CMD(
);
#endif

3
board/esd/cpci405/config.mk
View File

@ -38,3 +38,6 @@ TEXT_BASE = 0xFFFD0000
endif
endif
endif
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

1
board/esd/cpci750/cpci750.c
View File

@ -378,7 +378,6 @@ int misc_init_r ()
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[3]);
}
return 0;
}

3
board/esd/hh405/config.mk
View File

@ -29,3 +29,6 @@
TEXT_BASE = 0xFFF80000
#TEXT_BASE = 0xFFFC0000
#TEXT_BASE = 0x00FC0000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

2
board/esd/hh405/hh405.c
View File

@ -697,7 +697,7 @@ void ide_set_reset(int on)
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)

3
board/esd/hub405/config.mk
View File

@ -26,3 +26,6 @@
#
TEXT_BASE = 0xFFFC0000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

2
board/esd/hub405/hub405.c
View File

@ -265,7 +265,7 @@ int testdram (void)
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)

3
board/esd/plu405/config.mk
View File

@ -27,3 +27,6 @@
TEXT_BASE = 0xFFFC0000
#TEXT_BASE = 0x00FC0000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

2
board/esd/plu405/plu405.c
View File

@ -269,7 +269,7 @@ void ide_set_reset(int on)
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)

3
board/esd/voh405/config.mk
View File

@ -26,3 +26,6 @@
#
TEXT_BASE = 0xFFF80000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

2
board/esd/voh405/voh405.c
View File

@ -343,7 +343,7 @@ void ide_set_reset(int on)
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)

3
board/esd/wuh405/config.mk
View File

@ -26,3 +26,6 @@
#
TEXT_BASE = 0xFFFC0000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

2
board/esd/wuh405/wuh405.c
View File

@ -239,7 +239,7 @@ int testdram (void)
/* ------------------------------------------------------------------------- */
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)

2
board/g2000/g2000.c
View File

@ -185,7 +185,7 @@ int testdram (void)
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)

46
board/mcc200/Makefile Normal file
View File

@ -0,0 +1,46 @@
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := $(BOARD).o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

43
board/mcc200/config.mk Normal file
View File

@ -0,0 +1,43 @@
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# MCC200 board:
#
# Valid values for TEXT_BASE are:
#
# 0xFFF00000 boot high (standard configuration)
# 0xFE000000 boot low
# 0x00100000 boot from RAM (for testing only)
#
sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
## Standard: boot high
TEXT_BASE = 0xFFF00000
## For testing: boot from RAM
# TEXT_BASE = 0x00100000
endif
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board

276
board/mcc200/mcc200.c Normal file
View File

@ -0,0 +1,276 @@
/*
* (C) Copyright 2003-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
#include "mt48lc8m32b2-6-7.h"
extern flash_info_t flash_info[]; /* FLASH chips info */
ulong flash_get_size (ulong base, int banknum);
#ifndef CFG_RAMBOOT
static void sdram_start (int hi_addr)
{
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
/* unlock mode register */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
__asm__ volatile ("sync");
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set mode register: extended mode */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
__asm__ volatile ("sync");
/* set mode register: reset DLL */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
__asm__ volatile ("sync");
#endif
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
/* auto refresh */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
__asm__ volatile ("sync");
/* set mode register */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
__asm__ volatile ("sync");
/* normal operation */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
__asm__ volatile ("sync");
}
#endif
/*
* ATTENTION: Although partially referenced initdram does NOT make real use
* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
* is something else than 0x00000000.
*/
long int initdram (int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
#ifndef CFG_RAMBOOT
ulong test1, test2;
/* setup SDRAM chip selects */
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
__asm__ volatile ("sync");
/* setup config registers */
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set tap delay */
*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
__asm__ volatile ("sync");
#endif
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
sdram_start(1);
test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
} else {
dramsize = test2;
}
/* memory smaller than 1MB is impossible */
if (dramsize < (1 << 20)) {
dramsize = 0;
}
/* set SDRAM CS0 size according to the amount of RAM found */
if (dramsize > 0) {
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
} else {
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
}
/* let SDRAM CS1 start right after CS0 */
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
/* find RAM size using SDRAM CS1 only */
if (!dramsize)
sdram_start(0);
test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
if (!dramsize) {
sdram_start(1);
test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
}
if (test1 > test2) {
sdram_start(0);
dramsize2 = test1;
} else {
dramsize2 = test2;
}
/* memory smaller than 1MB is impossible */
if (dramsize2 < (1 << 20)) {
dramsize2 = 0;
}
/* set SDRAM CS1 size according to the amount of RAM found */
if (dramsize2 > 0) {
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
} else {
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
}
#else /* CFG_RAMBOOT */
/* retrieve size of memory connected to SDRAM CS0 */
dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
if (dramsize >= 0x13) {
dramsize = (1 << (dramsize - 0x13)) << 20;
} else {
dramsize = 0;
}
/* retrieve size of memory connected to SDRAM CS1 */
dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
if (dramsize2 >= 0x13) {
dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
} else {
dramsize2 = 0;
}
#endif /* CFG_RAMBOOT */
return dramsize + dramsize2;
}
int checkboard (void)
{
puts ("Board: MCC200\n");
return 0;
}
int misc_init_r (void)
{
DECLARE_GLOBAL_DATA_PTR;
/*
* Adjust flash start and offset to detected values
*/
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
/*
* Check if boot FLASH isn't max size
*/
if (gd->bd->bi_flashsize < (0 - CFG_FLASH_BASE)) {
/* adjust mapping */
*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
START_REG(gd->bd->bi_flashstart);
*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize);
/*
* Re-check to get correct base address
*/
flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
/*
* Re-do flash protection upon new addresses
*/
flash_protect (FLAG_PROTECT_CLEAR,
gd->bd->bi_flashstart, 0xffffffff,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
/* Monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
/* Environment protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
/* Redundant environment protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
}
return (0);
}
#ifdef CONFIG_PCI
static struct pci_controller hose;
extern void pci_mpc5xxx_init(struct pci_controller *);
void pci_init_board(void)
{
pci_mpc5xxx_init(&hose);
}
#endif
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
void init_ide_reset (void)
{
debug ("init_ide_reset\n");
}
void ide_set_reset (int idereset)
{
debug ("ide_reset(%d)\n", idereset);
}
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
#if (CONFIG_COMMANDS & CFG_CMD_DOC)
extern void doc_probe (ulong physadr);
void doc_init (void)
{
doc_probe (CFG_DOC_BASE);
}
#endif

37
board/mcc200/mt46v16m16-75.h Normal file
View File

@ -0,0 +1,37 @@
/*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define SDRAM_DDR 1 /* is DDR */
#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONTROL 0x714f0f00
#define SDRAM_CONFIG1 0x73722930
#define SDRAM_CONFIG2 0x47770000
#define SDRAM_TAPDELAY 0x10000000
#else
#error CONFIG_MPC5200 not defined
#endif

43
board/mcc200/mt48lc16m16a2-75.h Normal file
View File

@ -0,0 +1,43 @@
/*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define SDRAM_DDR 0 /* is SDR */
#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x00CD0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xD2322800
#define SDRAM_CONFIG2 0x8AD70000
#elif defined(CONFIG_MGT5100)
/* Settings for XLB = 66 MHz */
#define SDRAM_MODE 0x008D0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xC2222600
#define SDRAM_CONFIG2 0x88B70004
#define SDRAM_ADDRSEL 0x02000000
#else
#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
#endif

12
board/mcc200/mt48lc8m32b2-6-7.h Normal file
View File

@ -0,0 +1,12 @@
/*
* Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform
*/
#define SDRAM_DDR 0 /* is SDR */
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */
#define SDRAM_CONTROL 0x504f0000 /* Control Register MBAR + 0x0104 */
#define SDRAM_CONFIG1 0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */
#define SDRAM_CONFIG2 0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */

125
board/mcc200/u-boot.lds Normal file
View File

@ -0,0 +1,125 @@
/*
* (C) Copyright 2003-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc5xxx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

3
board/netphone/config.mk
View File

@ -26,3 +26,6 @@
#
TEXT_BASE = 0x40000000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

2
board/netphone/netphone.c
View File

@ -599,7 +599,7 @@ int board_early_init_f(void)
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern ulong nand_probe(ulong physadr);
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];

3
board/netstar/config.mk
View File

@ -10,6 +10,5 @@
# XXX TEXT_BASE = 0x20012000
TEXT_BASE = 0x13FC0000
# Compile the new NAND code (needed iff #ifdef CONFIG_NEW_NAND_CODE)
# Compile the new NAND code
BOARDLIBS = drivers/nand/libnand.a

4
board/netstar/setup.S
View File

@ -129,8 +129,8 @@ MUX_CONFIG_OFFSETS:
.byte 0x0c @ COMP_MODE_CTRL_0
.byte 0xff
.globl platformsetup
platformsetup:
.globl lowlevel_init
lowlevel_init:
/* Improve performance a bit... */
mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register
mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register

3
board/netta2/config.mk
View File

@ -26,3 +26,6 @@
#
TEXT_BASE = 0x40000000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

2
board/netta2/netta2.c
View File

@ -597,7 +597,7 @@ int board_early_init_f(void)
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern ulong nand_probe(ulong physadr);
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];

3
board/netvia/config.mk
View File

@ -26,3 +26,6 @@
#
TEXT_BASE = 0x40000000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

2
board/netvia/netvia.c
View File

@ -418,7 +418,7 @@ int board_early_init_f(void)
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern ulong nand_probe(ulong physadr);
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];

2
board/omap2420h4/omap2420h4.c
View File

@ -32,7 +32,7 @@
#include <i2c.h>
#include <asm/mach-types.h>
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
#endif

3
board/sixnet/config.mk
View File

@ -26,3 +26,6 @@
#
TEXT_BASE = 0xF8000000
# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

2
board/sixnet/sixnet.c
View File

@ -34,7 +34,7 @@
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
#endif

2
board/stxxtc/stxxtc.c
View File

@ -576,7 +576,7 @@ int board_early_init_f(void)
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
extern ulong nand_probe(ulong physadr);
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];

2
board/tqm85xx/tqm85xx.c
View File

@ -296,7 +296,7 @@ int misc_init_r (void)
/* Monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE, 0xffffffff,
CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
/* Environment protection ON by default */

14
board/zylonite/lowlevel_init.S
View File

@ -250,7 +250,7 @@ mem_init:
mov r6, #0
mov r7, #0
10: /* fastScrubLoop */
subs r9, r9, #32 // 32 bytes/line
subs r9, r9, #32 /* 32 bytes/line */
stmia r8!, {r0-r7}
beq 15f
b 10b
@ -262,19 +262,16 @@ mem_init:
/* Disable software and data breakpoints */
mov r0, #0
mcr p15,0,r0,c14,c8,0 // ibcr0
mcr p15,0,r0,c14,c9,0 // ibcr1
mcr p15,0,r0,c14,c4,0 // dbcon
mcr p15,0,r0,c14,c8,0 /* ibcr0 */
mcr p15,0,r0,c14,c9,0 /* ibcr1 */
mcr p15,0,r0,c14,c4,0 /* dbcon */
/* Enable all debug functionality */
mov r0,#0x80000000
mcr p14,0,r0,c10,c0,0 // dcsr
mcr p14,0,r0,c10,c0,0 /* dcsr */
/* We are finished with Intel's memory controller initialisation */
/* ---------------------------------------------------------------- */
/* End lowlevel_init */
/* ---------------------------------------------------------------- */
@ -283,7 +280,6 @@ endlowlevel_init:
mov pc, lr
/*
@********************************************************************************
@ DDR calibration

2
common/Makefile
View File

@ -37,7 +37,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o \
cmd_i2c.o cmd_ide.o cmd_immap.o cmd_itest.o cmd_jffs2.o \
cmd_load.o cmd_log.o \
cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \
cmd_nand.o cmd_nand_new.o cmd_net.o cmd_nvedit.o \
cmd_nand.o cmd_net.o cmd_nvedit.o \
cmd_pci.o cmd_pcmcia.o cmd_portio.o \
cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_universe.o \
cmd_usb.o cmd_vfd.o \

3
common/cmd_doc.c
View File

@ -22,8 +22,9 @@
#if (CONFIG_COMMANDS & CFG_CMD_DOC)
#include <linux/mtd/nftl.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_legacy.h>
#include <linux/mtd/nand_ids.h>
#include <linux/mtd/doc2000.h>
#include <linux/mtd/nftl.h>

17
common/cmd_jffs2.c
View File

@ -91,7 +91,6 @@
#include <command.h>
#include <malloc.h>
#include <jffs2/jffs2.h>
#include <linux/mtd/nand.h>
#include <linux/list.h>
#include <linux/ctype.h>
@ -99,10 +98,14 @@
#include <cramfs/cramfs_fs.h>
#ifdef CONFIG_NEW_NAND_CODE
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#ifdef CFG_NAND_LEGACY
#include <linux/mtd/nand_legacy.h>
#else /* !CFG_NAND_LEGACY */
#include <linux/mtd/nand.h>
#include <nand.h>
#endif
#endif /* !CFG_NAND_LEGACY */
#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
/* enable/disable debugging messages */
#define DEBUG_JFFS
#undef DEBUG_JFFS
@ -467,7 +470,7 @@ static int part_del(struct mtd_device *dev, struct part_info *part)
}
}
#ifndef CONFIG_NEW_NAND_CODE
#ifdef CFG_NAND_LEGACY
jffs2_free_cache(part);
#endif
list_del(&part->link);
@ -496,7 +499,7 @@ static void part_delall(struct list_head *head)
list_for_each_safe(entry, n, head) {
part_tmp = list_entry(entry, struct part_info, link);
#ifndef CONFIG_NEW_NAND_CODE
#ifdef CFG_NAND_LEGACY
jffs2_free_cache(part_tmp);
#endif
list_del(entry);
@ -732,7 +735,7 @@ static int device_validate(u8 type, u8 num, u32 *size)
} else if (type == MTD_DEV_TYPE_NAND) {
#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND)
if (num < CFG_MAX_NAND_DEVICE) {
#ifdef CONFIG_NEW_NAND_CODE
#ifndef CFG_NAND_LEGACY
*size = nand_info[num].size;
#else
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];

1955
common/cmd_nand.c
View File

File diff suppressed because it is too large Load Diff

364
common/cmd_nand_new.c
View File

@ -1,364 +0,0 @@
#include <common.h>
#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined CONFIG_NEW_NAND_CODE
#include <command.h>
#include <watchdog.h>
#include <malloc.h>
#include <asm/byteorder.h>
#ifdef CONFIG_SHOW_BOOT_PROGRESS
# include <status_led.h>
# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
#else
# define SHOW_BOOT_PROGRESS(arg)
#endif
#include <jffs2/jffs2.h>
#include <nand.h>
extern nand_info_t nand_info[]; /* info for NAND chips */
static int nand_dump_oob(nand_info_t *nand, ulong off)
{
return 0;
}
static int nand_dump(nand_info_t *nand, ulong off)
{
int i;
u_char *buf, *p;
buf = malloc(nand->oobblock + nand->oobsize);
if (!buf) {
puts("No memory for page buffer\n");
return 1;
}
off &= ~(nand->oobblock - 1);
i = nand_read_raw(nand, buf, off, nand->oobblock, nand->oobsize);
if (i < 0) {
printf("Error (%d) reading page %08x\n", i, off);
free(buf);
return 1;
}
printf("Page %08x dump:\n", off);
i = nand->oobblock >> 4; p = buf;
while (i--) {
printf( "\t%02x %02x %02x %02x %02x %02x %02x %02x"
" %02x %02x %02x %02x %02x %02x %02x %02x\n",
p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],
p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15]);
p += 16;
}
puts("OOB:\n");
i = nand->oobsize >> 3;
while (i--) {
printf( "\t%02x %02x %02x %02x %02x %02x %02x %02x\n",
p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
p += 8;
}
free(buf);
return 0;
}
/* ------------------------------------------------------------------------- */
static void
arg_off_size(int argc, char *argv[], ulong *off, ulong *size, ulong totsize)
{
*off = 0;
*size = 0;
#if defined(CONFIG_JFFS2_NAND) && defined(CFG_JFFS_CUSTOM_PART)
if (argc >= 1 && strcmp(argv[0], "partition") == 0) {
int part_num;
struct part_info *part;
const char *partstr;
if (argc >= 2)
partstr = argv[1];
else
partstr = getenv("partition");
if (partstr)
part_num = (int)simple_strtoul(partstr, NULL, 10);
else
part_num = 0;
part = jffs2_part_info(part_num);
if (part == NULL) {
printf("\nInvalid partition %d\n", part_num);
return;
}
*size = part->size;
*off = (ulong)part->offset;
} else
#endif
{
if (argc >= 1)
*off = (ulong)simple_strtoul(argv[0], NULL, 16);
else
*off = 0;
if (argc >= 2)
*size = (ulong)simple_strtoul(argv[1], NULL, 16);
else
*size = totsize - *off;
}
}
int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
int i, dev, ret;
ulong addr, off, size;
char *cmd, *s;
nand_info_t *nand;
/* at least two arguments please */
if (argc < 2)
goto usage;
cmd = argv[1];
if (strcmp(cmd, "info") == 0) {
putc('\n');
for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) {
if (nand_info[i].name)
printf("Device %d: %s\n", i, nand_info[i].name);
}
return 0;
}
if (strcmp(cmd, "device") == 0) {
if (argc < 3) {
if ((nand_curr_device < 0) ||
(nand_curr_device >= CFG_MAX_NAND_DEVICE))
puts("\nno devices available\n");
else
printf("\nDevice %d: %s\n", nand_curr_device,
nand_info[nand_curr_device].name);
return 0;
}
dev = (int)simple_strtoul(argv[2], NULL, 10);
if (dev < 0 || dev >= CFG_MAX_NAND_DEVICE || !nand_info[dev].name) {
puts("No such device\n");
return 1;
}
printf("Device %d: %s", dev, nand_info[dev].name);
puts("... is now current device\n");
nand_curr_device = dev;
return 0;
}
if (strcmp(cmd, "bad") != 0 && strcmp(cmd, "erase") != 0 &&
strncmp(cmd, "dump", 4) != 0 &&
strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0)
goto usage;
/* the following commands operate on the current device */
if (nand_curr_device < 0 || nand_curr_device >= CFG_MAX_NAND_DEVICE ||
!nand_info[nand_curr_device].name) {
puts("\nno devices available\n");
return 1;
}
nand = &nand_info[nand_curr_device];
if (strcmp(cmd, "bad") == 0) {
printf("\nDevice %d bad blocks:\n", nand_curr_device);
for (off = 0; off < nand->size; off += nand->erasesize)
if (nand_block_isbad(nand, off))
printf(" %08x\n", off);
return 0;
}
if (strcmp(cmd, "erase") == 0) {
arg_off_size(argc - 2, argv + 2, &off, &size, nand->size);
if (off == 0 && size == 0)
return 1;
printf("\nNAND erase: device %d offset 0x%x, size 0x%x ",
nand_curr_device, off, size);
ret = nand_erase(nand, off, size);
printf("%s\n", ret ? "ERROR" : "OK");
return ret == 0 ? 0 : 1;
}
if (strncmp(cmd, "dump", 4) == 0) {
if (argc < 3)
goto usage;
s = strchr(cmd, '.');
off = (int)simple_strtoul(argv[2], NULL, 16);
if (s != NULL && strcmp(s, ".oob") == 0)
ret = nand_dump_oob(nand, off);
else
ret = nand_dump(nand, off);
return ret == 0 ? 1 : 0;
}
/* read write */
if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) {
if (argc < 4)
goto usage;
/*
s = strchr(cmd, '.');
clean = CLEAN_NONE;
if (s != NULL) {
if (strcmp(s, ".jffs2") == 0 || strcmp(s, ".e") == 0
|| strcmp(s, ".i"))
clean = CLEAN_JFFS2;
}
*/
addr = (ulong)simple_strtoul(argv[2], NULL, 16);
arg_off_size(argc - 3, argv + 3, &off, &size, nand->size);
if (off == 0 && size == 0)
return 1;
i = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */
printf("\nNAND %s: device %d offset %u, size %u ... ",
i ? "read" : "write", nand_curr_device, off, size);
if (i)
ret = nand_read(nand, off, &size, (u_char *)addr);
else
ret = nand_write(nand, off, &size, (u_char *)addr);
printf(" %d bytes %s: %s\n", size,
i ? "read" : "written", ret ? "ERROR" : "OK");
return ret == 0 ? 0 : 1;
}
usage:
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
U_BOOT_CMD(nand, 5, 1, do_nand,
"nand - NAND sub-system\n",
"info - show available NAND devices\n"
"nand device [dev] - show or set current device\n"
"nand read[.jffs2] - addr off size\n"
"nand write[.jffs2] - addr off size - read/write `size' bytes starting\n"
" at offset `off' to/from memory address `addr'\n"
"nand erase [clean] [off size] - erase `size' bytes from\n"
" offset `off' (entire device if not specified)\n"
"nand bad - show bad blocks\n"
"nand dump[.oob] off - dump page\n"
"nand scrub - really clean NAND erasing bad blocks (UNSAFE)\n"
"nand markbad off - mark bad block at offset (UNSAFE)\n"
"nand biterr off - make a bit error at offset (UNSAFE)\n");
int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
char *boot_device = NULL;
char *ep;
int dev;
int r;
ulong addr, cnt, offset = 0;
image_header_t *hdr;
nand_info_t *nand;
switch (argc) {
case 1:
addr = CFG_LOAD_ADDR;
boot_device = getenv("bootdevice");
break;
case 2:
addr = simple_strtoul(argv[1], NULL, 16);
boot_device = getenv("bootdevice");
break;
case 3:
addr = simple_strtoul(argv[1], NULL, 16);
boot_device = argv[2];
break;
case 4:
addr = simple_strtoul(argv[1], NULL, 16);
boot_device = argv[2];
offset = simple_strtoul(argv[3], NULL, 16);
break;
default:
printf("Usage:\n%s\n", cmdtp->usage);
SHOW_BOOT_PROGRESS(-1);
return 1;
}
if (!boot_device) {
puts("\n** No boot device **\n");
SHOW_BOOT_PROGRESS(-1);
return 1;
}
dev = simple_strtoul(boot_device, &ep, 16);
if (dev < 0 || dev >= CFG_MAX_NAND_DEVICE || !nand_info[dev].name) {
printf("\n** Device %d not available\n", dev);
SHOW_BOOT_PROGRESS(-1);
return 1;
}
nand = &nand_info[dev];
printf("\nLoading from device %d: %s (offset 0x%lx)\n",
dev, nand->name, offset);
cnt = nand->oobblock;
r = nand_read(nand, offset, &cnt, (u_char *) addr);
if (r) {
printf("** Read error on %d\n", dev);
SHOW_BOOT_PROGRESS(-1);
return 1;
}
hdr = (image_header_t *) addr;
if (ntohl(hdr->ih_magic) != IH_MAGIC) {
printf("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic);
SHOW_BOOT_PROGRESS(-1);
return 1;
}
print_image_hdr(hdr);
cnt = (ntohl(hdr->ih_size) + sizeof (image_header_t));
r = nand_read(nand, offset, &cnt, (u_char *) addr);
if (r) {
printf("** Read error on %d\n", dev);
SHOW_BOOT_PROGRESS(-1);
return 1;
}
/* Loading ok, update default load address */
load_addr = addr;
/* Check if we should attempt an auto-start */
if (((ep = getenv("autostart")) != NULL) && (strcmp(ep, "yes") == 0)) {
char *local_args[2];
extern int do_bootm(cmd_tbl_t *, int, int, char *[]);
local_args[0] = argv[0];
local_args[1] = NULL;
printf("Automatic boot of image at addr 0x%08lx ...\n", addr);
do_bootm(cmdtp, 0, 1, local_args);
return 1;
}
return 0;
}
U_BOOT_CMD(nboot, 4, 1, do_nandboot,
"nboot - boot from NAND device\n", "loadAddr dev\n");
#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */

37
common/env_nand.c
View File

@ -36,7 +36,7 @@
#include <command.h>
#include <environment.h>
#include <linux/stddef.h>
#include <linux/mtd/nand.h>
#include <nand.h>
#if ((CONFIG_COMMANDS&(CFG_CMD_ENV|CFG_CMD_NAND)) == (CFG_CMD_ENV|CFG_CMD_NAND))
#define CMD_SAVEENV
@ -55,16 +55,12 @@
#error CONFIG_INFERNO not supported yet
#endif
/* references to names in cmd_nand.c */
#define NANDRW_READ 0x01
#define NANDRW_WRITE 0x00
#define NANDRW_JFFS2 0x02
extern struct nand_chip nand_dev_desc[];
int nand_rw (struct nand_chip* nand, int cmd,
int nand_legacy_rw (struct nand_chip* nand, int cmd,
size_t start, size_t len,
size_t * retlen, u_char * buf);
int nand_erase(struct nand_chip* nand, size_t ofs,
size_t len, int clean);
/* info for NAND chips, defined in drivers/nand/nand.c */
extern nand_info_t nand_info[];
/* references to names in env_common.c */
extern uchar default_environment[];
@ -110,17 +106,22 @@ int env_init(void)
}
#ifdef CMD_SAVEENV
/*
* The legacy NAND code saved the environment in the first NAND device i.e.,
* nand_dev_desc + 0. This is also the behaviour using the new NAND code.
*/
int saveenv(void)
{
int total, ret = 0;
puts ("Erasing Nand...");
if (nand_erase(nand_dev_desc + 0, CFG_ENV_OFFSET, CFG_ENV_SIZE, 0))
if (nand_erase(&nand_info[0], CFG_NEW_OFFSET, CFG_ENV_SIZE))
return 1;
puts ("Writing to Nand... ");
ret = nand_rw(nand_dev_desc + 0,
NANDRW_WRITE | NANDRW_JFFS2, CFG_ENV_OFFSET, CFG_ENV_SIZE,
&total, (u_char*)env_ptr);
total = CFG_ENV_SIZE;
ret = nand_write(&nand_info[0], CFG_ENV_OFFSET, &total,
(u_char*) env_ptr);
if (ret || total != CFG_ENV_SIZE)
return 1;
@ -130,14 +131,18 @@ int saveenv(void)
#endif /* CMD_SAVEENV */
/*
* The legacy NAND code saved the environment in the first NAND device i.e.,
* nand_dev_desc + 0. This is also the behaviour using the new NAND code.
*/
void env_relocate_spec (void)
{
#if !defined(ENV_IS_EMBEDDED)
int ret, total;
ret = nand_rw(nand_dev_desc + 0,
NANDRW_READ | NANDRW_JFFS2, CFG_ENV_OFFSET, CFG_ENV_SIZE,
&total, (u_char*)env_ptr);
total = CFG_ENV_SIZE;
ret = nand_read(&nand_info[0], CFG_ENV_OFFSET, &total,
(u_char*) env_ptr);
if (ret || total != CFG_ENV_SIZE)
return use_default();

3
cpu/mpc5xxx/fec.c
View File

@ -880,8 +880,9 @@ int mpc5xxx_fec_initialize(bd_t * bis)
fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
#if defined(CONFIG_CANMB) || defined(CONFIG_HMI1001) || \
defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \
defined(CONFIG_MCC200) || defined(CONFIG_O2DNT) || \
defined(CONFIG_PM520) || defined(CONFIG_TOP5200) || \
defined(CONFIG_TQM5200) || defined(CONFIG_O2DNT)
defined(CONFIG_TQM5200)
# ifndef CONFIG_FEC_10MBIT
fec->xcv_type = MII100;
# else

1
cpu/pxa/cpu.c
View File

@ -162,4 +162,3 @@ void set_GPIO_mode(int gpio_mode)
GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2));
}
#endif /* CONFIG_CPU_MONAHANS */

6
cpu/pxa/start.S
View File

@ -198,7 +198,6 @@ cpuspeed: .word CFG_CPUSPEED
#error "You have to define CFG_CPUSPEED!!"
#endif
/* takes care the CP15 update has taken place */
.macro CPWAIT reg
mrc p15,0,\reg,c2,c0,0
@ -206,12 +205,10 @@ cpuspeed: .word CFG_CPUSPEED
sub pc,pc,#4
.endm
cpu_init_crit:
/* mask all IRQs */
#ifndef CONFIG_CPU_MONAHANS
ldr r0, IC_BASE
mov r1, #0x00
str r1, [r0, #ICMR]
@ -234,12 +231,10 @@ cpu_init_crit:
ldr r1, =CKENB
ldr r2, =(CKENB_6_IRQ)
str r2, [r1]
#endif
#ifndef CONFIG_CPU_MONAHANS
#ifdef CFG_CPUSPEED
/* set clock speed tbd@mk: required for monahans? */
ldr r0, CC_BASE
ldr r1, cpuspeed
@ -252,7 +247,6 @@ setspeed_done:
#endif /* CFG_CPUSPEED */
#endif /* CONFIG_CPU_MONAHANS */
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will

34
doc/README.nand
View File

@ -1,5 +1,9 @@
NAND FLASH commands and notes
See NOTE below!!!
# (C) Copyright 2003
# Dave Ellis, SIXNET, dge@sixnetio.com
#
@ -173,3 +177,33 @@ More Definitions:
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
NOTE:
=====
We now use a complete rewrite of the NAND code based on what is in
2.6.12 Linux kernel.
The old NAND handling code has been re-factored and is now confined
to only board-specific files and - unfortunately - to the DoC code
(see below). A new configuration variable has been introduced:
CFG_NAND_LEGACY, which has to be defined in the board config file if
that board uses legacy code. If CFG_NAND_LEGACY is defined, the board
specific config.mk file should also have "BOARDLIBS =
drivers/nand_legacy/libnand_legacy.a". For boards using the new NAND
approach (PPChameleon and netstar at the moment) no variable is
necessary, but the config.mk should have "BOARDLIBS =
drivers/nand/libnand.a".
The necessary changes have been made to all affected boards, and no
build breakage has been introduced, except for NETTA and NETTA_ISDN
targets from MAKEALL. This is due to the fact that these two boards
use JFFS, which has been adopted to use the new NAND, and at the same
time use NAND in legacy mode. The breakage will disappear when the
board-specific code is changed to the new NAND.
As mentioned above, the legacy code is still used by the DoC subsystem.
The consequence of this is that the legacy NAND can't be removed from
the tree until the DoC is ported to use the new NAND support (or boards
with DoC will break).

156
drivers/cfi_flash.c
View File

@ -104,12 +104,15 @@
#define AMD_CMD_ERASE_SECTOR 0x30
#define AMD_CMD_UNLOCK_START 0xAA
#define AMD_CMD_UNLOCK_ACK 0x55
#define AMD_CMD_WRITE_TO_BUFFER 0x25
#define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29
#define AMD_STATUS_TOGGLE 0x40
#define AMD_STATUS_ERROR 0x20
#define AMD_ADDR_ERASE_START 0x555
#define AMD_ADDR_START 0x555
#define AMD_ADDR_ACK 0x2AA
#define AMD_ADDR_ERASE_START ((info->portwidth == FLASH_CFI_8BIT) ? 0xAAA : 0x555)
#define AMD_ADDR_START ((info->portwidth == FLASH_CFI_8BIT) ? 0xAAA : 0x555)
#define AMD_ADDR_ACK ((info->portwidth == FLASH_CFI_8BIT) ? 0x555 : 0x2AA)
#define FLASH_OFFSET_CFI 0x55
#define FLASH_OFFSET_CFI_RESP 0x10
@ -175,6 +178,13 @@ static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* FLASH chips info */
#endif
/*
* Check if chip width is defined. If not, start detecting with 8bit.
*/
#ifndef CFG_FLASH_CFI_WIDTH
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
#endif
/*-----------------------------------------------------------------------
* Functions
@ -190,10 +200,10 @@ static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, u
static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
static int flash_detect_cfi (flash_info_t * info);
ulong flash_get_size (ulong base, int banknum);
static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
ulong tout, char *prompt);
ulong flash_get_size (ulong base, int banknum);
#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
static flash_info_t *flash_get_info(ulong base);
#endif
@ -328,6 +338,7 @@ ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
return retval;
}
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
@ -345,6 +356,24 @@ unsigned long flash_init (void)
i, flash_info[i].size, flash_info[i].size << 20);
#endif /* CFG_FLASH_QUIET_TEST */
}
#ifdef CFG_FLASH_PROTECTION
else {
char *s = getenv("unlock");
if (((s = getenv("unlock")) != NULL) && (strcmp(s, "yes") == 0)) {
/*
* Only the U-Boot image and it's environment is protected,
* all other sectors are unprotected (unlocked) if flash
* hardware protection is used (CFG_FLASH_PROTECTION) and
* the environment variable "unlock" is set to "yes".
*/
flash_protect (FLAG_PROTECT_CLEAR,
flash_info[i].start[0],
flash_info[i].start[0] + flash_info[i].size - 1,
&flash_info[i]);
}
}
#endif /* CFG_FLASH_PROTECTION */
}
/* Monitor protection ON by default */
@ -565,7 +594,22 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
buffered_size = (info->portwidth / info->chipwidth);
buffered_size *= info->buffer_size;
while (cnt >= info->portwidth) {
i = buffered_size > cnt ? cnt : buffered_size;
/* prohibit buffer write when buffer_size is 1 */
if (info->buffer_size == 1) {
cword.l = 0;
for (i = 0; i < info->portwidth; i++)
flash_add_byte (info, &cword, *src++);
if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
return rc;
wp += info->portwidth;
cnt -= info->portwidth;
continue;
}
/* write buffer until next buffered_size aligned boundary */
i = buffered_size - (wp % buffered_size);
if (i > cnt)
i = cnt;
if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
return rc;
i -= i & (info->portwidth - 1);
@ -705,7 +749,7 @@ static int flash_status_check (flash_info_t * info, flash_sect_t sector,
/* Wait for command completion */
start = get_timer (0);
while (flash_is_busy (info, sector)) {
if (get_timer (start) > info->erase_blk_tout * CFG_HZ) {
if (get_timer (start) > tout) {
printf ("Flash %s timeout at address %lx data %lx\n",
prompt, info->start[sector],
flash_read_long (info, sector, 0));
@ -729,7 +773,7 @@ static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
switch (info->vendor) {
case CFI_CMDSET_INTEL_EXTENDED:
case CFI_CMDSET_INTEL_STANDARD:
if ((retcode != ERR_OK)
if ((retcode == ERR_OK)
&& !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
retcode = ERR_INVAL;
printf ("Flash %s error at address %lx\n", prompt,
@ -985,7 +1029,7 @@ static int flash_detect_cfi (flash_info_t * info)
{
debug ("flash detect cfi\n");
for (info->portwidth = FLASH_CFI_8BIT;
for (info->portwidth = CFG_FLASH_CFI_WIDTH;
info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
for (info->chipwidth = FLASH_CFI_BY8;
info->chipwidth <= info->portwidth;
@ -1106,8 +1150,9 @@ ulong flash_get_size (ulong base, int banknum)
info->erase_blk_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT)));
tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT);
info->buffer_write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)));
tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT);
info->write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT))) / 1000;
tmp = (1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT)) *
(1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT));
info->write_tout = tmp / 1000 + (tmp % 1000 ? 1 : 0); /* round up when converting to ms */
info->flash_id = FLASH_MAN_CFI;
if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) {
info->portwidth >>= 1; /* XXX - Need to test on x8/x16 in parallel. */
@ -1118,13 +1163,26 @@ ulong flash_get_size (ulong base, int banknum)
return (info->size);
}
/* loop through the sectors from the highest address
* when the passed address is greater or equal to the sector address
* we have a match
*/
static flash_sect_t find_sector (flash_info_t * info, ulong addr)
{
flash_sect_t sector;
for (sector = info->sector_count - 1; sector >= 0; sector--) {
if (addr >= info->start[sector])
break;
}
return sector;
}
/*-----------------------------------------------------------------------
*/
static int flash_write_cfiword (flash_info_t * info, ulong dest,
cfiword_t cword)
{
cfiptr_t ctladdr;
cfiptr_t cptr;
int flag;
@ -1188,26 +1246,12 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest,
if (flag)
enable_interrupts ();
return flash_full_status_check (info, 0, info->write_tout, "write");
return flash_full_status_check (info, find_sector (info, dest),
info->write_tout, "write");
}
#ifdef CFG_FLASH_USE_BUFFER_WRITE
/* loop through the sectors from the highest address
* when the passed address is greater or equal to the sector address
* we have a match
*/
static flash_sect_t find_sector (flash_info_t * info, ulong addr)
{
flash_sect_t sector;
for (sector = info->sector_count - 1; sector >= 0; sector--) {
if (addr >= info->start[sector])
break;
}
return sector;
}
static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
int len)
{
@ -1216,18 +1260,16 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
int retcode;
volatile cfiptr_t src;
volatile cfiptr_t dst;
/* buffered writes in the AMD chip set is not supported yet */
if((info->vendor == CFI_CMDSET_AMD_STANDARD) ||
(info->vendor == CFI_CMDSET_AMD_EXTENDED))
return ERR_INVAL;
switch (info->vendor) {
case CFI_CMDSET_INTEL_STANDARD:
case CFI_CMDSET_INTEL_EXTENDED:
src.cp = cp;
dst.cp = (uchar *) dest;
sector = find_sector (info, dest);
flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
if ((retcode =
flash_status_check (info, sector, info->buffer_write_tout,
if ((retcode = flash_status_check (info, sector, info->buffer_write_tout,
"write to buffer")) == ERR_OK) {
/* reduce the number of loops by the width of the port */
switch (info->portwidth) {
@ -1269,13 +1311,55 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
}
flash_write_cmd (info, sector, 0,
FLASH_CMD_WRITE_BUFFER_CONFIRM);
retcode =
flash_full_status_check (info, sector,
retcode = flash_full_status_check (info, sector,
info->buffer_write_tout,
"buffer write");
}
flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
return retcode;
case CFI_CMDSET_AMD_STANDARD:
case CFI_CMDSET_AMD_EXTENDED:
src.cp = cp;
dst.cp = (uchar *) dest;
sector = find_sector (info, dest);
flash_unlock_seq(info,0);
flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_TO_BUFFER);
switch (info->portwidth) {
case FLASH_CFI_8BIT:
cnt = len;
flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
while (cnt-- > 0) *dst.cp++ = *src.cp++;
break;
case FLASH_CFI_16BIT:
cnt = len >> 1;
flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
while (cnt-- > 0) *dst.wp++ = *src.wp++;
break;
case FLASH_CFI_32BIT:
cnt = len >> 2;
flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
while (cnt-- > 0) *dst.lp++ = *src.lp++;
break;
case FLASH_CFI_64BIT:
cnt = len >> 3;
flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
while (cnt-- > 0) *dst.llp++ = *src.llp++;
break;
default:
return ERR_INVAL;
}
flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM);
retcode = flash_full_status_check (info, sector, info->buffer_write_tout,
"buffer write");
return retcode;
default:
debug ("Unknown Command Set\n");
return ERR_INVAL;
}
}
#endif /* CFG_FLASH_USE_BUFFER_WRITE */
#endif /* CFG_FLASH_CFI */

7
drivers/nand/diskonchip.c
View File

@ -20,7 +20,11 @@
*/
#include <common.h>
#ifdef CONFIG_NEW_NAND_CODE
#ifdef CFG_NAND_LEGACY
#error CFG_NAND_LEGACY defined in a file not using the legacy NAND support!
#endif
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/sched.h>
@ -1782,4 +1786,3 @@ module_exit(cleanup_nanddoc);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
MODULE_DESCRIPTION("M-Systems DiskOnChip 2000, Millennium and Millennium Plus device driver\n");
#endif /* CONFIG_NEW_NAND_CODE */

7
drivers/nand/nand.c
View File

@ -23,7 +23,10 @@
#include <common.h>
#ifdef CONFIG_NEW_NAND_CODE
#ifdef CFG_NAND_LEGACY
#error CFG_NAND_LEGACY defined in a file not using the legacy NAND support!
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <nand.h>
@ -72,5 +75,3 @@ void nand_init(void)
}
#endif
#endif /* CONFIG_NEW_NAND_CODE */

11
drivers/nand/nand_base.c
View File

@ -71,7 +71,10 @@
#endif
#include <common.h>
#ifdef CONFIG_NEW_NAND_CODE
#ifdef CFG_NAND_LEGACY
#error CFG_NAND_LEGACY defined in a file not using the legacy NAND support!
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
@ -864,10 +867,10 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
break;
}
}
/* XXX nand device 1 on dave (PPChameleonEVB) needs more time */
#ifdef PPCHAMELON_NAND_TIMER_HACK
reset_timer();
while (get_timer(0) < 10);
#endif /* PPCHAMELON_NAND_TIMER_HACK */
return this->read_byte(mtd);
}
@ -2663,5 +2666,3 @@ void nand_release (struct mtd_info *mtd)
}
#endif
#endif /* CONFIG_NEW_NAND_CODE */

7
drivers/nand/nand_bbt.c
View File

@ -54,7 +54,10 @@
#include <common.h>
#ifdef CONFIG_NEW_NAND_CODE
#ifdef CFG_NAND_LEGACY
#error CFG_NAND_LEGACY defined in a file not using the legacy NAND support!
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <malloc.h>
@ -1051,5 +1054,3 @@ int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt)
}
#endif
#endif /* CONFIG_NEW_NAND_CODE */

7
drivers/nand/nand_ecc.c
View File

@ -37,7 +37,10 @@
#include <common.h>
#ifdef CONFIG_NEW_NAND_CODE
#ifdef CFG_NAND_LEGACY
#error CFG_NAND_LEGACY defined in a file not using the legacy NAND support!
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include<linux/mtd/mtd.h>
@ -243,5 +246,3 @@ int nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_cha
}
#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */
#endif /* CONFIG_NEW_NAND_CODE */

7
drivers/nand/nand_ids.c
View File

@ -13,7 +13,10 @@
#include <common.h>
#ifdef CONFIG_NEW_NAND_CODE
#ifdef CFG_NAND_LEGACY
#error CFG_NAND_LEGACY defined in a file not using the legacy NAND support!
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
@ -127,5 +130,3 @@ struct nand_manufacturers nand_manuf_ids[] = {
{0x0, "Unknown"}
};
#endif
#endif /* CONFIG_NEW_NAND_CODE */

16
drivers/nand_legacy/Makefile Normal file
View File

@ -0,0 +1,16 @@
include $(TOPDIR)/config.mk
LIB := libnand_legacy.a
OBJS := nand_legacy.o
all: $(LIB)
$(LIB): $(OBJS)
$(AR) crv $@ $(OBJS)
#########################################################################
.depend: Makefile $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
sinclude .depend

1615
drivers/nand_legacy/nand_legacy.c Normal file
View File

File diff suppressed because it is too large Load Diff

24
fs/jffs2/jffs2_1pass.c
View File

@ -143,7 +143,8 @@
/* keeps pointer to currentlu processed partition */
static struct part_info *current_part;
#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CONFIG_NEW_NAND_CODE)
#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <nand.h>
/*
* Support for jffs2 on top of NAND-flash
*
@ -154,9 +155,8 @@ static struct part_info *current_part;
*
*/
/* this one defined in cmd_nand.c */
int read_jffs2_nand(size_t start, size_t len,
size_t * retlen, u_char * buf, int nanddev);
/* info for NAND chips, defined in drivers/nand/nand.c */
extern nand_info_t nand_info[];
#define NAND_PAGE_SIZE 512
#define NAND_PAGE_SHIFT 9
@ -167,6 +167,7 @@ int read_jffs2_nand(size_t start, size_t len,
#endif
#define NAND_CACHE_SIZE (NAND_CACHE_PAGES*NAND_PAGE_SIZE)
#ifdef CFG_NAND_LEGACY
static u8* nand_cache = NULL;
static u32 nand_cache_off = (u32)-1;
@ -174,7 +175,7 @@ static int read_nand_cached(u32 off, u32 size, u_char *buf)
{
struct mtdids *id = current_part->dev->id;
u32 bytes_read = 0;
size_t retlen;
ulong retlen;
int cpy_bytes;
while (bytes_read < size) {
@ -191,8 +192,10 @@ static int read_nand_cached(u32 off, u32 size, u_char *buf)
return -1;
}
}
if (read_jffs2_nand(nand_cache_off, NAND_CACHE_SIZE,
&retlen, nand_cache, id->num) < 0 ||
retlen = NAND_CACHE_SIZE;
if (nand_read(&nand_info[id->num], nand_cache_off,
&retlen, nand_cache) != 0 ||
retlen != NAND_CACHE_SIZE) {
printf("read_nand_cached: error reading nand off %#x size %d bytes\n",
nand_cache_off, NAND_CACHE_SIZE);
@ -248,6 +251,7 @@ static void put_fl_mem_nand(void *buf)
{
free(buf);
}
#endif /* CFG_NAND_LEGACY */
#endif /* #if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) */
@ -290,7 +294,7 @@ static inline void *get_fl_mem(u32 off, u32 size, void *ext_buf)
return get_fl_mem_nor(off);
#endif
#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CONFIG_NEW_NAND_CODE)
#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
if (id->type == MTD_DEV_TYPE_NAND)
return get_fl_mem_nand(off, size, ext_buf);
#endif
@ -308,7 +312,7 @@ static inline void *get_node_mem(u32 off)
return get_node_mem_nor(off);
#endif
#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CONFIG_NEW_NAND_CODE)
#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
if (id->type == MTD_DEV_TYPE_NAND)
return get_node_mem_nand(off);
#endif
@ -319,7 +323,7 @@ static inline void *get_node_mem(u32 off)
static inline void put_fl_mem(void *buf)
{
#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CONFIG_NEW_NAND_CODE)
#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
struct mtdids *id = current_part->dev->id;
if (id->type == MTD_DEV_TYPE_NAND)

2
fs/jffs2/jffs2_nand_1pass.c
View File

@ -1,6 +1,6 @@
#include <common.h>
#if defined(CONFIG_NEW_NAND_CODE) && (CONFIG_COMMANDS & CFG_CMD_JFFS2)
#if !defined(CFG_NAND_LEGACY) && (CONFIG_COMMANDS & CFG_CMD_JFFS2)
#include <malloc.h>
#include <linux/stat.h>

2
include/asm-arm/arch-pxa/pxa-regs.h
View File

@ -2059,8 +2059,6 @@ typedef void (*ExcpHndlr) (void) ;
#define MDCNFG_DCSE0 0x1 /* SDRAM CS 0 Enable */
/* Data Flash Controller Registers */
#define NDCR __REG(0x43100000) /* Data Flash Control register */

3
include/configs/ASH405.h
View File

@ -132,6 +132,9 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_NAND_LEGACY
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512

4
include/configs/BMW.h
View File

@ -69,6 +69,10 @@
CFG_CMD_DOC | \
CFG_CMD_ELF | \
0 )
/* CFG_CMD_DOC required legacy NAND support */
#define CFG_NAND_LEGACY
#if 0
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | \
CFG_CMD_PCI | CFG_CMD_DOC | CFG_CMD_DATE)

2
include/configs/CMS700.h
View File

@ -81,6 +81,8 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */

2
include/configs/CPCI405.h
View File

@ -79,6 +79,8 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */

2
include/configs/CPCI4052.h
View File

@ -100,6 +100,8 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */

3
include/configs/CPCI405AB.h
View File

@ -87,6 +87,9 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */

2
include/configs/CPCI405DT.h
View File

@ -98,6 +98,8 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */

2
include/configs/CPU86.h
View File

@ -178,6 +178,8 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
/*
* Miscellaneous configurable options
*/

2
include/configs/CPU87.h
View File

@ -189,6 +189,8 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
/*
* Miscellaneous configurable options
*/

2
include/configs/GEN860T.h
View File

@ -284,6 +284,8 @@
*/
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
/*
* Verbose help from command monitor.
*/

2
include/configs/HH405.h
View File

@ -130,6 +130,8 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
#undef CONFIG_BZIP2 /* include support for bzip2 compressed images */
#undef CONFIG_WATCHDOG /* watchdog disabled */

2
include/configs/HUB405.h
View File

@ -135,6 +135,8 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_NAND_LEGACY
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512

2
include/configs/MIP405.h
View File

@ -87,6 +87,8 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
/**************************************************************

1
include/configs/NETPHONE.h
View File

@ -491,6 +491,7 @@
/****************************************************************/
/* NAND */
#define CFG_NAND_LEGACY
#define CFG_NAND_BASE NAND_BASE
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CONFIG_MTD_NAND_VERIFY_WRITE

1
include/configs/NETTA2.h
View File

@ -491,6 +491,7 @@
/****************************************************************/
/* NAND */
#define CFG_NAND_LEGACY
#define CFG_NAND_BASE NAND_BASE
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CONFIG_MTD_NAND_VERIFY_WRITE

2
include/configs/NETVIA.h
View File

@ -387,6 +387,8 @@
/*****************************************************************************/
#define CFG_NAND_LEGACY
#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
/* NAND */

1
include/configs/PCIPPC2.h
View File

@ -77,6 +77,7 @@
*/
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
/*
* Miscellaneous configurable options

1
include/configs/PCIPPC6.h
View File

@ -79,6 +79,7 @@
*/
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
/*
* Miscellaneous configurable options

2
include/configs/PIP405.h
View File

@ -69,6 +69,8 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
/**************************************************************

2
include/configs/PLU405.h
View File

@ -160,6 +160,8 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_NAND_LEGACY
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512

2
include/configs/PM520.h
View File

@ -101,6 +101,8 @@
#define ADD_DOC_CMD 0
#else
#define ADD_DOC_CMD CFG_CMD_DOC
/* DoC requires legacy NAND for now */
#define CFG_NAND_LEGACY
#endif
/*

2
include/configs/PM826.h
View File

@ -180,6 +180,8 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
/*
* Disk-On-Chip configuration
*/

1
include/configs/PM828.h
View File

@ -183,6 +183,7 @@
/*
* Disk-On-Chip configuration
*/
#define CFG_NAND_LEGACY
#define CFG_DOC_SHORT_TIMEOUT
#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */

105
include/configs/PPChameleonEVB.h
View File

@ -188,36 +188,31 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
/*
* nand device 1 on dave (PPChameleonEVB) needs more time,
* so we just introduce additional wait in nand_wait(),
* effectively for both devices.
*/
#define PPCHAMELON_NAND_TIMER_HACK
/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
#define CONFIG_NEW_NAND_CODE
#define CFG_NAND0_BASE 0xFF400000
#define CFG_NAND1_BASE 0xFF000000
#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, CFG_NAND1_BASE }
#define NAND_BIG_DELAY_US 25
#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
#define SECTORSIZE 512
#define NAND_NO_RB
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CFG_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CFG_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
#define CFG_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
#define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
#ifdef CONFIG_NEW_NAND_CODE
#define MACRO_NAND_DISABLE_CE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
@ -293,83 +288,17 @@
break; \
} \
} while(0)
#else
#define NAND_DISABLE_CE(nand) do \
{ \
switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
{ \
case CFG_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
break; \
case CFG_NAND1_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
break; \
} \
} while(0)
#define NAND_ENABLE_CE(nand) do \
{ \
switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
{ \
case CFG_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
break; \
case CFG_NAND1_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
break; \
} \
} while(0)
#if 0
#define SECTORSIZE 512
#define NAND_NO_RB
#define NAND_CTL_CLRALE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
case CFG_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
break; \
case CFG_NAND1_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
break; \
} \
} while(0)
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_CTL_SETALE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
case CFG_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
break; \
case CFG_NAND1_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
break; \
} \
} while(0)
#define NAND_CTL_CLRCLE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
case CFG_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
break; \
case CFG_NAND1_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
break; \
} \
} while(0)
#define NAND_CTL_SETCLE(nandptr) do { \
switch((unsigned long)nandptr) { \
case CFG_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
break; \
case CFG_NAND1_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
break; \
} \
} while(0)
#endif /* !CONFIG_NEW_NAND_CODE */
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#ifdef NAND_NO_RB
/* constant delay (see also tR in the datasheet) */
@ -385,7 +314,7 @@
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#endif
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------

2
include/configs/RBC823.h
View File

@ -326,6 +326,8 @@
/************************************************************
* Disk-On-Chip configuration
************************************************************/
#define CFG_NAND_LEGACY
#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
#define CFG_DOC_SHORT_TIMEOUT
#define CFG_DOC_SUPPORT_2000

1
include/configs/SXNI855T.h
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@ -183,6 +183,7 @@
*/
/* NAND flash support */
#define CFG_NAND_LEGACY
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512

2
include/configs/VOH405.h
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@ -141,6 +141,8 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_NAND_LEGACY
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512

2
include/configs/WUH405.h
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@ -133,6 +133,8 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_NAND_LEGACY
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512

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