dts: update to v4.11-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
parent
cc2392cf4f
commit
957bb6b6bc
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@ -40,6 +40,8 @@ Board compatible values:
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- "hardkernel,odroid-c2" (Meson gxbb)
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- "hardkernel,odroid-c2" (Meson gxbb)
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- "amlogic,p200" (Meson gxbb)
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- "amlogic,p200" (Meson gxbb)
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- "amlogic,p201" (Meson gxbb)
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- "amlogic,p201" (Meson gxbb)
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- "wetek,hub" (Meson gxbb)
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- "wetek,play2" (Meson gxbb)
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- "amlogic,p212" (Meson gxl s905x)
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- "amlogic,p212" (Meson gxl s905x)
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- "amlogic,p230" (Meson gxl s905d)
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- "amlogic,p230" (Meson gxl s905d)
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- "amlogic,p231" (Meson gxl s905d)
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- "amlogic,p231" (Meson gxl s905d)
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@ -31,6 +31,12 @@ to deliver its interrupts via SPIs.
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This also affects writes to the tval register, due to the implicit
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This also affects writes to the tval register, due to the implicit
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counter read.
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counter read.
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- hisilicon,erratum-161010101 : A boolean property. Indicates the
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presence of Hisilicon erratum 161010101, which says that reading the
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counters is unreliable in some cases, and reads may return a value 32
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beyond the correct value. This also affects writes to the tval
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registers, due to the implicit counter read.
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** Optional properties:
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** Optional properties:
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- arm,cpu-registers-not-fw-configured : Firmware does not initialize
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- arm,cpu-registers-not-fw-configured : Firmware does not initialize
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@ -0,0 +1,19 @@
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Device tree bindings for Axentia ARM devices
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============================================
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Linea CPU module
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----------------
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Required root node properties:
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compatible = "axentia,linea",
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"atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
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and following the rules from atmel-at91.txt for a sama5d31 SoC.
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TSE-850 v3 board
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----------------
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Required root node properties:
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compatible = "axentia,tse850v3", "axentia,linea",
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"atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
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and following the rules from above for the axentia,linea CPU module.
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@ -158,6 +158,7 @@ nodes to be present and contain the properties described below.
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"arm,cortex-a53"
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"arm,cortex-a53"
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"arm,cortex-a57"
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"arm,cortex-a57"
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"arm,cortex-a72"
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"arm,cortex-a72"
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"arm,cortex-a73"
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"arm,cortex-m0"
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"arm,cortex-m0"
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"arm,cortex-m0+"
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"arm,cortex-m0+"
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"arm,cortex-m1"
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"arm,cortex-m1"
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@ -202,6 +203,7 @@ nodes to be present and contain the properties described below.
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"marvell,armada-380-smp"
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"marvell,armada-380-smp"
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"marvell,armada-390-smp"
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"marvell,armada-390-smp"
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"marvell,armada-xp-smp"
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"marvell,armada-xp-smp"
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"marvell,98dx3236-smp"
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"mediatek,mt6589-smp"
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"mediatek,mt6589-smp"
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"mediatek,mt81xx-tz-smp"
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"mediatek,mt81xx-tz-smp"
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"qcom,gcc-msm8660"
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"qcom,gcc-msm8660"
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@ -13,6 +13,10 @@ EnBW AM1808 based CMC board
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Required root node properties:
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Required root node properties:
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- compatible = "enbw,cmc", "ti,da850;
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- compatible = "enbw,cmc", "ti,da850;
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LEGO MINDSTORMS EV3 (AM1808 based)
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Required root node properties:
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- compatible = "lego,ev3", "ti,da850";
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Generic DaVinci Boards
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Generic DaVinci Boards
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----------------------
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----------------------
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@ -108,7 +108,7 @@ status.
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- compatible: Should contain a chip-specific compatible string,
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- compatible: Should contain a chip-specific compatible string,
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Chip-specific strings are of the form "fsl,<chip>-scfg",
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Chip-specific strings are of the form "fsl,<chip>-scfg",
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The following <chip>s are known to be supported:
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The following <chip>s are known to be supported:
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ls1021a, ls1043a, ls1046a, ls2080a.
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ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
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- reg: should contain base address and length of SCFG memory-mapped registers
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- reg: should contain base address and length of SCFG memory-mapped registers
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@ -126,7 +126,7 @@ core start address and release the secondary core from holdoff and startup.
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- compatible: Should contain a chip-specific compatible string,
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- compatible: Should contain a chip-specific compatible string,
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Chip-specific strings are of the form "fsl,<chip>-dcfg",
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Chip-specific strings are of the form "fsl,<chip>-dcfg",
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The following <chip>s are known to be supported:
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The following <chip>s are known to be supported:
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ls1021a, ls1043a, ls1046a, ls2080a.
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ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
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- reg : should contain base address and length of DCFG memory-mapped registers
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- reg : should contain base address and length of DCFG memory-mapped registers
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@ -139,6 +139,22 @@ Example:
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Freescale ARMv8 based Layerscape SoC family Device Tree Bindings
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Freescale ARMv8 based Layerscape SoC family Device Tree Bindings
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----------------------------------------------------------------
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----------------------------------------------------------------
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LS1012A SoC
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Required root node properties:
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- compatible = "fsl,ls1012a";
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LS1012A ARMv8 based RDB Board
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Required root node properties:
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- compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
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LS1012A ARMv8 based FRDM Board
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Required root node properties:
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- compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
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LS1012A ARMv8 based QDS Board
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Required root node properties:
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- compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
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LS1043A SoC
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LS1043A SoC
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Required root node properties:
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Required root node properties:
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- compatible = "fsl,ls1043a";
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- compatible = "fsl,ls1043a";
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@ -1,5 +1,9 @@
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Hisilicon Platforms Device Tree Bindings
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Hisilicon Platforms Device Tree Bindings
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----------------------------------------------------
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----------------------------------------------------
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Hi3660 SoC
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Required root node properties:
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- compatible = "hisilicon,hi3660";
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Hi4511 Board
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Hi4511 Board
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Required root node properties:
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Required root node properties:
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- compatible = "hisilicon,hi3620-hi4511";
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- compatible = "hisilicon,hi3620-hi4511";
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@ -0,0 +1,16 @@
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Resume Control
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--------------
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Available on Marvell SOCs: 98DX3336 and 98DX4251
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Required properties:
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- compatible: must be "marvell,98dx3336-resume-ctrl"
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- reg: Should contain resume control registers location and length
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Example:
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resume@20980 {
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compatible = "marvell,98dx3336-resume-ctrl";
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reg = <0x20980 0x10>;
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};
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@ -0,0 +1,23 @@
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Marvell 98DX3236, 98DX3336 and 98DX4251 Platforms Device Tree Bindings
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----------------------------------------------------------------------
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Boards with a SoC of the Marvell 98DX3236, 98DX3336 and 98DX4251 families
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shall have the following property:
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Required root node property:
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compatible: must contain "marvell,armadaxp-98dx3236"
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In addition, boards using the Marvell 98DX3336 SoC shall have the
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following property:
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Required root node property:
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compatible: must contain "marvell,armadaxp-98dx3336"
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In addition, boards using the Marvell 98DX4251 SoC shall have the
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following property:
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Required root node property:
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compatible: must contain "marvell,armadaxp-98dx4251"
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@ -151,6 +151,9 @@ Boards:
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- AM335X SBC-T335 : single board computer, built around the Sitara AM3352/4
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- AM335X SBC-T335 : single board computer, built around the Sitara AM3352/4
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compatible = "compulab,sbc-t335", "compulab,cm-t335", "ti,am33xx"
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compatible = "compulab,sbc-t335", "compulab,cm-t335", "ti,am33xx"
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- AM335X phyCORE-AM335x: Development kit
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compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx"
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- OMAP5 EVM : Evaluation Module
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- OMAP5 EVM : Evaluation Module
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compatible = "ti,omap5-evm", "ti,omap5"
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compatible = "ti,omap5-evm", "ti,omap5"
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@ -75,7 +75,7 @@ Boards:
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compatible = "renesas,rskrza1", "renesas,r7s72100"
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compatible = "renesas,rskrza1", "renesas,r7s72100"
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- Salvator-X (RTP0RC7795SIPB0010S)
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- Salvator-X (RTP0RC7795SIPB0010S)
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compatible = "renesas,salvator-x", "renesas,r8a7795";
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compatible = "renesas,salvator-x", "renesas,r8a7795";
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- Salvator-X
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- Salvator-X (RTP0RC7796SIPB0011S)
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compatible = "renesas,salvator-x", "renesas,r8a7796";
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compatible = "renesas,salvator-x", "renesas,r8a7796";
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- SILK (RTP0RC7794LCB00011S)
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- SILK (RTP0RC7794LCB00011S)
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compatible = "renesas,silk", "renesas,r8a7794"
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compatible = "renesas,silk", "renesas,r8a7794"
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@ -12,6 +12,7 @@ using one of the following compatible strings:
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allwinner,sun8i-a23
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allwinner,sun8i-a23
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allwinner,sun8i-a33
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allwinner,sun8i-a33
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allwinner,sun8i-a83t
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allwinner,sun8i-a83t
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allwinner,sun8i-h2-plus
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allwinner,sun8i-h3
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allwinner,sun8i-h3
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allwinner,sun9i-a80
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allwinner,sun9i-a80
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allwinner,sun50i-a64
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allwinner,sun50i-a64
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@ -0,0 +1,18 @@
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Device tree binding for the TI DA850 AHCI SATA Controller
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---------------------------------------------------------
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Required properties:
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- compatible: must be "ti,da850-ahci"
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- reg: physical base addresses and sizes of the two register regions
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used by the controller: the register map as defined by the
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AHCI 1.1 standard and the Power Down Control Register (PWRDN)
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for enabling/disabling the SATA clock receiver
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- interrupts: interrupt specifier (refer to the interrupt binding)
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Example:
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sata: sata@218000 {
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compatible = "ti,da850-ahci";
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reg = <0x218000 0x2000>, <0x22c018 0x4>;
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interrupts = <67>;
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};
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@ -51,7 +51,7 @@ Required properties:
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- compatible: should be one of:
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- compatible: should be one of:
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"qcom,msm8660-ebi2"
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"qcom,msm8660-ebi2"
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"qcom,apq8060-ebi2"
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"qcom,apq8060-ebi2"
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- #address-cells: shoule be <2>: the first cell is the chipselect,
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- #address-cells: should be <2>: the first cell is the chipselect,
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the second cell is the offset inside the memory range
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the second cell is the offset inside the memory range
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- #size-cells: should be <1>
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- #size-cells: should be <1>
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- ranges: should be set to:
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- ranges: should be set to:
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@ -64,7 +64,7 @@ Required properties:
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- reg: two ranges of registers: EBI2 config and XMEM config areas
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- reg: two ranges of registers: EBI2 config and XMEM config areas
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- reg-names: should be "ebi2", "xmem"
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- reg-names: should be "ebi2", "xmem"
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- clocks: two clocks, EBI_2X and EBI
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- clocks: two clocks, EBI_2X and EBI
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- clock-names: shoule be "ebi2x", "ebi2"
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- clock-names: should be "ebi2x", "ebi2"
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Optional subnodes:
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Optional subnodes:
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- Nodes inside the EBI2 will be considered device nodes.
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- Nodes inside the EBI2 will be considered device nodes.
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@ -100,7 +100,7 @@ Optional properties arrays for FAST chip selects:
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assertion, with respect to the cycle where ADV (address valid) is asserted.
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assertion, with respect to the cycle where ADV (address valid) is asserted.
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2 means 2 cycles between ADV and OE. Valid values 0, 1, 2 or 3.
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2 means 2 cycles between ADV and OE. Valid values 0, 1, 2 or 3.
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- qcom,xmem-read-hold-cycles: the length in cycles of the first segment of a
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- qcom,xmem-read-hold-cycles: the length in cycles of the first segment of a
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read transfer. For a single read trandfer this will be the time from CS
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read transfer. For a single read transfer this will be the time from CS
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assertion to OE assertion. Valid values 0 thru 15.
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assertion to OE assertion. Valid values 0 thru 15.
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@ -16,7 +16,20 @@ Required properties:
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- #clock-cells: Should be <1>. The permitted clock-specifier values can be
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- #clock-cells: Should be <1>. The permitted clock-specifier values can be
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found in include/dt-bindings/clock/bcm2835.h
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found in include/dt-bindings/clock/bcm2835.h
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- reg: Specifies base physical address and size of the registers
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- reg: Specifies base physical address and size of the registers
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- clocks: The external oscillator clock phandle
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- clocks: phandles to the parent clocks used as input to the module, in
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the following order:
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- External oscillator
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- DSI0 byte clock
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- DSI0 DDR2 clock
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- DSI0 DDR clock
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- DSI1 byte clock
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- DSI1 DDR2 clock
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- DSI1 DDR clock
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Only external oscillator is required. The DSI clocks may
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not be present, in which case their children will be
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unusable.
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Example:
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Example:
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@ -1,38 +0,0 @@
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* Samsung Exynos4415 Clock Controller
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The Exynos4415 clock controller generates and supplies clock to various
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consumer devices within the Exynos4415 SoC.
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Required properties:
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- compatible: should be one of the following:
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- "samsung,exynos4415-cmu" - for the main system clocks controller
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(CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_CPU clock domains).
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- "samsung,exynos4415-cmu-dmc" - for the Exynos4415 SoC DRAM Memory
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Controller (DMC) domain clock controller.
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume.
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All available clocks are defined as preprocessor macros in
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dt-bindings/clock/exynos4415.h header and can be used in device
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tree sources.
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Example 1: An example of a clock controller node is listed below.
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cmu: clock-controller@10030000 {
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compatible = "samsung,exynos4415-cmu";
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reg = <0x10030000 0x18000>;
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#clock-cells = <1>;
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};
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cmu-dmc: clock-controller@105C0000 {
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compatible = "samsung,exynos4415-cmu-dmc";
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reg = <0x105C0000 0x3000>;
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#clock-cells = <1>;
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};
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@ -0,0 +1,42 @@
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* Hisilicon Hi3660 Clock Controller
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The Hi3660 clock controller generates and supplies clock to various
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controllers within the Hi3660 SoC.
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Required Properties:
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- compatible: the compatible should be one of the following strings to
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indicate the clock controller functionality.
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- "hisilicon,hi3660-crgctrl"
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- "hisilicon,hi3660-pctrl"
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- "hisilicon,hi3660-pmuctrl"
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- "hisilicon,hi3660-sctrl"
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- "hisilicon,hi3660-iomcu"
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|
|
||||||
|
- reg: physical base address of the controller and length of memory mapped
|
||||||
|
region.
|
||||||
|
|
||||||
|
- #clock-cells: should be 1.
|
||||||
|
|
||||||
|
Each clock is assigned an identifier and client nodes use this identifier
|
||||||
|
to specify the clock which they consume.
|
||||||
|
|
||||||
|
All these identifier could be found in <dt-bindings/clock/hi3660-clock.h>.
|
||||||
|
|
||||||
|
Examples:
|
||||||
|
crg_ctrl: clock-controller@fff35000 {
|
||||||
|
compatible = "hisilicon,hi3660-crgctrl", "syscon";
|
||||||
|
reg = <0x0 0xfff35000 0x0 0x1000>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
uart0: serial@fdf02000 {
|
||||||
|
compatible = "arm,pl011", "arm,primecell";
|
||||||
|
reg = <0x0 0xfdf02000 0x0 0x1000>;
|
||||||
|
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
|
||||||
|
<&crg_ctrl HI3660_PCLK>;
|
||||||
|
clock-names = "uartclk", "apb_pclk";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
|
@ -0,0 +1,65 @@
|
||||||
|
Binding for IDT VersaClock5 programmable i2c clock generator.
|
||||||
|
|
||||||
|
The IDT VersaClock5 are programmable i2c clock generators providing
|
||||||
|
from 3 to 12 output clocks.
|
||||||
|
|
||||||
|
==I2C device node==
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: shall be one of "idt,5p49v5923" , "idt,5p49v5933".
|
||||||
|
- reg: i2c device address, shall be 0x68 or 0x6a.
|
||||||
|
- #clock-cells: from common clock binding; shall be set to 1.
|
||||||
|
- clocks: from common clock binding; list of parent clock handles,
|
||||||
|
- 5p49v5923: (required) either or both of XTAL or CLKIN
|
||||||
|
reference clock.
|
||||||
|
- 5p49v5933: (optional) property not present (internal
|
||||||
|
Xtal used) or CLKIN reference
|
||||||
|
clock.
|
||||||
|
- clock-names: from common clock binding; clock input names, can be
|
||||||
|
- 5p49v5923: (required) either or both of "xin", "clkin".
|
||||||
|
- 5p49v5933: (optional) property not present or "clkin".
|
||||||
|
|
||||||
|
==Mapping between clock specifier and physical pins==
|
||||||
|
|
||||||
|
When referencing the provided clock in the DT using phandle and
|
||||||
|
clock specifier, the following mapping applies:
|
||||||
|
|
||||||
|
5P49V5923:
|
||||||
|
0 -- OUT0_SEL_I2CB
|
||||||
|
1 -- OUT1
|
||||||
|
2 -- OUT2
|
||||||
|
|
||||||
|
5P49V5933:
|
||||||
|
0 -- OUT0_SEL_I2CB
|
||||||
|
1 -- OUT1
|
||||||
|
2 -- OUT4
|
||||||
|
|
||||||
|
==Example==
|
||||||
|
|
||||||
|
/* 25MHz reference crystal */
|
||||||
|
ref25: ref25m {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
|
clock-frequency = <25000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c-master-node {
|
||||||
|
|
||||||
|
/* IDT 5P49V5923 i2c clock generator */
|
||||||
|
vc5: clock-generator@6a {
|
||||||
|
compatible = "idt,5p49v5923";
|
||||||
|
reg = <0x6a>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
|
||||||
|
/* Connect XIN input to 25MHz reference */
|
||||||
|
clocks = <&ref25m>;
|
||||||
|
clock-names = "xin";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Consumer referencing the 5P49V5923 pin OUT1 */
|
||||||
|
consumer {
|
||||||
|
...
|
||||||
|
clocks = <&vc5 1>;
|
||||||
|
...
|
||||||
|
}
|
|
@ -7,6 +7,7 @@ Required properties:
|
||||||
- compatible : must be "marvell,armada-370-corediv-clock",
|
- compatible : must be "marvell,armada-370-corediv-clock",
|
||||||
"marvell,armada-375-corediv-clock",
|
"marvell,armada-375-corediv-clock",
|
||||||
"marvell,armada-380-corediv-clock",
|
"marvell,armada-380-corediv-clock",
|
||||||
|
"marvell,mv98dx3236-corediv-clock",
|
||||||
|
|
||||||
- reg : must be the register address of Core Divider control register
|
- reg : must be the register address of Core Divider control register
|
||||||
- #clock-cells : from common clock binding; shall be set to 1
|
- #clock-cells : from common clock binding; shall be set to 1
|
||||||
|
|
|
@ -3,6 +3,7 @@ Device Tree Clock bindings for cpu clock of Marvell EBU platforms
|
||||||
Required properties:
|
Required properties:
|
||||||
- compatible : shall be one of the following:
|
- compatible : shall be one of the following:
|
||||||
"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
|
"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
|
||||||
|
"marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC
|
||||||
- reg : Address and length of the clock complex register set, followed
|
- reg : Address and length of the clock complex register set, followed
|
||||||
by address and length of the PMU DFS registers
|
by address and length of the PMU DFS registers
|
||||||
- #clock-cells : should be set to 1.
|
- #clock-cells : should be set to 1.
|
||||||
|
|
|
@ -117,7 +117,7 @@ ID Clock Peripheral
|
||||||
25 tdm Time Division Mplx
|
25 tdm Time Division Mplx
|
||||||
28 xor1 XOR DMA 1
|
28 xor1 XOR DMA 1
|
||||||
29 sata1lnk
|
29 sata1lnk
|
||||||
30 sata1 SATA Host 0
|
30 sata1 SATA Host 1
|
||||||
|
|
||||||
The following is a list of provided IDs for Dove:
|
The following is a list of provided IDs for Dove:
|
||||||
ID Clock Peripheral
|
ID Clock Peripheral
|
||||||
|
|
|
@ -11,6 +11,7 @@ Required properties :
|
||||||
compatible "qcom,rpmcc" should be also included.
|
compatible "qcom,rpmcc" should be also included.
|
||||||
|
|
||||||
"qcom,rpmcc-msm8916", "qcom,rpmcc"
|
"qcom,rpmcc-msm8916", "qcom,rpmcc"
|
||||||
|
"qcom,rpmcc-msm8974", "qcom,rpmcc"
|
||||||
"qcom,rpmcc-apq8064", "qcom,rpmcc"
|
"qcom,rpmcc-apq8064", "qcom,rpmcc"
|
||||||
|
|
||||||
- #clock-cells : shall contain 1
|
- #clock-cells : shall contain 1
|
||||||
|
|
|
@ -31,6 +31,7 @@ Required properties:
|
||||||
* "fsl,t4240-clockgen"
|
* "fsl,t4240-clockgen"
|
||||||
* "fsl,b4420-clockgen"
|
* "fsl,b4420-clockgen"
|
||||||
* "fsl,b4860-clockgen"
|
* "fsl,b4860-clockgen"
|
||||||
|
* "fsl,ls1012a-clockgen"
|
||||||
* "fsl,ls1021a-clockgen"
|
* "fsl,ls1021a-clockgen"
|
||||||
* "fsl,ls1043a-clockgen"
|
* "fsl,ls1043a-clockgen"
|
||||||
* "fsl,ls1046a-clockgen"
|
* "fsl,ls1046a-clockgen"
|
||||||
|
|
|
@ -42,6 +42,10 @@ Required Properties:
|
||||||
Domain bindings in
|
Domain bindings in
|
||||||
Documentation/devicetree/bindings/power/power_domain.txt.
|
Documentation/devicetree/bindings/power/power_domain.txt.
|
||||||
|
|
||||||
|
- #reset-cells: Must be 1
|
||||||
|
- The single reset specifier cell must be the module number, as defined
|
||||||
|
in the datasheet.
|
||||||
|
|
||||||
|
|
||||||
Examples
|
Examples
|
||||||
--------
|
--------
|
||||||
|
@ -55,6 +59,7 @@ Examples
|
||||||
clock-names = "extal", "extalr";
|
clock-names = "extal", "extalr";
|
||||||
#clock-cells = <2>;
|
#clock-cells = <2>;
|
||||||
#power-domain-cells = <0>;
|
#power-domain-cells = <0>;
|
||||||
|
#reset-cells = <1>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
|
@ -69,5 +74,6 @@ Examples
|
||||||
dmas = <&dmac1 0x13>, <&dmac1 0x12>;
|
dmas = <&dmac1 0x13>, <&dmac1 0x12>;
|
||||||
dma-names = "tx", "rx";
|
dma-names = "tx", "rx";
|
||||||
power-domains = <&cpg>;
|
power-domains = <&cpg>;
|
||||||
|
resets = <&cpg 310>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
|
@ -0,0 +1,57 @@
|
||||||
|
* Rockchip RK3328 Clock and Reset Unit
|
||||||
|
|
||||||
|
The RK3328 clock controller generates and supplies clock to various
|
||||||
|
controllers within the SoC and also implements a reset controller for SoC
|
||||||
|
peripherals.
|
||||||
|
|
||||||
|
Required Properties:
|
||||||
|
|
||||||
|
- compatible: should be "rockchip,rk3328-cru"
|
||||||
|
- reg: physical base address of the controller and length of memory mapped
|
||||||
|
region.
|
||||||
|
- #clock-cells: should be 1.
|
||||||
|
- #reset-cells: should be 1.
|
||||||
|
|
||||||
|
Optional Properties:
|
||||||
|
|
||||||
|
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||||
|
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||||
|
|
||||||
|
Each clock is assigned an identifier and client nodes can use this identifier
|
||||||
|
to specify the clock which they consume. All available clocks are defined as
|
||||||
|
preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
|
||||||
|
used in device tree sources. Similar macros exist for the reset sources in
|
||||||
|
these files.
|
||||||
|
|
||||||
|
External clocks:
|
||||||
|
|
||||||
|
There are several clocks that are generated outside the SoC. It is expected
|
||||||
|
that they are defined using standard clock bindings with following
|
||||||
|
clock-output-names:
|
||||||
|
- "xin24m" - crystal input - required,
|
||||||
|
- "clkin_i2s" - external I2S clock - optional,
|
||||||
|
- "gmac_clkin" - external GMAC clock - optional
|
||||||
|
- "phy_50m_out" - output clock of the pll in the mac phy
|
||||||
|
|
||||||
|
Example: Clock controller node:
|
||||||
|
|
||||||
|
cru: clock-controller@ff440000 {
|
||||||
|
compatible = "rockchip,rk3328-cru";
|
||||||
|
reg = <0x0 0xff440000 0x0 0x1000>;
|
||||||
|
rockchip,grf = <&grf>;
|
||||||
|
|
||||||
|
#clock-cells = <1>;
|
||||||
|
#reset-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
Example: UART controller node that consumes the clock generated by the clock
|
||||||
|
controller:
|
||||||
|
|
||||||
|
uart0: serial@ff120000 {
|
||||||
|
compatible = "snps,dw-apb-uart";
|
||||||
|
reg = <0xff120000 0x100>;
|
||||||
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
clocks = <&cru SCLK_UART0>;
|
||||||
|
};
|
|
@ -13,6 +13,12 @@ Required Properties:
|
||||||
- #clock-cells: should be 1.
|
- #clock-cells: should be 1.
|
||||||
- #reset-cells: should be 1.
|
- #reset-cells: should be 1.
|
||||||
|
|
||||||
|
Optional Properties:
|
||||||
|
|
||||||
|
- rockchip,grf: phandle to the syscon managing the "general register files".
|
||||||
|
It is used for GRF muxes, if missing any muxes present in the GRF will not
|
||||||
|
be available.
|
||||||
|
|
||||||
Each clock is assigned an identifier and client nodes can use this identifier
|
Each clock is assigned an identifier and client nodes can use this identifier
|
||||||
to specify the clock which they consume. All available clocks are defined as
|
to specify the clock which they consume. All available clocks are defined as
|
||||||
preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
|
preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
|
||||||
|
|
|
@ -10,6 +10,7 @@ Required properties:
|
||||||
- compatible: Should be:
|
- compatible: Should be:
|
||||||
"st,stm32f42xx-rcc"
|
"st,stm32f42xx-rcc"
|
||||||
"st,stm32f469-rcc"
|
"st,stm32f469-rcc"
|
||||||
|
"st,stm32f746-rcc"
|
||||||
- reg: should be register base and length as documented in the
|
- reg: should be register base and length as documented in the
|
||||||
datasheet
|
datasheet
|
||||||
- #reset-cells: 1, see below
|
- #reset-cells: 1, see below
|
||||||
|
@ -17,6 +18,9 @@ Required properties:
|
||||||
property, containing a phandle to the clock device node, an index selecting
|
property, containing a phandle to the clock device node, an index selecting
|
||||||
between gated clocks and other clocks and an index specifying the clock to
|
between gated clocks and other clocks and an index specifying the clock to
|
||||||
use.
|
use.
|
||||||
|
- clocks: External oscillator clock phandle
|
||||||
|
- high speed external clock signal (HSE)
|
||||||
|
- external I2S clock (I2S_CKIN)
|
||||||
|
|
||||||
Example:
|
Example:
|
||||||
|
|
||||||
|
@ -25,6 +29,7 @@ Example:
|
||||||
#clock-cells = <2>
|
#clock-cells = <2>
|
||||||
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
|
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
|
||||||
reg = <0x40023800 0x400>;
|
reg = <0x40023800 0x400>;
|
||||||
|
clocks = <&clk_hse>, <&clk_i2s_ckin>;
|
||||||
};
|
};
|
||||||
|
|
||||||
Specifying gated clocks
|
Specifying gated clocks
|
||||||
|
@ -66,6 +71,38 @@ The secondary index is bound with the following magic numbers:
|
||||||
|
|
||||||
0 SYSTICK
|
0 SYSTICK
|
||||||
1 FCLK
|
1 FCLK
|
||||||
|
2 CLK_LSI (low-power clock source)
|
||||||
|
3 CLK_LSE (generated from a 32.768 kHz low-speed external
|
||||||
|
crystal or ceramic resonator)
|
||||||
|
4 CLK_HSE_RTC (HSE division factor for RTC clock)
|
||||||
|
5 CLK_RTC (real-time clock)
|
||||||
|
6 PLL_VCO_I2S (vco frequency of I2S pll)
|
||||||
|
7 PLL_VCO_SAI (vco frequency of SAI pll)
|
||||||
|
8 CLK_LCD (LCD-TFT)
|
||||||
|
9 CLK_I2S (I2S clocks)
|
||||||
|
10 CLK_SAI1 (audio clocks)
|
||||||
|
11 CLK_SAI2
|
||||||
|
12 CLK_I2SQ_PDIV (post divisor of pll i2s q divisor)
|
||||||
|
13 CLK_SAIQ_PDIV (post divisor of pll sai q divisor)
|
||||||
|
|
||||||
|
14 CLK_HSI (Internal ocscillator clock)
|
||||||
|
15 CLK_SYSCLK (System Clock)
|
||||||
|
16 CLK_HDMI_CEC (HDMI-CEC clock)
|
||||||
|
17 CLK_SPDIF (SPDIF-Rx clock)
|
||||||
|
18 CLK_USART1 (U(s)arts clocks)
|
||||||
|
19 CLK_USART2
|
||||||
|
20 CLK_USART3
|
||||||
|
21 CLK_UART4
|
||||||
|
22 CLK_UART5
|
||||||
|
23 CLK_USART6
|
||||||
|
24 CLK_UART7
|
||||||
|
25 CLK_UART8
|
||||||
|
26 CLK_I2C1 (I2S clocks)
|
||||||
|
27 CLK_I2C2
|
||||||
|
28 CLK_I2C3
|
||||||
|
29 CLK_I2C4
|
||||||
|
30 CLK_LPTIMER (LPTimer1 clock)
|
||||||
|
)
|
||||||
|
|
||||||
Example:
|
Example:
|
||||||
|
|
||||||
|
|
|
@ -0,0 +1,20 @@
|
||||||
|
Clock bindings for ST-Ericsson ABx500 clocks
|
||||||
|
|
||||||
|
Required properties :
|
||||||
|
- compatible : shall contain the following:
|
||||||
|
"stericsson,ab8500-clk"
|
||||||
|
- #clock-cells should be <1>
|
||||||
|
|
||||||
|
The ABx500 clocks need to be placed as a subnode of an AB8500
|
||||||
|
device node, see mfd/ab8500.txt
|
||||||
|
|
||||||
|
All available clocks are defined as preprocessor macros in
|
||||||
|
dt-bindings/clock/ste-ab8500.h header and can be used in device
|
||||||
|
tree sources.
|
||||||
|
|
||||||
|
Example:
|
||||||
|
|
||||||
|
clock-controller {
|
||||||
|
compatible = "stericsson,ab8500-clk";
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
|
@ -0,0 +1,28 @@
|
||||||
|
Allwinner A80 Display Engine Clock Control Binding
|
||||||
|
--------------------------------------------------
|
||||||
|
|
||||||
|
Required properties :
|
||||||
|
- compatible: must contain one of the following compatibles:
|
||||||
|
- "allwinner,sun9i-a80-de-clks"
|
||||||
|
|
||||||
|
- reg: Must contain the registers base address and length
|
||||||
|
- clocks: phandle to the clocks feeding the display engine subsystem.
|
||||||
|
Three are needed:
|
||||||
|
- "mod": the display engine module clock
|
||||||
|
- "dram": the DRAM bus clock for the system
|
||||||
|
- "bus": the bus clock for the whole display engine subsystem
|
||||||
|
- clock-names: Must contain the clock names described just above
|
||||||
|
- resets: phandle to the reset control for the display engine subsystem.
|
||||||
|
- #clock-cells : must contain 1
|
||||||
|
- #reset-cells : must contain 1
|
||||||
|
|
||||||
|
Example:
|
||||||
|
de_clocks: clock@3000000 {
|
||||||
|
compatible = "allwinner,sun9i-a80-de-clks";
|
||||||
|
reg = <0x03000000 0x30>;
|
||||||
|
clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;
|
||||||
|
clock-names = "mod", "dram", "bus";
|
||||||
|
resets = <&ccu RST_BUS_DE>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
#reset-cells = <1>;
|
||||||
|
};
|
|
@ -0,0 +1,24 @@
|
||||||
|
Allwinner A80 USB Clock Control Binding
|
||||||
|
---------------------------------------
|
||||||
|
|
||||||
|
Required properties :
|
||||||
|
- compatible: must contain one of the following compatibles:
|
||||||
|
- "allwinner,sun9i-a80-usb-clocks"
|
||||||
|
|
||||||
|
- reg: Must contain the registers base address and length
|
||||||
|
- clocks: phandle to the clocks feeding the USB subsystem. Two are needed:
|
||||||
|
- "bus": the bus clock for the whole USB subsystem
|
||||||
|
- "hosc": the high frequency oscillator (usually at 24MHz)
|
||||||
|
- clock-names: Must contain the clock names described just above
|
||||||
|
- #clock-cells : must contain 1
|
||||||
|
- #reset-cells : must contain 1
|
||||||
|
|
||||||
|
Example:
|
||||||
|
usb_clocks: clock@a08000 {
|
||||||
|
compatible = "allwinner,sun9i-a80-usb-clks";
|
||||||
|
reg = <0x00a08000 0x8>;
|
||||||
|
clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
|
||||||
|
clock-names = "bus", "hosc";
|
||||||
|
#clock-cells = <1>;
|
||||||
|
#reset-cells = <1>;
|
||||||
|
};
|
|
@ -7,6 +7,8 @@ Required properties :
|
||||||
- "allwinner,sun8i-a23-ccu"
|
- "allwinner,sun8i-a23-ccu"
|
||||||
- "allwinner,sun8i-a33-ccu"
|
- "allwinner,sun8i-a33-ccu"
|
||||||
- "allwinner,sun8i-h3-ccu"
|
- "allwinner,sun8i-h3-ccu"
|
||||||
|
- "allwinner,sun8i-v3s-ccu"
|
||||||
|
- "allwinner,sun9i-a80-ccu"
|
||||||
- "allwinner,sun50i-a64-ccu"
|
- "allwinner,sun50i-a64-ccu"
|
||||||
|
|
||||||
- reg: Must contain the registers base address and length
|
- reg: Must contain the registers base address and length
|
||||||
|
|
|
@ -1,15 +1,22 @@
|
||||||
Binding for TO CDCE925 programmable I2C clock synthesizers.
|
Binding for TI CDCE913/925/937/949 programmable I2C clock synthesizers.
|
||||||
|
|
||||||
Reference
|
Reference
|
||||||
This binding uses the common clock binding[1].
|
This binding uses the common clock binding[1].
|
||||||
|
|
||||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||||
[2] http://www.ti.com/product/cdce925
|
[2] http://www.ti.com/product/cdce913
|
||||||
|
[3] http://www.ti.com/product/cdce925
|
||||||
|
[4] http://www.ti.com/product/cdce937
|
||||||
|
[5] http://www.ti.com/product/cdce949
|
||||||
|
|
||||||
The driver provides clock sources for each output Y1 through Y5.
|
The driver provides clock sources for each output Y1 through Y5.
|
||||||
|
|
||||||
Required properties:
|
Required properties:
|
||||||
- compatible: Shall be "ti,cdce925"
|
- compatible: Shall be one of the following:
|
||||||
|
- "ti,cdce913": 1-PLL, 3 Outputs
|
||||||
|
- "ti,cdce925": 2-PLL, 5 Outputs
|
||||||
|
- "ti,cdce937": 3-PLL, 7 Outputs
|
||||||
|
- "ti,cdce949": 4-PLL, 9 Outputs
|
||||||
- reg: I2C device address.
|
- reg: I2C device address.
|
||||||
- clocks: Points to a fixed parent clock that provides the input frequency.
|
- clocks: Points to a fixed parent clock that provides the input frequency.
|
||||||
- #clock-cells: From common clock bindings: Shall be 1.
|
- #clock-cells: From common clock bindings: Shall be 1.
|
||||||
|
@ -18,7 +25,7 @@ Optional properties:
|
||||||
- xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
|
- xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
|
||||||
board, or to compensate for external influences.
|
board, or to compensate for external influences.
|
||||||
|
|
||||||
For both PLL1 and PLL2 an optional child node can be used to specify spread
|
For all PLL1, PLL2, ... an optional child node can be used to specify spread
|
||||||
spectrum clocking parameters for a board.
|
spectrum clocking parameters for a board.
|
||||||
- spread-spectrum: SSC mode as defined in the data sheet.
|
- spread-spectrum: SSC mode as defined in the data sheet.
|
||||||
- spread-spectrum-center: Use "centered" mode instead of "max" mode. When
|
- spread-spectrum-center: Use "centered" mode instead of "max" mode. When
|
||||||
|
|
|
@ -13,6 +13,9 @@ Required properties:
|
||||||
"zte,zx296718-lsp1crm":
|
"zte,zx296718-lsp1crm":
|
||||||
zx296718 device level clock selection and gating
|
zx296718 device level clock selection and gating
|
||||||
|
|
||||||
|
"zte,zx296718-audiocrm":
|
||||||
|
zx296718 audio clock selection, divider and gating
|
||||||
|
|
||||||
- reg: Address and length of the register set
|
- reg: Address and length of the register set
|
||||||
|
|
||||||
The clock consumer should specify the desired clock by having the clock
|
The clock consumer should specify the desired clock by having the clock
|
||||||
|
|
|
@ -0,0 +1,128 @@
|
||||||
|
TI CPUFreq and OPP bindings
|
||||||
|
================================
|
||||||
|
|
||||||
|
Certain TI SoCs, like those in the am335x, am437x, am57xx, and dra7xx
|
||||||
|
families support different OPPs depending on the silicon variant in use.
|
||||||
|
The ti-cpufreq driver can use revision and an efuse value from the SoC to
|
||||||
|
provide the OPP framework with supported hardware information. This is
|
||||||
|
used to determine which OPPs from the operating-points-v2 table get enabled
|
||||||
|
when it is parsed by the OPP framework.
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
--------------------
|
||||||
|
In 'cpus' nodes:
|
||||||
|
- operating-points-v2: Phandle to the operating-points-v2 table to use.
|
||||||
|
|
||||||
|
In 'operating-points-v2' table:
|
||||||
|
- compatible: Should be
|
||||||
|
- 'operating-points-v2-ti-cpu' for am335x, am43xx, and dra7xx/am57xx SoCs
|
||||||
|
- syscon: A phandle pointing to a syscon node representing the control module
|
||||||
|
register space of the SoC.
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
--------------------
|
||||||
|
For each opp entry in 'operating-points-v2' table:
|
||||||
|
- opp-supported-hw: Two bitfields indicating:
|
||||||
|
1. Which revision of the SoC the OPP is supported by
|
||||||
|
2. Which eFuse bits indicate this OPP is available
|
||||||
|
|
||||||
|
A bitwise AND is performed against these values and if any bit
|
||||||
|
matches, the OPP gets enabled.
|
||||||
|
|
||||||
|
Example:
|
||||||
|
--------
|
||||||
|
|
||||||
|
/* From arch/arm/boot/dts/am33xx.dtsi */
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
cpu@0 {
|
||||||
|
compatible = "arm,cortex-a8";
|
||||||
|
device_type = "cpu";
|
||||||
|
reg = <0>;
|
||||||
|
|
||||||
|
operating-points-v2 = <&cpu0_opp_table>;
|
||||||
|
|
||||||
|
clocks = <&dpll_mpu_ck>;
|
||||||
|
clock-names = "cpu";
|
||||||
|
|
||||||
|
clock-latency = <300000>; /* From omap-cpufreq driver */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* cpu0 has different OPPs depending on SoC revision and some on revisions
|
||||||
|
* 0x2 and 0x4 have eFuse bits that indicate if they are available or not
|
||||||
|
*/
|
||||||
|
cpu0_opp_table: opp-table {
|
||||||
|
compatible = "operating-points-v2-ti-cpu";
|
||||||
|
syscon = <&scm_conf>;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The three following nodes are marked with opp-suspend
|
||||||
|
* because they can not be enabled simultaneously on a
|
||||||
|
* single SoC.
|
||||||
|
*/
|
||||||
|
opp50@300000000 {
|
||||||
|
opp-hz = /bits/ 64 <300000000>;
|
||||||
|
opp-microvolt = <950000 931000 969000>;
|
||||||
|
opp-supported-hw = <0x06 0x0010>;
|
||||||
|
opp-suspend;
|
||||||
|
};
|
||||||
|
|
||||||
|
opp100@275000000 {
|
||||||
|
opp-hz = /bits/ 64 <275000000>;
|
||||||
|
opp-microvolt = <1100000 1078000 1122000>;
|
||||||
|
opp-supported-hw = <0x01 0x00FF>;
|
||||||
|
opp-suspend;
|
||||||
|
};
|
||||||
|
|
||||||
|
opp100@300000000 {
|
||||||
|
opp-hz = /bits/ 64 <300000000>;
|
||||||
|
opp-microvolt = <1100000 1078000 1122000>;
|
||||||
|
opp-supported-hw = <0x06 0x0020>;
|
||||||
|
opp-suspend;
|
||||||
|
};
|
||||||
|
|
||||||
|
opp100@500000000 {
|
||||||
|
opp-hz = /bits/ 64 <500000000>;
|
||||||
|
opp-microvolt = <1100000 1078000 1122000>;
|
||||||
|
opp-supported-hw = <0x01 0xFFFF>;
|
||||||
|
};
|
||||||
|
|
||||||
|
opp100@600000000 {
|
||||||
|
opp-hz = /bits/ 64 <600000000>;
|
||||||
|
opp-microvolt = <1100000 1078000 1122000>;
|
||||||
|
opp-supported-hw = <0x06 0x0040>;
|
||||||
|
};
|
||||||
|
|
||||||
|
opp120@600000000 {
|
||||||
|
opp-hz = /bits/ 64 <600000000>;
|
||||||
|
opp-microvolt = <1200000 1176000 1224000>;
|
||||||
|
opp-supported-hw = <0x01 0xFFFF>;
|
||||||
|
};
|
||||||
|
|
||||||
|
opp120@720000000 {
|
||||||
|
opp-hz = /bits/ 64 <720000000>;
|
||||||
|
opp-microvolt = <1200000 1176000 1224000>;
|
||||||
|
opp-supported-hw = <0x06 0x0080>;
|
||||||
|
};
|
||||||
|
|
||||||
|
oppturbo@720000000 {
|
||||||
|
opp-hz = /bits/ 64 <720000000>;
|
||||||
|
opp-microvolt = <1260000 1234800 1285200>;
|
||||||
|
opp-supported-hw = <0x01 0xFFFF>;
|
||||||
|
};
|
||||||
|
|
||||||
|
oppturbo@800000000 {
|
||||||
|
opp-hz = /bits/ 64 <800000000>;
|
||||||
|
opp-microvolt = <1260000 1234800 1285200>;
|
||||||
|
opp-supported-hw = <0x06 0x0100>;
|
||||||
|
};
|
||||||
|
|
||||||
|
oppnitro@1000000000 {
|
||||||
|
opp-hz = /bits/ 64 <1000000000>;
|
||||||
|
opp-microvolt = <1325000 1298500 1351500>;
|
||||||
|
opp-supported-hw = <0x04 0x0200>;
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,22 @@
|
||||||
|
The Broadcom Secure Processing Unit (SPU) hardware supports symmetric
|
||||||
|
cryptographic offload for Broadcom SoCs. A SoC may have multiple SPU hardware
|
||||||
|
blocks.
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: Should be one of the following:
|
||||||
|
brcm,spum-crypto - for devices with SPU-M hardware
|
||||||
|
brcm,spu2-crypto - for devices with SPU2 hardware
|
||||||
|
brcm,spu2-v2-crypto - for devices with enhanced SPU2 hardware features like SHA3
|
||||||
|
and Rabin Fingerprint support
|
||||||
|
brcm,spum-nsp-crypto - for the Northstar Plus variant of the SPU-M hardware
|
||||||
|
|
||||||
|
- reg: Should contain SPU registers location and length.
|
||||||
|
- mboxes: The mailbox channel to be used to communicate with the SPU.
|
||||||
|
Mailbox channels correspond to DMA rings on the device.
|
||||||
|
|
||||||
|
Example:
|
||||||
|
crypto@612d0000 {
|
||||||
|
compatible = "brcm,spum-crypto";
|
||||||
|
reg = <0 0x612d0000 0 0x900>;
|
||||||
|
mboxes = <&pdc0 0>;
|
||||||
|
};
|
|
@ -0,0 +1,27 @@
|
||||||
|
MediaTek cryptographic accelerators
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: Should be "mediatek,eip97-crypto"
|
||||||
|
- reg: Address and length of the register set for the device
|
||||||
|
- interrupts: Should contain the five crypto engines interrupts in numeric
|
||||||
|
order. These are global system and four descriptor rings.
|
||||||
|
- clocks: the clock used by the core
|
||||||
|
- clock-names: the names of the clock listed in the clocks property. These are
|
||||||
|
"ethif", "cryp"
|
||||||
|
- power-domains: Must contain a reference to the PM domain.
|
||||||
|
|
||||||
|
|
||||||
|
Example:
|
||||||
|
crypto: crypto@1b240000 {
|
||||||
|
compatible = "mediatek,eip97-crypto";
|
||||||
|
reg = <0 0x1b240000 0 0x20000>;
|
||||||
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
|
||||||
|
<GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
|
||||||
|
<GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
|
||||||
|
<GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
|
||||||
|
<GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
|
||||||
|
<ðsys CLK_ETHSYS_CRYPTO>;
|
||||||
|
clock-names = "ethif","cryp";
|
||||||
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
|
||||||
|
};
|
|
@ -123,6 +123,20 @@ Detailed correlation between sub-blocks and power line according to Exynos SoC:
|
||||||
|--- FSYS
|
|--- FSYS
|
||||||
|--- FSYS2
|
|--- FSYS2
|
||||||
|
|
||||||
|
- In case of Exynos5433, there is VDD_INT power line as following:
|
||||||
|
VDD_INT |--- G2D (parent device)
|
||||||
|
|--- MSCL
|
||||||
|
|--- GSCL
|
||||||
|
|--- JPEG
|
||||||
|
|--- MFC
|
||||||
|
|--- HEVC
|
||||||
|
|--- BUS0
|
||||||
|
|--- BUS1
|
||||||
|
|--- BUS2
|
||||||
|
|--- PERIS (Fixed clock rate)
|
||||||
|
|--- PERIC (Fixed clock rate)
|
||||||
|
|--- FSYS (Fixed clock rate)
|
||||||
|
|
||||||
Example1:
|
Example1:
|
||||||
Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
|
Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
|
||||||
power line (regulator). The MIF (Memory Interface) AXI bus is used to
|
power line (regulator). The MIF (Memory Interface) AXI bus is used to
|
||||||
|
|
|
@ -22,7 +22,7 @@ Required properties:
|
||||||
|
|
||||||
- clocks: contains phandle and clock specifier pairs for the entries
|
- clocks: contains phandle and clock specifier pairs for the entries
|
||||||
in the clock-names property. See
|
in the clock-names property. See
|
||||||
Documentation/devicetree/binding/clock/clock-bindings.txt
|
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||||
|
|
||||||
Optional properties:
|
Optional properties:
|
||||||
|
|
||||||
|
|
|
@ -56,6 +56,18 @@ Required properties for V3D:
|
||||||
- interrupts: The interrupt number
|
- interrupts: The interrupt number
|
||||||
See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
|
See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
|
||||||
|
|
||||||
|
Required properties for DSI:
|
||||||
|
- compatible: Should be "brcm,bcm2835-dsi0" or "brcm,bcm2835-dsi1"
|
||||||
|
- reg: Physical base address and length of the DSI block's registers
|
||||||
|
- interrupts: The interrupt number
|
||||||
|
See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
|
||||||
|
- clocks: a) phy: The DSI PLL clock feeding the DSI analog PHY
|
||||||
|
b) escape: The DSI ESC clock from CPRMAN
|
||||||
|
c) pixel: The DSI pixel clock from CPRMAN
|
||||||
|
- clock-output-names:
|
||||||
|
The 3 clocks output from the DSI analog PHY: dsi[01]_byte,
|
||||||
|
dsi[01]_ddr2, and dsi[01]_ddr
|
||||||
|
|
||||||
[1] Documentation/devicetree/bindings/media/video-interfaces.txt
|
[1] Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||||
|
|
||||||
Example:
|
Example:
|
||||||
|
@ -99,6 +111,29 @@ dpi: dpi@7e208000 {
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
dsi1: dsi@7e700000 {
|
||||||
|
compatible = "brcm,bcm2835-dsi1";
|
||||||
|
reg = <0x7e700000 0x8c>;
|
||||||
|
interrupts = <2 12>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
|
||||||
|
clocks = <&clocks BCM2835_PLLD_DSI1>,
|
||||||
|
<&clocks BCM2835_CLOCK_DSI1E>,
|
||||||
|
<&clocks BCM2835_CLOCK_DSI1P>;
|
||||||
|
clock-names = "phy", "escape", "pixel";
|
||||||
|
|
||||||
|
clock-output-names = "dsi1_byte", "dsi1_ddr2", "dsi1_ddr";
|
||||||
|
|
||||||
|
pitouchscreen: panel@0 {
|
||||||
|
compatible = "raspberrypi,touchscreen";
|
||||||
|
reg = <0>;
|
||||||
|
|
||||||
|
<...>
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
vec: vec@7e806000 {
|
vec: vec@7e806000 {
|
||||||
compatible = "brcm,bcm2835-vec";
|
compatible = "brcm,bcm2835-vec";
|
||||||
reg = <0x7e806000 0x1000>;
|
reg = <0x7e806000 0x1000>;
|
||||||
|
|
|
@ -38,10 +38,22 @@ The following input format properties are required except in "rgb 1x" and
|
||||||
- adi,input-justification: The input bit justification ("left", "evenly",
|
- adi,input-justification: The input bit justification ("left", "evenly",
|
||||||
"right").
|
"right").
|
||||||
|
|
||||||
|
- avdd-supply: A 1.8V supply that powers up the AVDD pin on the chip.
|
||||||
|
- dvdd-supply: A 1.8V supply that powers up the DVDD pin on the chip.
|
||||||
|
- pvdd-supply: A 1.8V supply that powers up the PVDD pin on the chip.
|
||||||
|
- dvdd-3v-supply: A 3.3V supply that powers up the pin called DVDD_3V
|
||||||
|
on the chip.
|
||||||
|
- bgvdd-supply: A 1.8V supply that powers up the BGVDD pin. This is
|
||||||
|
needed only for ADV7511.
|
||||||
|
|
||||||
The following properties are required for ADV7533:
|
The following properties are required for ADV7533:
|
||||||
|
|
||||||
- adi,dsi-lanes: Number of DSI data lanes connected to the DSI host. It should
|
- adi,dsi-lanes: Number of DSI data lanes connected to the DSI host. It should
|
||||||
be one of 1, 2, 3 or 4.
|
be one of 1, 2, 3 or 4.
|
||||||
|
- a2vdd-supply: 1.8V supply that powers up the A2VDD pin on the chip.
|
||||||
|
- v3p3-supply: A 3.3V supply that powers up the V3P3 pin on the chip.
|
||||||
|
- v1p2-supply: A supply that powers up the V1P2 pin on the chip. It can be
|
||||||
|
either 1.2V or 1.8V.
|
||||||
|
|
||||||
Optional properties:
|
Optional properties:
|
||||||
|
|
||||||
|
|
|
@ -33,7 +33,7 @@ Optional properties for dp-controller:
|
||||||
in Documentation/devicetree/bindings/media/video-interfaces.txt,
|
in Documentation/devicetree/bindings/media/video-interfaces.txt,
|
||||||
please refer to the SoC specific binding document:
|
please refer to the SoC specific binding document:
|
||||||
* Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
|
* Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
|
||||||
* Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
|
* Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
|
||||||
|
|
||||||
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||||
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
||||||
|
|
|
@ -1,52 +1,33 @@
|
||||||
DesignWare HDMI bridge bindings
|
Synopsys DesignWare HDMI TX Encoder
|
||||||
|
===================================
|
||||||
|
|
||||||
Required properties:
|
This document defines device tree properties for the Synopsys DesignWare HDMI
|
||||||
- compatible: platform specific such as:
|
TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding
|
||||||
* "snps,dw-hdmi-tx"
|
specification by itself but is meant to be referenced by platform-specific
|
||||||
* "fsl,imx6q-hdmi"
|
device tree bindings.
|
||||||
* "fsl,imx6dl-hdmi"
|
|
||||||
* "rockchip,rk3288-dw-hdmi"
|
|
||||||
- reg: Physical base address and length of the controller's registers.
|
|
||||||
- interrupts: The HDMI interrupt number
|
|
||||||
- clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks,
|
|
||||||
as described in Documentation/devicetree/bindings/clock/clock-bindings.txt,
|
|
||||||
the clocks are soc specific, the clock-names should be "iahb", "isfr"
|
|
||||||
-port@[X]: SoC specific port nodes with endpoint definitions as defined
|
|
||||||
in Documentation/devicetree/bindings/media/video-interfaces.txt,
|
|
||||||
please refer to the SoC specific binding document:
|
|
||||||
* Documentation/devicetree/bindings/display/imx/hdmi.txt
|
|
||||||
* Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
|
|
||||||
|
|
||||||
Optional properties
|
When referenced from platform device tree bindings the properties defined in
|
||||||
- reg-io-width: the width of the reg:1,4, default set to 1 if not present
|
this document are defined as follows. The platform device tree bindings are
|
||||||
- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing,
|
responsible for defining whether each property is required or optional.
|
||||||
if the property is omitted, a functionally reduced I2C bus
|
|
||||||
controller on DW HDMI is probed
|
|
||||||
- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec"
|
|
||||||
|
|
||||||
Example:
|
- reg: Memory mapped base address and length of the DWC HDMI TX registers.
|
||||||
hdmi: hdmi@0120000 {
|
|
||||||
compatible = "fsl,imx6q-hdmi";
|
|
||||||
reg = <0x00120000 0x9000>;
|
|
||||||
interrupts = <0 115 0x04>;
|
|
||||||
gpr = <&gpr>;
|
|
||||||
clocks = <&clks 123>, <&clks 124>;
|
|
||||||
clock-names = "iahb", "isfr";
|
|
||||||
ddc-i2c-bus = <&i2c2>;
|
|
||||||
|
|
||||||
port@0 {
|
- reg-io-width: Width of the registers specified by the reg property. The
|
||||||
reg = <0>;
|
value is expressed in bytes and must be equal to 1 or 4 if specified. The
|
||||||
|
register width defaults to 1 if the property is not present.
|
||||||
|
|
||||||
hdmi_mux_0: endpoint {
|
- interrupts: Reference to the DWC HDMI TX interrupt.
|
||||||
remote-endpoint = <&ipu1_di0_hdmi>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
port@1 {
|
- clocks: References to all the clocks specified in the clock-names property
|
||||||
reg = <1>;
|
as specified in Documentation/devicetree/bindings/clock/clock-bindings.txt.
|
||||||
|
|
||||||
hdmi_mux_1: endpoint {
|
- clock-names: The DWC HDMI TX uses the following clocks.
|
||||||
remote-endpoint = <&ipu1_di1_hdmi>;
|
|
||||||
};
|
- "iahb" is the bus clock for either AHB and APB (mandatory).
|
||||||
};
|
- "isfr" is the internal register configuration clock (mandatory).
|
||||||
};
|
- "cec" is the HDMI CEC controller main clock (optional).
|
||||||
|
|
||||||
|
- ports: The connectivity of the DWC HDMI TX with the rest of the system is
|
||||||
|
expressed in using ports as specified in the device graph bindings defined
|
||||||
|
in Documentation/devicetree/bindings/graph.txt. The numbering of the ports
|
||||||
|
is platform-specific.
|
||||||
|
|
|
@ -0,0 +1,46 @@
|
||||||
|
THS8135 Video DAC
|
||||||
|
-----------------
|
||||||
|
|
||||||
|
This is the binding for Texas Instruments THS8135 Video DAC bridge.
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
|
||||||
|
- compatible: Must be "ti,ths8135"
|
||||||
|
|
||||||
|
Required nodes:
|
||||||
|
|
||||||
|
This device has two video ports. Their connections are modelled using the OF
|
||||||
|
graph bindings specified in Documentation/devicetree/bindings/graph.txt.
|
||||||
|
|
||||||
|
- Video port 0 for RGB input
|
||||||
|
- Video port 1 for VGA output
|
||||||
|
|
||||||
|
Example
|
||||||
|
-------
|
||||||
|
|
||||||
|
vga-bridge {
|
||||||
|
compatible = "ti,ths8135";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
ports {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
port@0 {
|
||||||
|
reg = <0>;
|
||||||
|
|
||||||
|
vga_bridge_in: endpoint {
|
||||||
|
remote-endpoint = <&lcdc_out_vga>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
port@1 {
|
||||||
|
reg = <1>;
|
||||||
|
|
||||||
|
vga_bridge_out: endpoint {
|
||||||
|
remote-endpoint = <&vga_con_in>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
|
@ -6,7 +6,7 @@ Required properties:
|
||||||
location and size of the framebuffer memory.
|
location and size of the framebuffer memory.
|
||||||
- clocks : phandle + clock specifier pair of the FB reference clock.
|
- clocks : phandle + clock specifier pair of the FB reference clock.
|
||||||
- display : phandle to a display node as described in
|
- display : phandle to a display node as described in
|
||||||
Documentation/devicetree/bindings/display/display-timing.txt.
|
Documentation/devicetree/bindings/display/panel/display-timing.txt.
|
||||||
Additionally, the display node has to define properties:
|
Additionally, the display node has to define properties:
|
||||||
- bits-per-pixel: Bits per pixel.
|
- bits-per-pixel: Bits per pixel.
|
||||||
- ac-prescale : LCD AC bias frequency. This frequency is the required
|
- ac-prescale : LCD AC bias frequency. This frequency is the required
|
||||||
|
|
|
@ -33,12 +33,12 @@ Required properties:
|
||||||
- i80-if-timings: timing configuration for lcd i80 interface support.
|
- i80-if-timings: timing configuration for lcd i80 interface support.
|
||||||
|
|
||||||
Optional Properties:
|
Optional Properties:
|
||||||
- samsung,power-domain: a phandle to DECON power domain node.
|
- power-domains: a phandle to DECON power domain node.
|
||||||
- display-timings: timing settings for DECON, as described in document [1].
|
- display-timings: timing settings for DECON, as described in document [1].
|
||||||
Can be used in case timings cannot be provided otherwise
|
Can be used in case timings cannot be provided otherwise
|
||||||
or to override timings provided by the panel.
|
or to override timings provided by the panel.
|
||||||
|
|
||||||
[1]: Documentation/devicetree/bindings/display/display-timing.txt
|
[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt
|
||||||
|
|
||||||
Example:
|
Example:
|
||||||
|
|
||||||
|
|
|
@ -83,7 +83,7 @@ in [2]. The following are properties specific to those nodes:
|
||||||
3 - for parallel output,
|
3 - for parallel output,
|
||||||
4 - for write-back interface
|
4 - for write-back interface
|
||||||
|
|
||||||
[1]: Documentation/devicetree/bindings/display/display-timing.txt
|
[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt
|
||||||
[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||||
|
|
||||||
Example:
|
Example:
|
||||||
|
|
|
@ -16,7 +16,7 @@ Required properties:
|
||||||
"clk_ade_core" for the ADE core clock.
|
"clk_ade_core" for the ADE core clock.
|
||||||
"clk_codec_jpeg" for the media NOC QoS clock, which use the same clock with
|
"clk_codec_jpeg" for the media NOC QoS clock, which use the same clock with
|
||||||
jpeg codec.
|
jpeg codec.
|
||||||
"clk_ade_pix" for the ADE pixel clok.
|
"clk_ade_pix" for the ADE pixel clock.
|
||||||
- assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks'
|
- assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks'
|
||||||
phandle + clock-specifier pairs.
|
phandle + clock-specifier pairs.
|
||||||
- assigned-clock-rates: clock rates, one for each entry in assigned-clocks.
|
- assigned-clock-rates: clock rates, one for each entry in assigned-clocks.
|
||||||
|
|
|
@ -9,7 +9,7 @@ Required properties:
|
||||||
|
|
||||||
Required nodes:
|
Required nodes:
|
||||||
- display: Phandle to a display node as described in
|
- display: Phandle to a display node as described in
|
||||||
Documentation/devicetree/bindings/display/display-timing.txt
|
Documentation/devicetree/bindings/display/panel/display-timing.txt
|
||||||
Additional, the display node has to define properties:
|
Additional, the display node has to define properties:
|
||||||
- bits-per-pixel: Bits per pixel
|
- bits-per-pixel: Bits per pixel
|
||||||
- fsl,pcr: LCDC PCR value
|
- fsl,pcr: LCDC PCR value
|
||||||
|
|
|
@ -1,29 +1,36 @@
|
||||||
Device-Tree bindings for HDMI Transmitter
|
Freescale i.MX6 DWC HDMI TX Encoder
|
||||||
|
===================================
|
||||||
|
|
||||||
HDMI Transmitter
|
The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
|
||||||
================
|
with a companion PHY IP.
|
||||||
|
|
||||||
|
These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
|
||||||
|
Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
|
||||||
|
following device-specific properties.
|
||||||
|
|
||||||
The HDMI Transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
|
|
||||||
with accompanying PHY IP.
|
|
||||||
|
|
||||||
Required properties:
|
Required properties:
|
||||||
- #address-cells : should be <1>
|
|
||||||
- #size-cells : should be <0>
|
|
||||||
- compatible : should be "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
|
|
||||||
- gpr : should be <&gpr>.
|
|
||||||
The phandle points to the iomuxc-gpr region containing the HDMI
|
|
||||||
multiplexer control register.
|
|
||||||
- clocks, clock-names : phandles to the HDMI iahb and isrf clocks, as described
|
|
||||||
in Documentation/devicetree/bindings/clock/clock-bindings.txt and
|
|
||||||
Documentation/devicetree/bindings/clock/imx6q-clock.txt.
|
|
||||||
- port@[0-4]: Up to four port nodes with endpoint definitions as defined in
|
|
||||||
Documentation/devicetree/bindings/media/video-interfaces.txt,
|
|
||||||
corresponding to the four inputs to the HDMI multiplexer.
|
|
||||||
|
|
||||||
Optional properties:
|
- compatible : Shall be one of "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
|
||||||
- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
|
- reg: See dw_hdmi.txt.
|
||||||
|
- interrupts: HDMI interrupt number
|
||||||
|
- clocks: See dw_hdmi.txt.
|
||||||
|
- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
|
||||||
|
- ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports,
|
||||||
|
numbered 0 to 3, corresponding to the four inputs of the HDMI multiplexer.
|
||||||
|
Each port shall have a single endpoint.
|
||||||
|
- gpr : Shall contain a phandle to the iomuxc-gpr region containing the HDMI
|
||||||
|
multiplexer control register.
|
||||||
|
|
||||||
example:
|
Optional properties
|
||||||
|
|
||||||
|
- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
|
||||||
|
or the functionally-reduced I2C master contained in the DWC HDMI. When
|
||||||
|
connected to a system I2C master this property contains a phandle to that
|
||||||
|
I2C master controller.
|
||||||
|
|
||||||
|
|
||||||
|
Example:
|
||||||
|
|
||||||
gpr: iomuxc-gpr@020e0000 {
|
gpr: iomuxc-gpr@020e0000 {
|
||||||
/* ... */
|
/* ... */
|
||||||
|
|
|
@ -64,7 +64,7 @@ Required properties:
|
||||||
Optional properties (required if display-timings are used):
|
Optional properties (required if display-timings are used):
|
||||||
- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
|
- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
|
||||||
- display-timings : A node that describes the display timings as defined in
|
- display-timings : A node that describes the display timings as defined in
|
||||||
Documentation/devicetree/bindings/display/display-timing.txt.
|
Documentation/devicetree/bindings/display/panel/display-timing.txt.
|
||||||
- fsl,data-mapping : should be "spwg" or "jeida"
|
- fsl,data-mapping : should be "spwg" or "jeida"
|
||||||
This describes how the color bits are laid out in the
|
This describes how the color bits are laid out in the
|
||||||
serialized LVDS signal.
|
serialized LVDS signal.
|
||||||
|
|
|
@ -55,7 +55,7 @@ Required properties (DMA function blocks):
|
||||||
"mediatek,<chip>-disp-rdma"
|
"mediatek,<chip>-disp-rdma"
|
||||||
"mediatek,<chip>-disp-wdma"
|
"mediatek,<chip>-disp-wdma"
|
||||||
- larb: Should contain a phandle pointing to the local arbiter device as defined
|
- larb: Should contain a phandle pointing to the local arbiter device as defined
|
||||||
in Documentation/devicetree/bindings/soc/mediatek/mediatek,smi-larb.txt
|
in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
|
||||||
- iommus: Should point to the respective IOMMU block with master port as
|
- iommus: Should point to the respective IOMMU block with master port as
|
||||||
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
|
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
|
||||||
for details.
|
for details.
|
||||||
|
|
|
@ -108,7 +108,7 @@ Optional properties:
|
||||||
- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
|
- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
|
||||||
regulator is wanted.
|
regulator is wanted.
|
||||||
|
|
||||||
[1] Documentation/devicetree/bindings/clocks/clock-bindings.txt
|
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||||
[2] Documentation/devicetree/bindings/graph.txt
|
[2] Documentation/devicetree/bindings/graph.txt
|
||||||
[3] Documentation/devicetree/bindings/media/video-interfaces.txt
|
[3] Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||||
[4] Documentation/devicetree/bindings/display/panel/
|
[4] Documentation/devicetree/bindings/display/panel/
|
||||||
|
|
|
@ -10,7 +10,7 @@ Required properties:
|
||||||
- interrupts: The interrupt signal from the eDP block.
|
- interrupts: The interrupt signal from the eDP block.
|
||||||
- power-domains: Should be <&mmcc MDSS_GDSC>.
|
- power-domains: Should be <&mmcc MDSS_GDSC>.
|
||||||
- clocks: device clocks
|
- clocks: device clocks
|
||||||
See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
|
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
|
||||||
- clock-names: the following clocks are required:
|
- clock-names: the following clocks are required:
|
||||||
* "core_clk"
|
* "core_clk"
|
||||||
* "iface_clk"
|
* "iface_clk"
|
||||||
|
|
|
@ -1,23 +1,19 @@
|
||||||
Qualcomm adreno/snapdragon GPU
|
Qualcomm adreno/snapdragon GPU
|
||||||
|
|
||||||
Required properties:
|
Required properties:
|
||||||
- compatible: "qcom,adreno-3xx"
|
- compatible: "qcom,adreno-XYZ.W", "qcom,adreno"
|
||||||
|
for example: "qcom,adreno-306.0", "qcom,adreno"
|
||||||
|
Note that you need to list the less specific "qcom,adreno" (since this
|
||||||
|
is what the device is matched on), in addition to the more specific
|
||||||
|
with the chip-id.
|
||||||
- reg: Physical base address and length of the controller's registers.
|
- reg: Physical base address and length of the controller's registers.
|
||||||
- interrupts: The interrupt signal from the gpu.
|
- interrupts: The interrupt signal from the gpu.
|
||||||
- clocks: device clocks
|
- clocks: device clocks
|
||||||
See ../clocks/clock-bindings.txt for details.
|
See ../clocks/clock-bindings.txt for details.
|
||||||
- clock-names: the following clocks are required:
|
- clock-names: the following clocks are required:
|
||||||
* "core_clk"
|
* "core"
|
||||||
* "iface_clk"
|
* "iface"
|
||||||
* "mem_iface_clk"
|
* "mem_iface"
|
||||||
- qcom,chipid: gpu chip-id. Note this may become optional for future
|
|
||||||
devices if we can reliably read the chipid from hw
|
|
||||||
- qcom,gpu-pwrlevels: list of operating points
|
|
||||||
- compatible: "qcom,gpu-pwrlevels"
|
|
||||||
- for each qcom,gpu-pwrlevel:
|
|
||||||
- qcom,gpu-freq: requested gpu clock speed
|
|
||||||
- NOTE: downstream android driver defines additional parameters to
|
|
||||||
configure memory bandwidth scaling per OPP.
|
|
||||||
|
|
||||||
Example:
|
Example:
|
||||||
|
|
||||||
|
@ -25,28 +21,18 @@ Example:
|
||||||
...
|
...
|
||||||
|
|
||||||
gpu: qcom,kgsl-3d0@4300000 {
|
gpu: qcom,kgsl-3d0@4300000 {
|
||||||
compatible = "qcom,adreno-3xx";
|
compatible = "qcom,adreno-320.2", "qcom,adreno";
|
||||||
reg = <0x04300000 0x20000>;
|
reg = <0x04300000 0x20000>;
|
||||||
reg-names = "kgsl_3d0_reg_memory";
|
reg-names = "kgsl_3d0_reg_memory";
|
||||||
interrupts = <GIC_SPI 80 0>;
|
interrupts = <GIC_SPI 80 0>;
|
||||||
interrupt-names = "kgsl_3d0_irq";
|
interrupt-names = "kgsl_3d0_irq";
|
||||||
clock-names =
|
clock-names =
|
||||||
"core_clk",
|
"core",
|
||||||
"iface_clk",
|
"iface",
|
||||||
"mem_iface_clk";
|
"mem_iface";
|
||||||
clocks =
|
clocks =
|
||||||
<&mmcc GFX3D_CLK>,
|
<&mmcc GFX3D_CLK>,
|
||||||
<&mmcc GFX3D_AHB_CLK>,
|
<&mmcc GFX3D_AHB_CLK>,
|
||||||
<&mmcc MMSS_IMEM_AHB_CLK>;
|
<&mmcc MMSS_IMEM_AHB_CLK>;
|
||||||
qcom,chipid = <0x03020100>;
|
|
||||||
qcom,gpu-pwrlevels {
|
|
||||||
compatible = "qcom,gpu-pwrlevels";
|
|
||||||
qcom,gpu-pwrlevel@0 {
|
|
||||||
qcom,gpu-freq = <450000000>;
|
|
||||||
};
|
|
||||||
qcom,gpu-pwrlevel@1 {
|
|
||||||
qcom,gpu-freq = <27000000>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
@ -49,7 +49,7 @@ Required properties:
|
||||||
* "hdmi_tx_l4"
|
* "hdmi_tx_l4"
|
||||||
- power-domains: Should be <&mmcc MDSS_GDSC>.
|
- power-domains: Should be <&mmcc MDSS_GDSC>.
|
||||||
- clocks: device clocks
|
- clocks: device clocks
|
||||||
See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
|
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
|
||||||
- core-vdda-supply: phandle to vdda regulator device node
|
- core-vdda-supply: phandle to vdda regulator device node
|
||||||
|
|
||||||
Example:
|
Example:
|
||||||
|
|
|
@ -0,0 +1,27 @@
|
||||||
|
Multi-Inno MI0283QT display panel
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: "multi-inno,mi0283qt".
|
||||||
|
|
||||||
|
The node for this driver must be a child node of a SPI controller, hence
|
||||||
|
all mandatory properties described in ../spi/spi-bus.txt must be specified.
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
- dc-gpios: D/C pin. The presence/absence of this GPIO determines
|
||||||
|
the panel interface mode (IM[3:0] pins):
|
||||||
|
- present: IM=x110 4-wire 8-bit data serial interface
|
||||||
|
- absent: IM=x101 3-wire 9-bit data serial interface
|
||||||
|
- reset-gpios: Reset pin
|
||||||
|
- power-supply: A regulator node for the supply voltage.
|
||||||
|
- backlight: phandle of the backlight device attached to the panel
|
||||||
|
- rotation: panel rotation in degrees counter clockwise (0,90,180,270)
|
||||||
|
|
||||||
|
Example:
|
||||||
|
mi0283qt@0{
|
||||||
|
compatible = "multi-inno,mi0283qt";
|
||||||
|
reg = <0>;
|
||||||
|
spi-max-frequency = <32000000>;
|
||||||
|
rotation = <90>;
|
||||||
|
dc-gpios = <&gpio 25 0>;
|
||||||
|
backlight = <&backlight>;
|
||||||
|
};
|
|
@ -0,0 +1,7 @@
|
||||||
|
BOE OPTOELECTRONICS TECHNOLOGY 10.1" WXGA TFT LCD panel
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: should be "boe,nv101wxmn51"
|
||||||
|
|
||||||
|
This binding is compatible with the simple-panel binding, which is specified
|
||||||
|
in simple-panel.txt in this directory.
|
|
@ -0,0 +1,7 @@
|
||||||
|
Netron-DY E231732 7.0" WSVGA TFT LCD panel
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: should be "netron-dy,e231732"
|
||||||
|
|
||||||
|
This binding is compatible with the simple-panel binding, which is specified
|
||||||
|
in simple-panel.txt in this directory.
|
|
@ -12,7 +12,7 @@ Optional properties:
|
||||||
|
|
||||||
Required nodes:
|
Required nodes:
|
||||||
- "panel-timing" containing video timings
|
- "panel-timing" containing video timings
|
||||||
(Documentation/devicetree/bindings/display/display-timing.txt)
|
(Documentation/devicetree/bindings/display/panel/display-timing.txt)
|
||||||
- Video port for DPI input
|
- Video port for DPI input
|
||||||
|
|
||||||
Example
|
Example
|
||||||
|
|
|
@ -0,0 +1,4 @@
|
||||||
|
Common display properties
|
||||||
|
-------------------------
|
||||||
|
|
||||||
|
- rotation: Display rotation in degrees counter clockwise (0,90,180,270)
|
|
@ -20,7 +20,7 @@ The device node can contain one 'port' child node with one child
|
||||||
'endpoint' node, according to the bindings defined in [3]. This
|
'endpoint' node, according to the bindings defined in [3]. This
|
||||||
node should describe panel's video bus.
|
node should describe panel's video bus.
|
||||||
|
|
||||||
[1]: Documentation/devicetree/bindings/display/display-timing.txt
|
[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt
|
||||||
[2]: Documentation/devicetree/bindings/spi/spi-bus.txt
|
[2]: Documentation/devicetree/bindings/spi/spi-bus.txt
|
||||||
[3]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
[3]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||||
|
|
||||||
|
|
|
@ -21,7 +21,7 @@ The device node can contain one 'port' child node with one child
|
||||||
'endpoint' node, according to the bindings defined in [2]. This
|
'endpoint' node, according to the bindings defined in [2]. This
|
||||||
node should describe panel's video bus.
|
node should describe panel's video bus.
|
||||||
|
|
||||||
[1]: Documentation/devicetree/bindings/display/display-timing.txt
|
[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt
|
||||||
[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||||
|
|
||||||
Example:
|
Example:
|
||||||
|
|
|
@ -0,0 +1,7 @@
|
||||||
|
Tianma Micro-electronics TM070JDHG30 7.0" WXGA TFT LCD panel
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: should be "tianma,tm070jdhg30"
|
||||||
|
|
||||||
|
This binding is compatible with the simple-panel binding, which is specified
|
||||||
|
in simple-panel.txt in this directory.
|
|
@ -35,7 +35,7 @@ Optional property for different chips:
|
||||||
Required elements: "grf"
|
Required elements: "grf"
|
||||||
|
|
||||||
For the below properties, please refer to Analogix DP binding document:
|
For the below properties, please refer to Analogix DP binding document:
|
||||||
* Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
|
* Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
|
||||||
- phys (required)
|
- phys (required)
|
||||||
- phy-names (required)
|
- phy-names (required)
|
||||||
- hpd-gpios (optional)
|
- hpd-gpios (optional)
|
||||||
|
|
|
@ -1,24 +1,39 @@
|
||||||
Rockchip specific extensions to the Synopsys Designware HDMI
|
Rockchip DWC HDMI TX Encoder
|
||||||
================================
|
============================
|
||||||
|
|
||||||
|
The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
|
||||||
|
with a companion PHY IP.
|
||||||
|
|
||||||
|
These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
|
||||||
|
Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
|
||||||
|
following device-specific properties.
|
||||||
|
|
||||||
|
|
||||||
Required properties:
|
Required properties:
|
||||||
- compatible: "rockchip,rk3288-dw-hdmi";
|
|
||||||
- reg: Physical base address and length of the controller's registers.
|
- compatible: Shall contain "rockchip,rk3288-dw-hdmi".
|
||||||
- clocks: phandle to hdmi iahb and isfr clocks.
|
- reg: See dw_hdmi.txt.
|
||||||
- clock-names: should be "iahb" "isfr"
|
- reg-io-width: See dw_hdmi.txt. Shall be 4.
|
||||||
- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
|
|
||||||
- interrupts: HDMI interrupt number
|
- interrupts: HDMI interrupt number
|
||||||
- ports: contain a port node with endpoint definitions as defined in
|
- clocks: See dw_hdmi.txt.
|
||||||
Documentation/devicetree/bindings/media/video-interfaces.txt. For
|
- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
|
||||||
vopb,set the reg = <0> and set the reg = <1> for vopl.
|
- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
|
||||||
- reg-io-width: the width of the reg:1,4, the value should be 4 on
|
corresponding to the video input of the controller. The port shall have two
|
||||||
rk3288 platform
|
endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
|
||||||
|
- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
|
||||||
|
|
||||||
Optional properties
|
Optional properties
|
||||||
- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
|
|
||||||
- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec"
|
- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
|
||||||
|
or the functionally-reduced I2C master contained in the DWC HDMI. When
|
||||||
|
connected to a system I2C master this property contains a phandle to that
|
||||||
|
I2C master controller.
|
||||||
|
- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
|
||||||
|
- clock-names: May contain "cec" as defined in dw_hdmi.txt.
|
||||||
|
|
||||||
|
|
||||||
Example:
|
Example:
|
||||||
|
|
||||||
hdmi: hdmi@ff980000 {
|
hdmi: hdmi@ff980000 {
|
||||||
compatible = "rockchip,rk3288-dw-hdmi";
|
compatible = "rockchip,rk3288-dw-hdmi";
|
||||||
reg = <0xff980000 0x20000>;
|
reg = <0xff980000 0x20000>;
|
||||||
|
|
|
@ -8,14 +8,15 @@ Required properties:
|
||||||
0x3c or 0x3d
|
0x3c or 0x3d
|
||||||
- pwm: Should contain the pwm to use according to the OF device tree PWM
|
- pwm: Should contain the pwm to use according to the OF device tree PWM
|
||||||
specification [0]. Only required for the ssd1307.
|
specification [0]. Only required for the ssd1307.
|
||||||
- reset-gpios: Should contain the GPIO used to reset the OLED display
|
|
||||||
- solomon,height: Height in pixel of the screen driven by the controller
|
- solomon,height: Height in pixel of the screen driven by the controller
|
||||||
- solomon,width: Width in pixel of the screen driven by the controller
|
- solomon,width: Width in pixel of the screen driven by the controller
|
||||||
- solomon,page-offset: Offset of pages (band of 8 pixels) that the screen is
|
- solomon,page-offset: Offset of pages (band of 8 pixels) that the screen is
|
||||||
mapped to.
|
mapped to.
|
||||||
|
|
||||||
Optional properties:
|
Optional properties:
|
||||||
- reset-active-low: Is the reset gpio is active on physical low?
|
- reset-gpios: The GPIO used to reset the OLED display, if available. See
|
||||||
|
Documentation/devicetree/bindings/gpio/gpio.txt for details.
|
||||||
|
- vbat-supply: The supply for VBAT
|
||||||
- solomon,segment-no-remap: Display needs normal (non-inverted) data column
|
- solomon,segment-no-remap: Display needs normal (non-inverted) data column
|
||||||
to segment mapping
|
to segment mapping
|
||||||
- solomon,com-seq: Display uses sequential COM pin configuration
|
- solomon,com-seq: Display uses sequential COM pin configuration
|
||||||
|
|
|
@ -15,7 +15,7 @@ Required properties:
|
||||||
- display-timings: typical videomode of lcd panel. Multiple video modes
|
- display-timings: typical videomode of lcd panel. Multiple video modes
|
||||||
can be listed if the panel supports multiple timings, but the 'native-mode'
|
can be listed if the panel supports multiple timings, but the 'native-mode'
|
||||||
should be the preferred/default resolution. Refer to
|
should be the preferred/default resolution. Refer to
|
||||||
Documentation/devicetree/bindings/display/display-timing.txt for display
|
Documentation/devicetree/bindings/display/panel/display-timing.txt for display
|
||||||
timing binding details.
|
timing binding details.
|
||||||
|
|
||||||
Optional properties:
|
Optional properties:
|
||||||
|
|
|
@ -49,6 +49,15 @@ Required properties:
|
||||||
"osc_clk"
|
"osc_clk"
|
||||||
"xclk"
|
"xclk"
|
||||||
|
|
||||||
|
* TV Encoder output device
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: should be "zte,zx296718-tvenc"
|
||||||
|
- reg: Physical base address and length of the TVENC device IO region
|
||||||
|
- zte,tvenc-power-control: the phandle to SYSCTRL block followed by two
|
||||||
|
integer cells. The first cell is the offset of SYSCTRL register used
|
||||||
|
to control TV Encoder DAC power, and the second cell is the bit mask.
|
||||||
|
|
||||||
Example:
|
Example:
|
||||||
|
|
||||||
vou: vou@1440000 {
|
vou: vou@1440000 {
|
||||||
|
@ -81,4 +90,10 @@ vou: vou@1440000 {
|
||||||
<&topcrm HDMI_XCLK>;
|
<&topcrm HDMI_XCLK>;
|
||||||
clock-names = "osc_cec", "osc_clk", "xclk";
|
clock-names = "osc_cec", "osc_clk", "xclk";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
tvenc: tvenc@2000 {
|
||||||
|
compatible = "zte,zx296718-tvenc";
|
||||||
|
reg = <0x2000 0x1000>;
|
||||||
|
zte,tvenc-power-control = <&sysctrl 0x170 0x10>;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
|
@ -40,8 +40,7 @@ Example:
|
||||||
|
|
||||||
DMA clients connected to the STM32 DMA controller must use the format
|
DMA clients connected to the STM32 DMA controller must use the format
|
||||||
described in the dma.txt file, using a five-cell specifier for each
|
described in the dma.txt file, using a five-cell specifier for each
|
||||||
channel: a phandle plus four integer cells.
|
channel: a phandle to the DMA controller plus the following four integer cells:
|
||||||
The four cells in order are:
|
|
||||||
|
|
||||||
1. The channel id
|
1. The channel id
|
||||||
2. The request line number
|
2. The request line number
|
||||||
|
@ -61,7 +60,7 @@ The four cells in order are:
|
||||||
0x1: medium
|
0x1: medium
|
||||||
0x2: high
|
0x2: high
|
||||||
0x3: very high
|
0x3: very high
|
||||||
5. A 32bit mask specifying the DMA FIFO threshold configuration which are device
|
4. A 32bit mask specifying the DMA FIFO threshold configuration which are device
|
||||||
dependent:
|
dependent:
|
||||||
-bit 0-1: Fifo threshold
|
-bit 0-1: Fifo threshold
|
||||||
0x0: 1/4 full FIFO
|
0x0: 1/4 full FIFO
|
||||||
|
|
|
@ -10,6 +10,8 @@ Required properties:
|
||||||
|
|
||||||
"catalyst,24c32"
|
"catalyst,24c32"
|
||||||
|
|
||||||
|
"microchip,24c128"
|
||||||
|
|
||||||
"ramtron,24c64"
|
"ramtron,24c64"
|
||||||
|
|
||||||
"renesas,r1ex24002"
|
"renesas,r1ex24002"
|
||||||
|
|
|
@ -0,0 +1,24 @@
|
||||||
|
Cortina Systems Gemini GPIO Controller
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
|
||||||
|
- compatible : Must be "cortina,gemini-gpio"
|
||||||
|
- reg : Should contain registers location and length
|
||||||
|
- interrupts : Should contain the interrupt line for the GPIO block
|
||||||
|
- gpio-controller : marks this as a GPIO controller
|
||||||
|
- #gpio-cells : Should be 2, see gpio/gpio.txt
|
||||||
|
- interrupt-controller : marks this as an interrupt controller
|
||||||
|
- #interrupt-cells : a standard two-cell interrupt flag, see
|
||||||
|
interrupt-controller/interrupts.txt
|
||||||
|
|
||||||
|
Example:
|
||||||
|
|
||||||
|
gpio@4d000000 {
|
||||||
|
compatible = "cortina,gemini-gpio";
|
||||||
|
reg = <0x4d000000 0x100>;
|
||||||
|
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
};
|
|
@ -29,6 +29,10 @@ Required properties:
|
||||||
onsemi,pca9654
|
onsemi,pca9654
|
||||||
exar,xra1202
|
exar,xra1202
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
- reset-gpios: GPIO specification for the RESET input. This is an
|
||||||
|
active low signal to the PCA953x.
|
||||||
|
|
||||||
Example:
|
Example:
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -187,10 +187,10 @@ gpio-controller's driver probe function.
|
||||||
|
|
||||||
Each GPIO hog definition is represented as a child node of the GPIO controller.
|
Each GPIO hog definition is represented as a child node of the GPIO controller.
|
||||||
Required properties:
|
Required properties:
|
||||||
- gpio-hog: A property specifying that this child node represent a GPIO hog.
|
- gpio-hog: A property specifying that this child node represents a GPIO hog.
|
||||||
- gpios: Store the GPIO information (id, flags, ...). Shall contain the
|
- gpios: Store the GPIO information (id, flags, ...) for each GPIO to
|
||||||
number of cells specified in its parent node (GPIO controller
|
affect. Shall contain an integer multiple of the number of cells
|
||||||
node).
|
specified in its parent node (GPIO controller node).
|
||||||
Only one of the following properties scanned in the order shown below.
|
Only one of the following properties scanned in the order shown below.
|
||||||
This means that when multiple properties are present they will be searched
|
This means that when multiple properties are present they will be searched
|
||||||
in the order presented below and the first match is taken as the intended
|
in the order presented below and the first match is taken as the intended
|
||||||
|
|
|
@ -0,0 +1,81 @@
|
||||||
|
ARM Mali Utgard GPU
|
||||||
|
===================
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible
|
||||||
|
* Must be one of the following:
|
||||||
|
+ "arm,mali-300"
|
||||||
|
+ "arm,mali-400"
|
||||||
|
+ "arm,mali-450"
|
||||||
|
* And, optionally, one of the vendor specific compatible:
|
||||||
|
+ allwinner,sun4i-a10-mali
|
||||||
|
+ allwinner,sun7i-a20-mali
|
||||||
|
+ amlogic,meson-gxbb-mali
|
||||||
|
+ amlogic,meson-gxl-mali
|
||||||
|
+ stericsson,db8500-mali
|
||||||
|
|
||||||
|
- reg: Physical base address and length of the GPU registers
|
||||||
|
|
||||||
|
- interrupts: an entry for each entry in interrupt-names.
|
||||||
|
See ../interrupt-controller/interrupts.txt for details.
|
||||||
|
|
||||||
|
- interrupt-names:
|
||||||
|
* ppX: Pixel Processor X interrupt (X from 0 to 7)
|
||||||
|
* ppmmuX: Pixel Processor X MMU interrupt (X from 0 to 7)
|
||||||
|
* pp: Pixel Processor broadcast interrupt (mali-450 only)
|
||||||
|
* gp: Geometry Processor interrupt
|
||||||
|
* gpmmu: Geometry Processor MMU interrupt
|
||||||
|
|
||||||
|
- clocks: an entry for each entry in clock-names
|
||||||
|
- clock-names:
|
||||||
|
* bus: bus clock for the GPU
|
||||||
|
* core: clock driving the GPU itself
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
- interrupt-names and interrupts:
|
||||||
|
* pmu: Power Management Unit interrupt, if implemented in hardware
|
||||||
|
|
||||||
|
Vendor-specific bindings
|
||||||
|
------------------------
|
||||||
|
|
||||||
|
The Mali GPU is integrated very differently from one SoC to
|
||||||
|
another. In order to accomodate those differences, you have the option
|
||||||
|
to specify one more vendor-specific compatible, among:
|
||||||
|
|
||||||
|
- allwinner,sun4i-a10-mali
|
||||||
|
Required properties:
|
||||||
|
* resets: phandle to the reset line for the GPU
|
||||||
|
|
||||||
|
- allwinner,sun7i-a20-mali
|
||||||
|
Required properties:
|
||||||
|
* resets: phandle to the reset line for the GPU
|
||||||
|
|
||||||
|
- stericsson,db8500-mali
|
||||||
|
Required properties:
|
||||||
|
* interrupt-names and interrupts:
|
||||||
|
+ combined: combined interrupt of all of the above lines
|
||||||
|
|
||||||
|
Example:
|
||||||
|
|
||||||
|
mali: gpu@1c40000 {
|
||||||
|
compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
|
||||||
|
reg = <0x01c40000 0x10000>;
|
||||||
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
interrupt-names = "gp",
|
||||||
|
"gpmmu",
|
||||||
|
"pp0",
|
||||||
|
"ppmmu0",
|
||||||
|
"pp1",
|
||||||
|
"ppmmu1",
|
||||||
|
"pmu";
|
||||||
|
clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
|
||||||
|
clock-names = "bus", "core";
|
||||||
|
resets = <&ccu RST_BUS_GPU>;
|
||||||
|
};
|
||||||
|
|
|
@ -0,0 +1,38 @@
|
||||||
|
TI ADC128D818 ADC System Monitor With Temperature Sensor
|
||||||
|
--------------------------------------------------------
|
||||||
|
|
||||||
|
Operation modes:
|
||||||
|
|
||||||
|
- Mode 0: 7 single-ended voltage readings (IN0-IN6),
|
||||||
|
1 temperature reading (internal)
|
||||||
|
- Mode 1: 8 single-ended voltage readings (IN0-IN7),
|
||||||
|
no temperature
|
||||||
|
- Mode 2: 4 pseudo-differential voltage readings
|
||||||
|
(IN0-IN1, IN3-IN2, IN4-IN5, IN7-IN6),
|
||||||
|
1 temperature reading (internal)
|
||||||
|
- Mode 3: 4 single-ended voltage readings (IN0-IN3),
|
||||||
|
2 pseudo-differential voltage readings
|
||||||
|
(IN4-IN5, IN7-IN6),
|
||||||
|
1 temperature reading (internal)
|
||||||
|
|
||||||
|
If no operation mode is configured via device tree, the driver keeps the
|
||||||
|
currently active chip operation mode (default is mode 0).
|
||||||
|
|
||||||
|
|
||||||
|
Required node properties:
|
||||||
|
|
||||||
|
- compatible: must be set to "ti,adc128d818"
|
||||||
|
- reg: I2C address of the device
|
||||||
|
|
||||||
|
Optional node properties:
|
||||||
|
|
||||||
|
- ti,mode: Operation mode (see above).
|
||||||
|
|
||||||
|
|
||||||
|
Example (operation mode 2):
|
||||||
|
|
||||||
|
adc128d818@1d {
|
||||||
|
compatible = "ti,adc128d818";
|
||||||
|
reg = <0x1d>;
|
||||||
|
ti,mode = <2>;
|
||||||
|
};
|
|
@ -4,6 +4,7 @@ Required properties:
|
||||||
- compatible: one of
|
- compatible: one of
|
||||||
"ti,lm70"
|
"ti,lm70"
|
||||||
"ti,tmp121"
|
"ti,tmp121"
|
||||||
|
"ti,tmp122"
|
||||||
"ti,lm71"
|
"ti,lm71"
|
||||||
"ti,lm74"
|
"ti,lm74"
|
||||||
|
|
||||||
|
|
|
@ -33,6 +33,11 @@ Optional properties:
|
||||||
LM90 "-ALERT" pin output.
|
LM90 "-ALERT" pin output.
|
||||||
See interrupt-controller/interrupts.txt for the format.
|
See interrupt-controller/interrupts.txt for the format.
|
||||||
|
|
||||||
|
- #thermal-sensor-cells: should be set to 1. See thermal/thermal.txt for
|
||||||
|
details. See <include/dt-bindings/thermal/lm90.h> for the
|
||||||
|
definition of the local, remote and 2nd remote sensor index
|
||||||
|
constants.
|
||||||
|
|
||||||
Example LM90 node:
|
Example LM90 node:
|
||||||
|
|
||||||
temp-sensor {
|
temp-sensor {
|
||||||
|
@ -41,4 +46,5 @@ temp-sensor {
|
||||||
vcc-supply = <&palmas_ldo6_reg>;
|
vcc-supply = <&palmas_ldo6_reg>;
|
||||||
interrupt-parent = <&gpio>;
|
interrupt-parent = <&gpio>;
|
||||||
interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_LOW>;
|
interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
#thermal-sensor-cells = <1>;
|
||||||
}
|
}
|
||||||
|
|
|
@ -0,0 +1,19 @@
|
||||||
|
Sensirion SHT15 Humidity and Temperature Sensor
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
|
||||||
|
- "compatible": must be "sensirion,sht15".
|
||||||
|
- "data-gpios": GPIO connected to the data line.
|
||||||
|
- "clk-gpios": GPIO connected to the clock line.
|
||||||
|
- "vcc-supply": regulator that drives the VCC pin.
|
||||||
|
|
||||||
|
Example:
|
||||||
|
|
||||||
|
sensor {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&pinctrl_sensor>;
|
||||||
|
compatible = "sensirion,sht15";
|
||||||
|
clk-gpios = <&gpio4 12 0>;
|
||||||
|
data-gpios = <&gpio4 13 0>;
|
||||||
|
vcc-supply = <®_sht15>;
|
||||||
|
};
|
|
@ -0,0 +1,15 @@
|
||||||
|
* STTS751 thermometer.
|
||||||
|
|
||||||
|
Required node properties:
|
||||||
|
- compatible: "stts751"
|
||||||
|
- reg: I2C bus address of the device
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
- smbus-timeout-disable: when set, the smbus timeout function will be disabled
|
||||||
|
|
||||||
|
Example stts751 node:
|
||||||
|
|
||||||
|
temp-sensor {
|
||||||
|
compatible = "stts751";
|
||||||
|
reg = <0x48>;
|
||||||
|
}
|
|
@ -19,7 +19,14 @@ Optional Properties:
|
||||||
- i2c-mux-idle-disconnect: Boolean; if defined, forces mux to disconnect all
|
- i2c-mux-idle-disconnect: Boolean; if defined, forces mux to disconnect all
|
||||||
children in idle state. This is necessary for example, if there are several
|
children in idle state. This is necessary for example, if there are several
|
||||||
multiplexers on the bus and the devices behind them use same I2C addresses.
|
multiplexers on the bus and the devices behind them use same I2C addresses.
|
||||||
|
- interrupt-parent: Phandle for the interrupt controller that services
|
||||||
|
interrupts for this device.
|
||||||
|
- interrupts: Interrupt mapping for IRQ.
|
||||||
|
- interrupt-controller: Marks the device node as an interrupt controller.
|
||||||
|
- #interrupt-cells : Should be two.
|
||||||
|
- first cell is the pin number
|
||||||
|
- second cell is used to specify flags.
|
||||||
|
See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
|
||||||
|
|
||||||
Example:
|
Example:
|
||||||
|
|
||||||
|
@ -29,6 +36,11 @@ Example:
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
reg = <0x74>;
|
reg = <0x74>;
|
||||||
|
|
||||||
|
interrupt-parent = <&ipic>;
|
||||||
|
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
|
||||||
i2c@2 {
|
i2c@2 {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
|
|
@ -10,6 +10,7 @@ Required properties:
|
||||||
- "renesas,iic-r8a7793" (R-Car M2-N)
|
- "renesas,iic-r8a7793" (R-Car M2-N)
|
||||||
- "renesas,iic-r8a7794" (R-Car E2)
|
- "renesas,iic-r8a7794" (R-Car E2)
|
||||||
- "renesas,iic-r8a7795" (R-Car H3)
|
- "renesas,iic-r8a7795" (R-Car H3)
|
||||||
|
- "renesas,iic-r8a7796" (R-Car M3-W)
|
||||||
- "renesas,iic-sh73a0" (SH-Mobile AG5)
|
- "renesas,iic-sh73a0" (SH-Mobile AG5)
|
||||||
- "renesas,rcar-gen2-iic" (generic R-Car Gen2 compatible device)
|
- "renesas,rcar-gen2-iic" (generic R-Car Gen2 compatible device)
|
||||||
- "renesas,rcar-gen3-iic" (generic R-Car Gen3 compatible device)
|
- "renesas,rcar-gen3-iic" (generic R-Car Gen3 compatible device)
|
||||||
|
|
|
@ -0,0 +1,33 @@
|
||||||
|
* I2C controller embedded in STMicroelectronics STM32 I2C platform
|
||||||
|
|
||||||
|
Required properties :
|
||||||
|
- compatible : Must be "st,stm32f4-i2c"
|
||||||
|
- reg : Offset and length of the register set for the device
|
||||||
|
- interrupts : Must contain the interrupt id for I2C event and then the
|
||||||
|
interrupt id for I2C error.
|
||||||
|
- resets: Must contain the phandle to the reset controller.
|
||||||
|
- clocks: Must contain the input clock of the I2C instance.
|
||||||
|
- A pinctrl state named "default" must be defined to set pins in mode of
|
||||||
|
operation for I2C transfer
|
||||||
|
- #address-cells = <1>;
|
||||||
|
- #size-cells = <0>;
|
||||||
|
|
||||||
|
Optional properties :
|
||||||
|
- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
|
||||||
|
the default 100 kHz frequency will be used. As only Normal and Fast modes
|
||||||
|
are supported, possible values are 100000 and 400000.
|
||||||
|
|
||||||
|
Example :
|
||||||
|
|
||||||
|
i2c@40005400 {
|
||||||
|
compatible = "st,stm32f4-i2c";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
reg = <0x40005400 0x400>;
|
||||||
|
interrupts = <31>,
|
||||||
|
<32>;
|
||||||
|
resets = <&rcc 277>;
|
||||||
|
clocks = <&rcc 0 149>;
|
||||||
|
pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
};
|
|
@ -0,0 +1,42 @@
|
||||||
|
NVIDIA Tegra186 BPMP I2C controller
|
||||||
|
|
||||||
|
In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW
|
||||||
|
devices, such as the I2C controller for the power management I2C bus. Software
|
||||||
|
running on other CPUs must perform IPC to the BPMP in order to execute
|
||||||
|
transactions on that I2C bus. This binding describes an I2C bus that is
|
||||||
|
accessed in such a fashion.
|
||||||
|
|
||||||
|
The BPMP I2C node must be located directly inside the main BPMP node. See
|
||||||
|
../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
|
||||||
|
|
||||||
|
This node represents an I2C controller. See ../i2c/i2c.txt for details of the
|
||||||
|
core I2C binding.
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible:
|
||||||
|
Array of strings.
|
||||||
|
One of:
|
||||||
|
- "nvidia,tegra186-bpmp-i2c".
|
||||||
|
- #address-cells: Address cells for I2C device address.
|
||||||
|
Single-cell integer.
|
||||||
|
Must be <1>.
|
||||||
|
- #size-cells:
|
||||||
|
Single-cell integer.
|
||||||
|
Must be <0>.
|
||||||
|
- nvidia,bpmp-bus-id:
|
||||||
|
Single-cell integer.
|
||||||
|
Indicates the I2C bus number this DT node represent, as defined by the
|
||||||
|
BPMP firmware.
|
||||||
|
|
||||||
|
Example:
|
||||||
|
|
||||||
|
bpmp {
|
||||||
|
...
|
||||||
|
|
||||||
|
i2c {
|
||||||
|
compatible = "nvidia,tegra186-bpmp-i2c";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
nvidia,bpmp-bus-id = <5>;
|
||||||
|
};
|
||||||
|
};
|
|
@ -36,6 +36,7 @@ dallas,ds1775 Tiny Digital Thermometer and Thermostat
|
||||||
dallas,ds3232 Extremely Accurate I²C RTC with Integrated Crystal and SRAM
|
dallas,ds3232 Extremely Accurate I²C RTC with Integrated Crystal and SRAM
|
||||||
dallas,ds4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O
|
dallas,ds4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O
|
||||||
dallas,ds75 Digital Thermometer and Thermostat
|
dallas,ds75 Digital Thermometer and Thermostat
|
||||||
|
devantech,srf08 Devantech SRF08 ultrasonic ranger
|
||||||
dlg,da9053 DA9053: flexible system level PMIC with multicore support
|
dlg,da9053 DA9053: flexible system level PMIC with multicore support
|
||||||
dlg,da9063 DA9063: system PMIC for quad-core application processors
|
dlg,da9063 DA9063: system PMIC for quad-core application processors
|
||||||
domintech,dmard09 DMARD09: 3-axis Accelerometer
|
domintech,dmard09 DMARD09: 3-axis Accelerometer
|
||||||
|
|
|
@ -5,7 +5,7 @@ that apply in on the generic device (independent from the bus).
|
||||||
|
|
||||||
|
|
||||||
Required properties for the SPI bindings:
|
Required properties for the SPI bindings:
|
||||||
- compatible: should be set to "st,lis3lv02d_spi"
|
- compatible: should be set to "st,lis3lv02d-spi"
|
||||||
- reg: the chipselect index
|
- reg: the chipselect index
|
||||||
- spi-max-frequency: maximal bus speed, should be set to 1000000 unless
|
- spi-max-frequency: maximal bus speed, should be set to 1000000 unless
|
||||||
constrained by external circuitry
|
constrained by external circuitry
|
||||||
|
|
|
@ -0,0 +1,32 @@
|
||||||
|
* Amlogic Meson SAR (Successive Approximation Register) A/D converter
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: depending on the SoC this should be one of:
|
||||||
|
- "amlogic,meson-gxbb-saradc" for GXBB
|
||||||
|
- "amlogic,meson-gxl-saradc" for GXL
|
||||||
|
- "amlogic,meson-gxm-saradc" for GXM
|
||||||
|
along with the generic "amlogic,meson-saradc"
|
||||||
|
- reg: the physical base address and length of the registers
|
||||||
|
- clocks: phandle and clock identifier (see clock-names)
|
||||||
|
- clock-names: mandatory clocks:
|
||||||
|
- "clkin" for the reference clock (typically XTAL)
|
||||||
|
- "core" for the SAR ADC core clock
|
||||||
|
optional clocks:
|
||||||
|
- "sana" for the analog clock
|
||||||
|
- "adc_clk" for the ADC (sampling) clock
|
||||||
|
- "adc_sel" for the ADC (sampling) clock mux
|
||||||
|
- vref-supply: the regulator supply for the ADC reference voltage
|
||||||
|
- #io-channel-cells: must be 1, see ../iio-bindings.txt
|
||||||
|
|
||||||
|
Example:
|
||||||
|
saradc: adc@8680 {
|
||||||
|
compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
|
||||||
|
#io-channel-cells = <1>;
|
||||||
|
reg = <0x0 0x8680 0x0 0x34>;
|
||||||
|
clocks = <&xtal>,
|
||||||
|
<&clkc CLKID_SAR_ADC>,
|
||||||
|
<&clkc CLKID_SANA>,
|
||||||
|
<&clkc CLKID_SAR_ADC_CLK>,
|
||||||
|
<&clkc CLKID_SAR_ADC_SEL>;
|
||||||
|
clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
|
||||||
|
};
|
|
@ -0,0 +1,18 @@
|
||||||
|
* AVIA HX711 ADC chip for weight cells
|
||||||
|
Bit-banging driver
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: Should be "avia,hx711"
|
||||||
|
- sck-gpios: Definition of the GPIO for the clock
|
||||||
|
- dout-gpios: Definition of the GPIO for data-out
|
||||||
|
See Documentation/devicetree/bindings/gpio/gpio.txt
|
||||||
|
- avdd-supply: Definition of the regulator used as analog supply
|
||||||
|
|
||||||
|
Example:
|
||||||
|
weight@0 {
|
||||||
|
compatible = "avia,hx711";
|
||||||
|
sck-gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
|
||||||
|
dout-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
|
||||||
|
avdd-suppy = <&avdd>;
|
||||||
|
};
|
||||||
|
|
|
@ -0,0 +1,18 @@
|
||||||
|
* Maxim max11100 Analog to Digital Converter (ADC)
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: Should be "maxim,max11100"
|
||||||
|
- reg: the adc unit address
|
||||||
|
- vref-supply: phandle to the regulator that provides reference voltage
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
- spi-max-frequency: SPI maximum frequency
|
||||||
|
|
||||||
|
Example:
|
||||||
|
|
||||||
|
max11100: adc@0 {
|
||||||
|
compatible = "maxim,max11100";
|
||||||
|
reg = <0>;
|
||||||
|
vref-supply = <&adc0_vref>;
|
||||||
|
spi-max-frequency = <240000>;
|
||||||
|
};
|
|
@ -0,0 +1,149 @@
|
||||||
|
Qualcomm's PM8xxx voltage XOADC
|
||||||
|
|
||||||
|
The Qualcomm PM8xxx PMICs contain a HK/XO ADC (Housekeeping/Crystal
|
||||||
|
oscillator ADC) encompassing PM8018, PM8038, PM8058 and PM8921.
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
|
||||||
|
- compatible: should be one of:
|
||||||
|
"qcom,pm8018-adc"
|
||||||
|
"qcom,pm8038-adc"
|
||||||
|
"qcom,pm8058-adc"
|
||||||
|
"qcom,pm8921-adc"
|
||||||
|
|
||||||
|
- reg: should contain the ADC base address in the PMIC, typically
|
||||||
|
0x197.
|
||||||
|
|
||||||
|
- xoadc-ref-supply: should reference a regulator that can supply
|
||||||
|
a reference voltage on demand. The reference voltage may vary
|
||||||
|
with PMIC variant but is typically something like 2.2 or 1.8V.
|
||||||
|
|
||||||
|
The following required properties are standard for IO channels, see
|
||||||
|
iio-bindings.txt for more details:
|
||||||
|
|
||||||
|
- #address-cells: should be set to <1>
|
||||||
|
|
||||||
|
- #size-cells: should be set to <0>
|
||||||
|
|
||||||
|
- #io-channel-cells: should be set to <1>
|
||||||
|
|
||||||
|
- interrupts: should refer to the parent PMIC interrupt controller
|
||||||
|
and reference the proper ADC interrupt.
|
||||||
|
|
||||||
|
Required subnodes:
|
||||||
|
|
||||||
|
The ADC channels are configured as subnodes of the ADC. Since some of
|
||||||
|
them are used for calibrating the ADC, these nodes are compulsory:
|
||||||
|
|
||||||
|
adc-channel@c {
|
||||||
|
reg = <0x0c>;
|
||||||
|
};
|
||||||
|
|
||||||
|
adc-channel@d {
|
||||||
|
reg = <0x0d>;
|
||||||
|
};
|
||||||
|
|
||||||
|
adc-channel@f {
|
||||||
|
reg = <0x0f>;
|
||||||
|
};
|
||||||
|
|
||||||
|
These three nodes are used for absolute and ratiometric calibration
|
||||||
|
and only need to have these reg values: they are by hardware definition
|
||||||
|
1:1 ratio converters that sample 625, 1250 and 0 milliV and create
|
||||||
|
an interpolation calibration for all other ADCs.
|
||||||
|
|
||||||
|
Optional subnodes: any channels other than channel 0x0c, 0x0d and
|
||||||
|
0x0f are optional.
|
||||||
|
|
||||||
|
Required channel node properties:
|
||||||
|
|
||||||
|
- reg: should contain the hardware channel number in the range
|
||||||
|
0 .. 0x0f (4 bits). The hardware only supports 16 channels.
|
||||||
|
|
||||||
|
Optional channel node properties:
|
||||||
|
|
||||||
|
- qcom,decimation:
|
||||||
|
Value type: <u32>
|
||||||
|
Definition: This parameter is used to decrease the ADC sampling rate.
|
||||||
|
Quicker measurements can be made by reducing the decimation ratio.
|
||||||
|
Valid values are 512, 1024, 2048, 4096.
|
||||||
|
If the property is not found, a default value of 512 will be used.
|
||||||
|
|
||||||
|
- qcom,ratiometric:
|
||||||
|
Value type: <u32>
|
||||||
|
Definition: Channel calibration type. If this property is specified
|
||||||
|
VADC will use a special voltage references for channel
|
||||||
|
calibration. The available references are specified in the
|
||||||
|
as a u32 value setting (see below) and it is compulsory
|
||||||
|
to also specify this reference if ratiometric calibration
|
||||||
|
is selected.
|
||||||
|
|
||||||
|
If the property is not found, the channel will be
|
||||||
|
calibrated with the 0.625V and 1.25V reference channels, also
|
||||||
|
known as an absolute calibration.
|
||||||
|
The reference voltage pairs when using ratiometric calibration:
|
||||||
|
0 = XO_IN/XOADC_GND
|
||||||
|
1 = PMIC_IN/XOADC_GND
|
||||||
|
2 = PMIC_IN/BMS_CSP
|
||||||
|
3 (invalid)
|
||||||
|
4 = XOADC_GND/XOADC_GND
|
||||||
|
5 = XOADC_VREF/XOADC_GND
|
||||||
|
|
||||||
|
Example:
|
||||||
|
|
||||||
|
xoadc: xoadc@197 {
|
||||||
|
compatible = "qcom,pm8058-adc";
|
||||||
|
reg = <0x197>;
|
||||||
|
interrupt-parent = <&pm8058>;
|
||||||
|
interrupts = <76 1>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
#io-channel-cells = <1>;
|
||||||
|
|
||||||
|
vcoin: adc-channel@0 {
|
||||||
|
reg = <0x00>;
|
||||||
|
};
|
||||||
|
vbat: adc-channel@1 {
|
||||||
|
reg = <0x01>;
|
||||||
|
};
|
||||||
|
dcin: adc-channel@2 {
|
||||||
|
reg = <0x02>;
|
||||||
|
};
|
||||||
|
ichg: adc-channel@3 {
|
||||||
|
reg = <0x03>;
|
||||||
|
};
|
||||||
|
vph_pwr: adc-channel@4 {
|
||||||
|
reg = <0x04>;
|
||||||
|
};
|
||||||
|
usb_vbus: adc-channel@a {
|
||||||
|
reg = <0x0a>;
|
||||||
|
};
|
||||||
|
die_temp: adc-channel@b {
|
||||||
|
reg = <0x0b>;
|
||||||
|
};
|
||||||
|
ref_625mv: adc-channel@c {
|
||||||
|
reg = <0x0c>;
|
||||||
|
};
|
||||||
|
ref_1250mv: adc-channel@d {
|
||||||
|
reg = <0x0d>;
|
||||||
|
};
|
||||||
|
ref_325mv: adc-channel@e {
|
||||||
|
reg = <0x0e>;
|
||||||
|
};
|
||||||
|
ref_muxoff: adc-channel@f {
|
||||||
|
reg = <0x0f>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
/* IIO client node */
|
||||||
|
iio-hwmon {
|
||||||
|
compatible = "iio-hwmon";
|
||||||
|
io-channels = <&xoadc 0x01>, /* Battery */
|
||||||
|
<&xoadc 0x02>, /* DC in (charger) */
|
||||||
|
<&xoadc 0x04>, /* VPH the main system voltage */
|
||||||
|
<&xoadc 0x0b>, /* Die temperature */
|
||||||
|
<&xoadc 0x0c>, /* Reference voltage 1.25V */
|
||||||
|
<&xoadc 0x0d>, /* Reference voltage 0.625V */
|
||||||
|
<&xoadc 0x0e>; /* Reference voltage 0.325V */
|
||||||
|
};
|
|
@ -0,0 +1,99 @@
|
||||||
|
* Renesas RCar GyroADC device driver
|
||||||
|
|
||||||
|
The GyroADC block is a reduced SPI block with up to 8 chipselect lines,
|
||||||
|
which supports the SPI protocol of a selected few SPI ADCs. The SPI ADCs
|
||||||
|
are sampled by the GyroADC block in a round-robin fashion and the result
|
||||||
|
presented in the GyroADC registers.
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: Should be "<soc-specific>", "renesas,rcar-gyroadc".
|
||||||
|
The <soc-specific> should be one of:
|
||||||
|
renesas,r8a7791-gyroadc - for the GyroADC block present
|
||||||
|
in r8a7791 SoC
|
||||||
|
renesas,r8a7792-gyroadc - for the GyroADC with interrupt
|
||||||
|
block present in r8a7792 SoC
|
||||||
|
- reg: Address and length of the register set for the device
|
||||||
|
- clocks: References to all the clocks specified in the clock-names
|
||||||
|
property as specified in
|
||||||
|
Documentation/devicetree/bindings/clock/clock-bindings.txt.
|
||||||
|
- clock-names: Shall contain "fck" and "if". The "fck" is the GyroADC block
|
||||||
|
clock, the "if" is the interface clock.
|
||||||
|
- power-domains: Must contain a reference to the PM domain, if available.
|
||||||
|
- #address-cells: Should be <1> (setting for the subnodes) for all ADCs
|
||||||
|
except for "fujitsu,mb88101a". Should be <0> (setting for
|
||||||
|
only subnode) for "fujitsu,mb88101a".
|
||||||
|
- #size-cells: Should be <0> (setting for the subnodes)
|
||||||
|
|
||||||
|
Sub-nodes:
|
||||||
|
You must define subnode(s) which select the connected ADC type and reference
|
||||||
|
voltage for the GyroADC channels.
|
||||||
|
|
||||||
|
Required properties for subnodes:
|
||||||
|
- compatible: Should be either of:
|
||||||
|
"fujitsu,mb88101a"
|
||||||
|
- Fujitsu MB88101A compatible mode,
|
||||||
|
12bit sampling, up to 4 channels can be sampled in
|
||||||
|
round-robin fashion. One Fujitsu chip supplies four
|
||||||
|
GyroADC channels with data as it contains four ADCs
|
||||||
|
on the chip and thus for 4-channel operation, single
|
||||||
|
MB88101A is required. The Cx chipselect lines of the
|
||||||
|
MB88101A connect directly to two CHS lines of the
|
||||||
|
GyroADC, no demuxer is required. The data out line
|
||||||
|
of each MB88101A connects to a shared input pin of
|
||||||
|
the GyroADC.
|
||||||
|
"ti,adcs7476" or "ti,adc121" or "adi,ad7476"
|
||||||
|
- TI ADCS7476 / TI ADC121 / ADI AD7476 compatible mode,
|
||||||
|
15bit sampling, up to 8 channels can be sampled in
|
||||||
|
round-robin fashion. One TI/ADI chip supplies single
|
||||||
|
ADC channel with data, thus for 8-channel operation,
|
||||||
|
8 chips are required. A 3:8 chipselect demuxer is
|
||||||
|
required to connect the nCS line of the TI/ADI chips
|
||||||
|
to the GyroADC, while MISO line of each TI/ADI ADC
|
||||||
|
connects to a shared input pin of the GyroADC.
|
||||||
|
"maxim,max1162" or "maxim,max11100"
|
||||||
|
- Maxim MAX1162 / Maxim MAX11100 compatible mode,
|
||||||
|
16bit sampling, up to 8 channels can be sampled in
|
||||||
|
round-robin fashion. One Maxim chip supplies single
|
||||||
|
ADC channel with data, thus for 8-channel operation,
|
||||||
|
8 chips are required. A 3:8 chipselect demuxer is
|
||||||
|
required to connect the nCS line of the MAX chips
|
||||||
|
to the GyroADC, while MISO line of each Maxim ADC
|
||||||
|
connects to a shared input pin of the GyroADC.
|
||||||
|
- reg: Should be the number of the analog input. Should be present
|
||||||
|
for all ADCs except "fujitsu,mb88101a".
|
||||||
|
- vref-supply: Reference to the channel reference voltage regulator.
|
||||||
|
|
||||||
|
Example:
|
||||||
|
vref_max1162: regulator-vref-max1162 {
|
||||||
|
compatible = "regulator-fixed";
|
||||||
|
|
||||||
|
regulator-name = "MAX1162 Vref";
|
||||||
|
regulator-min-microvolt = <4096000>;
|
||||||
|
regulator-max-microvolt = <4096000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
adc@e6e54000 {
|
||||||
|
compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc";
|
||||||
|
reg = <0 0xe6e54000 0 64>;
|
||||||
|
clocks = <&mstp9_clks R8A7791_CLK_GYROADC>, <&clk_65m>;
|
||||||
|
clock-names = "fck", "if";
|
||||||
|
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||||
|
|
||||||
|
pinctrl-0 = <&adc_pins>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
adc@0 {
|
||||||
|
reg = <0>;
|
||||||
|
compatible = "maxim,max1162";
|
||||||
|
vref-supply = <&vref_max1162>;
|
||||||
|
};
|
||||||
|
|
||||||
|
adc@1 {
|
||||||
|
reg = <1>;
|
||||||
|
compatible = "maxim,max1162";
|
||||||
|
vref-supply = <&vref_max1162>;
|
||||||
|
};
|
||||||
|
};
|
|
@ -53,6 +53,11 @@ Required properties:
|
||||||
- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers" in
|
- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers" in
|
||||||
Documentation/devicetree/bindings/iio/iio-bindings.txt
|
Documentation/devicetree/bindings/iio/iio-bindings.txt
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
- dmas: Phandle to dma channel for this ADC instance.
|
||||||
|
See ../../dma/dma.txt for details.
|
||||||
|
- dma-names: Must be "rx" when dmas property is being used.
|
||||||
|
|
||||||
Example:
|
Example:
|
||||||
adc: adc@40012000 {
|
adc: adc@40012000 {
|
||||||
compatible = "st,stm32f4-adc-core";
|
compatible = "st,stm32f4-adc-core";
|
||||||
|
@ -77,6 +82,8 @@ Example:
|
||||||
interrupt-parent = <&adc>;
|
interrupt-parent = <&adc>;
|
||||||
interrupts = <0>;
|
interrupts = <0>;
|
||||||
st,adc-channels = <8>;
|
st,adc-channels = <8>;
|
||||||
|
dmas = <&dma2 0 0 0x400 0x0>;
|
||||||
|
dma-names = "rx";
|
||||||
};
|
};
|
||||||
...
|
...
|
||||||
other adc child nodes follow...
|
other adc child nodes follow...
|
||||||
|
|
|
@ -0,0 +1,23 @@
|
||||||
|
* Texas Instruments ADS7950 family of A/DC chips
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: Must be one of "ti,ads7950", "ti,ads7951", "ti,ads7952",
|
||||||
|
"ti,ads7953", "ti,ads7954", "ti,ads7955", "ti,ads7956", "ti,ads7957",
|
||||||
|
"ti,ads7958", "ti,ads7959", "ti,ads7960", or "ti,ads7961"
|
||||||
|
- reg: SPI chip select number for the device
|
||||||
|
- #io-channel-cells: Must be 1 as per ../iio-bindings.txt
|
||||||
|
- vref-supply: phandle to a regulator node that supplies the 2.5V or 5V
|
||||||
|
reference voltage
|
||||||
|
|
||||||
|
Recommended properties:
|
||||||
|
- spi-max-frequency: Definition as per
|
||||||
|
Documentation/devicetree/bindings/spi/spi-bus.txt
|
||||||
|
|
||||||
|
Example:
|
||||||
|
adc@0 {
|
||||||
|
compatible = "ti,ads7957";
|
||||||
|
reg = <0>;
|
||||||
|
#io-channel-cells = <1>;
|
||||||
|
vref-supply = <&refin_supply>;
|
||||||
|
spi-max-frequency = <10000000>;
|
||||||
|
};
|
|
@ -0,0 +1,36 @@
|
||||||
|
Bosch BMI160 - Inertial Measurement Unit with Accelerometer, Gyroscope
|
||||||
|
and externally connectable Magnetometer
|
||||||
|
|
||||||
|
https://www.bosch-sensortec.com/bst/products/all_products/bmi160
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible : should be "bosch,bmi160"
|
||||||
|
- reg : the I2C address or SPI chip select number of the sensor
|
||||||
|
- spi-max-frequency : set maximum clock frequency (only for SPI)
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
- interrupt-parent : should be the phandle of the interrupt controller
|
||||||
|
- interrupts : interrupt mapping for IRQ, must be IRQ_TYPE_LEVEL_LOW
|
||||||
|
- interrupt-names : set to "INT1" if INT1 pin should be used as interrupt
|
||||||
|
input, set to "INT2" if INT2 pin should be used instead
|
||||||
|
|
||||||
|
Examples:
|
||||||
|
|
||||||
|
bmi160@68 {
|
||||||
|
compatible = "bosch,bmi160";
|
||||||
|
reg = <0x68>;
|
||||||
|
|
||||||
|
interrupt-parent = <&gpio4>;
|
||||||
|
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
interrupt-names = "INT1";
|
||||||
|
};
|
||||||
|
|
||||||
|
bmi160@0 {
|
||||||
|
compatible = "bosch,bmi160";
|
||||||
|
reg = <0>;
|
||||||
|
spi-max-frequency = <10000000>;
|
||||||
|
|
||||||
|
interrupt-parent = <&gpio2>;
|
||||||
|
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
interrupt-names = "INT2";
|
||||||
|
};
|
|
@ -0,0 +1,26 @@
|
||||||
|
* ST_LSM6DSx driver for STM 6-axis (acc + gyro) imu Mems sensors
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: must be one of:
|
||||||
|
"st,lsm6ds3"
|
||||||
|
"st,lsm6dsm"
|
||||||
|
- reg: i2c address of the sensor / spi cs line
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
- st,drdy-int-pin: the pin on the package that will be used to signal
|
||||||
|
"data ready" (valid values: 1 or 2).
|
||||||
|
- interrupt-parent: should be the phandle for the interrupt controller
|
||||||
|
- interrupts: interrupt mapping for IRQ. It should be configured with
|
||||||
|
flags IRQ_TYPE_LEVEL_HIGH or IRQ_TYPE_EDGE_RISING.
|
||||||
|
|
||||||
|
Refer to interrupt-controller/interrupts.txt for generic interrupt
|
||||||
|
client node bindings.
|
||||||
|
|
||||||
|
Example:
|
||||||
|
|
||||||
|
lsm6dsm@6b {
|
||||||
|
compatible = "st,lsm6dsm";
|
||||||
|
reg = <0x6b>;
|
||||||
|
interrupt-parent = <&gpio0>;
|
||||||
|
interrupts = <0 IRQ_TYPE_EDGE_RISING>;
|
||||||
|
};
|
|
@ -0,0 +1,41 @@
|
||||||
|
Capella Microsystems CM3605
|
||||||
|
Ambient Light and Short Distance Proximity Sensor
|
||||||
|
|
||||||
|
The CM3605 is an entirely analog part which however require quite a bit of
|
||||||
|
software logic to interface a host operating system.
|
||||||
|
|
||||||
|
This ALS and proximity sensor was one of the very first deployed in mobile
|
||||||
|
handsets, notably it is used in the very first Nexus One Android phone from
|
||||||
|
2010.
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: must be: "capella,cm3605"
|
||||||
|
- aset-gpios: GPIO line controlling the ASET line (drive low
|
||||||
|
to activate the ALS, should be flagged GPIO_ACTIVE_LOW)
|
||||||
|
- interrupts: the IRQ line (such as a GPIO) that is connected to
|
||||||
|
the POUT (proximity sensor out) line. The edge detection must
|
||||||
|
be set to IRQ_TYPE_EDGE_BOTH so as to detect movements toward
|
||||||
|
and away from the proximity sensor.
|
||||||
|
- io-channels: the ADC channel used for converting the voltage from
|
||||||
|
AOUT to a digital representation.
|
||||||
|
- io-channel-names: must be "aout"
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
- vdd-supply: regulator supplying VDD power to the component.
|
||||||
|
- capella,aset-resistance-ohms: the sensitivity calibration resistance,
|
||||||
|
in Ohms. Valid values are: 50000, 100000, 300000 and 600000,
|
||||||
|
as these are the resistance values that we are supplied with
|
||||||
|
calibration curves for. If not supplied, 100 kOhm will be assumed
|
||||||
|
but it is strongly recommended to supply this.
|
||||||
|
|
||||||
|
Example:
|
||||||
|
|
||||||
|
cm3605 {
|
||||||
|
compatible = "capella,cm3605";
|
||||||
|
vdd-supply = <&foo_reg>;
|
||||||
|
aset-gpios = <&foo_gpio 1 GPIO_ACTIVE_LOW>;
|
||||||
|
capella,aset-resistance-ohms = <100000>;
|
||||||
|
interrupts = <1 IRQ_TYPE_EDGE_BOTH>;
|
||||||
|
io-channels = <&adc 0x01>;
|
||||||
|
io-channel-names = "aout";
|
||||||
|
};
|
|
@ -0,0 +1,23 @@
|
||||||
|
* Maxim Linear-Taper Digital Potentiometer MAX5481-MAX5484
|
||||||
|
|
||||||
|
The node for this driver must be a child node of a SPI controller, hence
|
||||||
|
all mandatory properties described in
|
||||||
|
|
||||||
|
Documentation/devicetree/bindings/spi/spi-bus.txt
|
||||||
|
|
||||||
|
must be specified.
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: Must be one of the following, depending on the
|
||||||
|
model:
|
||||||
|
"maxim,max5481"
|
||||||
|
"maxim,max5482"
|
||||||
|
"maxim,max5483"
|
||||||
|
"maxim,max5484"
|
||||||
|
|
||||||
|
Example:
|
||||||
|
max548x: max548x@0 {
|
||||||
|
compatible = "maxim,max5482";
|
||||||
|
spi-max-frequency = <7000000>;
|
||||||
|
reg = <0>; /* chip-select */
|
||||||
|
};
|
|
@ -27,6 +27,8 @@ standard bindings from pinctrl/pinctrl-bindings.txt.
|
||||||
Valid compatible strings:
|
Valid compatible strings:
|
||||||
|
|
||||||
Accelerometers:
|
Accelerometers:
|
||||||
|
- st,lis3lv02d (deprecated, use st,lis3lv02dl-accel)
|
||||||
|
- st,lis302dl-spi (deprecated, use st,lis3lv02dl-accel)
|
||||||
- st,lis3lv02dl-accel
|
- st,lis3lv02dl-accel
|
||||||
- st,lsm303dlh-accel
|
- st,lsm303dlh-accel
|
||||||
- st,lsm303dlhc-accel
|
- st,lsm303dlhc-accel
|
||||||
|
|
|
@ -0,0 +1,35 @@
|
||||||
|
* TI TMP007 - IR thermopile sensor with integrated math engine
|
||||||
|
|
||||||
|
Link to datasheet: http://www.ti.com/lit/ds/symlink/tmp007.pdf
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
|
||||||
|
- compatible: should be "ti,tmp007"
|
||||||
|
- reg: the I2C address of the sensor (changeable via ADR pins)
|
||||||
|
------------------------------
|
||||||
|
|ADR1 | ADR0 | Device Address|
|
||||||
|
------------------------------
|
||||||
|
0 0 0x40
|
||||||
|
0 1 0x41
|
||||||
|
0 SDA 0x42
|
||||||
|
0 SCL 0x43
|
||||||
|
1 0 0x44
|
||||||
|
1 1 0x45
|
||||||
|
1 SDA 0x46
|
||||||
|
1 SCL 0x47
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
|
||||||
|
- interrupt-parent: should be the phandle for the interrupt controller
|
||||||
|
|
||||||
|
- interrupts: interrupt mapping for GPIO IRQ (level active low)
|
||||||
|
|
||||||
|
Example:
|
||||||
|
|
||||||
|
tmp007@40 {
|
||||||
|
compatible = "ti,tmp007";
|
||||||
|
reg = <0x40>;
|
||||||
|
interrupt-parent = <&gpio0>;
|
||||||
|
interrupts = <5 0x08>;
|
||||||
|
};
|
||||||
|
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue