ARM: i.MX6: Use upstream dtsi files
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
parent
04a3e57996
commit
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "imx6dl-pinfunc.h"
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#include "imx6qdl-pingrp.h"
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#include "imx6qdl.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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operating-points = <
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/* kHz uV */
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996000 1275000
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792000 1175000
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396000 1075000
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>;
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fsl,soc-operating-points = <
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/* ARM kHz SOC-PU uV */
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996000 1175000
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792000 1175000
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396000 1175000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clks 104>, <&clks 6>, <&clks 16>,
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<&clks 17>, <&clks 170>;
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clock-names = "arm", "pll2_pfd2_396m", "step",
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"pll1_sw", "pll1_sys";
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arm-supply = <®_arm>;
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pu-supply = <®_pu>;
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soc-supply = <®_soc>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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};
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soc {
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ocram: sram@00900000 {
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compatible = "mmio-sram";
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reg = <0x00900000 0x20000>;
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clocks = <&clks 142>;
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};
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aips1: aips-bus@02000000 {
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iomuxc: iomuxc@020e0000 {
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compatible = "fsl,imx6dl-iomuxc";
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};
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pxp: pxp@020f0000 {
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reg = <0x020f0000 0x4000>;
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interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
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};
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epdc: epdc@020f4000 {
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reg = <0x020f4000 0x4000>;
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interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
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};
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lcdif: lcdif@020f8000 {
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reg = <0x020f8000 0x4000>;
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interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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aips2: aips-bus@02100000 {
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i2c4: i2c@021f8000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx1-i2c";
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reg = <0x021f8000 0x4000>;
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interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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};
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};
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};
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&ldb {
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clocks = <&clks 33>, <&clks 34>,
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<&clks 39>, <&clks 40>,
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<&clks 135>, <&clks 136>;
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clock-names = "di0_pll", "di1_pll",
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"di0_sel", "di1_sel",
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"di0", "di1";
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lvds-channel@0 {
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crtcs = <&ipu1 0>, <&ipu1 1>;
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};
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lvds-channel@1 {
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crtcs = <&ipu1 0>, <&ipu1 1>;
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};
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};
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#include <arm/imx6dl.dtsi>
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "imx6q-pinfunc.h"
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#include "imx6qdl-pingrp.h"
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#include "imx6qdl.dtsi"
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#include <arm/imx6q.dtsi>
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/ {
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aliases {
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spi4 = &ecspi5;
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ipu1 = &ipu2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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operating-points = <
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/* kHz uV */
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1200000 1275000
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996000 1250000
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792000 1150000
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396000 975000
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>;
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fsl,soc-operating-points = <
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/* ARM kHz SOC-PU uV */
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1200000 1275000
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996000 1250000
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792000 1175000
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396000 1175000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clks 104>, <&clks 6>, <&clks 16>,
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<&clks 17>, <&clks 170>;
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clock-names = "arm", "pll2_pfd2_396m", "step",
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"pll1_sw", "pll1_sys";
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arm-supply = <®_arm>;
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pu-supply = <®_pu>;
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soc-supply = <®_soc>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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cpu@2 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <2>;
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next-level-cache = <&L2>;
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};
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cpu@3 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <3>;
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next-level-cache = <&L2>;
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};
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};
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soc {
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ocram: sram@00900000 {
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compatible = "mmio-sram";
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reg = <0x00900000 0x40000>;
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clocks = <&clks 142>;
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};
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aips-bus@02000000 { /* AIPS1 */
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spba-bus@02000000 {
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ecspi5: ecspi@02018000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
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reg = <0x02018000 0x4000>;
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interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks 116>, <&clks 116>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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};
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iomuxc: iomuxc@020e0000 {
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compatible = "fsl,imx6q-iomuxc";
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ipu2 {
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pinctrl_ipu2_1: ipu2grp-1 {
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fsl,pins = <
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MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
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MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10
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MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10
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MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10
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MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000
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MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10
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MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10
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MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10
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MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10
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MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10
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MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10
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MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10
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MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10
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MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10
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MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10
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MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10
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MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10
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MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10
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MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10
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MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10
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MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10
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MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10
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MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10
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MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10
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MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10
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MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10
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MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10
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MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10
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MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10
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>;
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};
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};
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};
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};
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sata: sata@02200000 {
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compatible = "fsl,imx6q-ahci";
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reg = <0x02200000 0x4000>;
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interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks 154>, <&clks 187>, <&clks 105>;
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clock-names = "sata", "sata_ref", "ahb";
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status = "disabled";
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};
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ipu2: ipu@02800000 {
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#crtc-cells = <1>;
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compatible = "fsl,imx6q-ipu";
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reg = <0x02800000 0x400000>;
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interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
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<0 7 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks 133>, <&clks 134>, <&clks 137>;
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clock-names = "bus", "di0", "di1";
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resets = <&src 4>;
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};
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};
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};
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&hdmi {
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compatible = "fsl,imx6q-hdmi";
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};
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&ldb {
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clocks = <&clks 33>, <&clks 34>,
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<&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>,
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<&clks 135>, <&clks 136>;
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clock-names = "di0_pll", "di1_pll",
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"di0_sel", "di1_sel", "di2_sel", "di3_sel",
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"di0", "di1";
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lvds-channel@0 {
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crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
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};
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lvds-channel@1 {
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crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
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};
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};
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@ -1,960 +1,11 @@
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/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "skeleton.dtsi"
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#include "imx6qdl-pingrp.h"
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/ {
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aliases {
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can0 = &can1;
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can1 = &can2;
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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gpio4 = &gpio5;
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gpio5 = &gpio6;
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gpio6 = &gpio7;
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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mmc2 = &usdhc3;
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mmc3 = &usdhc4;
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pwm0 = &pwm1;
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pwm1 = &pwm2;
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pwm2 = &pwm3;
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pwm3 = &pwm4;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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spi0 = &ecspi1;
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spi1 = &ecspi2;
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spi2 = &ecspi3;
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spi3 = &ecspi4;
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usbphy0 = &usbphy1;
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usbphy1 = &usbphy2;
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ipu0 = &ipu1;
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};
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intc: interrupt-controller@00a01000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-controller;
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reg = <0x00a01000 0x1000>,
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<0x00a00100 0x100>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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ckil {
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compatible = "fsl,imx-ckil", "fixed-clock";
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clock-frequency = <32768>;
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};
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ckih1 {
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compatible = "fsl,imx-ckih1", "fixed-clock";
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clock-frequency = <0>;
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};
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osc {
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compatible = "fsl,imx-osc", "fixed-clock";
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clock-frequency = <24000000>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&intc>;
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ranges;
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dma_apbh: dma-apbh@00110000 {
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compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
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reg = <0x00110000 0x2000>;
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interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 13 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
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#dma-cells = <1>;
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dma-channels = <4>;
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clocks = <&clks 106>;
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};
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gpmi: gpmi-nand@00112000 {
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compatible = "fsl,imx6q-gpmi-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
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reg-names = "gpmi-nand", "bch";
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interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "bch";
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clocks = <&clks 152>, <&clks 153>, <&clks 151>,
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<&clks 150>, <&clks 149>;
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clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
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"gpmi_bch_apb", "per1_bch";
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dmas = <&dma_apbh 0>;
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dma-names = "rx-tx";
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status = "disabled";
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};
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timer@00a00600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x00a00600 0x20>;
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interrupts = <1 13 0xf01>;
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clocks = <&clks 15>;
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};
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L2: l2-cache@00a02000 {
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compatible = "arm,pl310-cache";
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reg = <0x00a02000 0x1000>;
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interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
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cache-unified;
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cache-level = <2>;
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arm,tag-latency = <4 2 3>;
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arm,data-latency = <4 2 3>;
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};
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pcie: pcie@0x01000000 {
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compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
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reg = <0x01ffc000 0x4000>; /* DBI */
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
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0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
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num-lanes = <1>;
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interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
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clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
aips-bus@02000000 { /* AIPS1 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x02000000 0x100000>;
|
||||
ranges;
|
||||
|
||||
spba-bus@02000000 {
|
||||
compatible = "fsl,spba-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x02000000 0x40000>;
|
||||
ranges;
|
||||
|
||||
spdif: spdif@02004000 {
|
||||
compatible = "fsl,imx35-spdif";
|
||||
reg = <0x02004000 0x4000>;
|
||||
interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&sdma 14 18 0>,
|
||||
<&sdma 15 18 0>;
|
||||
dma-names = "rx", "tx";
|
||||
clocks = <&clks 197>, <&clks 3>,
|
||||
<&clks 197>, <&clks 107>,
|
||||
<&clks 0>, <&clks 118>,
|
||||
<&clks 0>, <&clks 139>,
|
||||
<&clks 0>;
|
||||
clock-names = "core", "rxtx0",
|
||||
"rxtx1", "rxtx2",
|
||||
"rxtx3", "rxtx4",
|
||||
"rxtx5", "rxtx6",
|
||||
"rxtx7";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi1: ecspi@02008000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02008000 0x4000>;
|
||||
interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 112>, <&clks 112>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi2: ecspi@0200c000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x0200c000 0x4000>;
|
||||
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 113>, <&clks 113>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi3: ecspi@02010000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02010000 0x4000>;
|
||||
interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 114>, <&clks 114>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi4: ecspi@02014000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02014000 0x4000>;
|
||||
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 115>, <&clks 115>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@02020000 {
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02020000 0x4000>;
|
||||
interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esai: esai@02024000 {
|
||||
reg = <0x02024000 0x4000>;
|
||||
interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
ssi1: ssi@02028000 {
|
||||
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
|
||||
reg = <0x02028000 0x4000>;
|
||||
interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 178>;
|
||||
dmas = <&sdma 37 1 0>,
|
||||
<&sdma 38 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <38 37>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssi2: ssi@0202c000 {
|
||||
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
|
||||
reg = <0x0202c000 0x4000>;
|
||||
interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 179>;
|
||||
dmas = <&sdma 41 1 0>,
|
||||
<&sdma 42 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <42 41>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssi3: ssi@02030000 {
|
||||
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
|
||||
reg = <0x02030000 0x4000>;
|
||||
interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 180>;
|
||||
dmas = <&sdma 45 1 0>,
|
||||
<&sdma 46 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <46 45>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
asrc: asrc@02034000 {
|
||||
reg = <0x02034000 0x4000>;
|
||||
interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spba@0203c000 {
|
||||
reg = <0x0203c000 0x4000>;
|
||||
};
|
||||
};
|
||||
|
||||
vpu: vpu@02040000 {
|
||||
reg = <0x02040000 0x3c000>;
|
||||
interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
aipstz@0207c000 { /* AIPSTZ1 */
|
||||
reg = <0x0207c000 0x4000>;
|
||||
};
|
||||
|
||||
pwm1: pwm@02080000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x02080000 0x4000>;
|
||||
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 62>, <&clks 145>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
pwm2: pwm@02084000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x02084000 0x4000>;
|
||||
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 62>, <&clks 146>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
pwm3: pwm@02088000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x02088000 0x4000>;
|
||||
interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 62>, <&clks 147>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
pwm4: pwm@0208c000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x0208c000 0x4000>;
|
||||
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 62>, <&clks 148>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
can1: flexcan@02090000 {
|
||||
compatible = "fsl,imx6q-flexcan";
|
||||
reg = <0x02090000 0x4000>;
|
||||
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 108>, <&clks 109>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can2: flexcan@02094000 {
|
||||
compatible = "fsl,imx6q-flexcan";
|
||||
reg = <0x02094000 0x4000>;
|
||||
interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 110>, <&clks 111>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpt: gpt@02098000 {
|
||||
compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
|
||||
reg = <0x02098000 0x4000>;
|
||||
interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 119>, <&clks 120>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
gpio1: gpio@0209c000 {
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x0209c000 0x4000>;
|
||||
interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@020a0000 {
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x020a0000 0x4000>;
|
||||
interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@020a4000 {
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x020a4000 0x4000>;
|
||||
interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio4: gpio@020a8000 {
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x020a8000 0x4000>;
|
||||
interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio5: gpio@020ac000 {
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x020ac000 0x4000>;
|
||||
interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio6: gpio@020b0000 {
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x020b0000 0x4000>;
|
||||
interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio7: gpio@020b4000 {
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x020b4000 0x4000>;
|
||||
interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
kpp: kpp@020b8000 {
|
||||
reg = <0x020b8000 0x4000>;
|
||||
interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
wdog1: wdog@020bc000 {
|
||||
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x020bc000 0x4000>;
|
||||
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 0>;
|
||||
};
|
||||
|
||||
wdog2: wdog@020c0000 {
|
||||
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x020c0000 0x4000>;
|
||||
interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clks: ccm@020c4000 {
|
||||
compatible = "fsl,imx6q-ccm";
|
||||
reg = <0x020c4000 0x4000>;
|
||||
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 88 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
anatop: anatop@020c8000 {
|
||||
compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
|
||||
reg = <0x020c8000 0x1000>;
|
||||
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
regulator-1p1@110 {
|
||||
compatible = "fsl,anatop-regulator";
|
||||
regulator-name = "vdd1p1";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1375000>;
|
||||
regulator-always-on;
|
||||
anatop-reg-offset = <0x110>;
|
||||
anatop-vol-bit-shift = <8>;
|
||||
anatop-vol-bit-width = <5>;
|
||||
anatop-min-bit-val = <4>;
|
||||
anatop-min-voltage = <800000>;
|
||||
anatop-max-voltage = <1375000>;
|
||||
};
|
||||
|
||||
regulator-3p0@120 {
|
||||
compatible = "fsl,anatop-regulator";
|
||||
regulator-name = "vdd3p0";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <3150000>;
|
||||
regulator-always-on;
|
||||
anatop-reg-offset = <0x120>;
|
||||
anatop-vol-bit-shift = <8>;
|
||||
anatop-vol-bit-width = <5>;
|
||||
anatop-min-bit-val = <0>;
|
||||
anatop-min-voltage = <2625000>;
|
||||
anatop-max-voltage = <3400000>;
|
||||
};
|
||||
|
||||
regulator-2p5@130 {
|
||||
compatible = "fsl,anatop-regulator";
|
||||
regulator-name = "vdd2p5";
|
||||
regulator-min-microvolt = <2000000>;
|
||||
regulator-max-microvolt = <2750000>;
|
||||
regulator-always-on;
|
||||
anatop-reg-offset = <0x130>;
|
||||
anatop-vol-bit-shift = <8>;
|
||||
anatop-vol-bit-width = <5>;
|
||||
anatop-min-bit-val = <0>;
|
||||
anatop-min-voltage = <2000000>;
|
||||
anatop-max-voltage = <2750000>;
|
||||
};
|
||||
|
||||
reg_arm: regulator-vddcore@140 {
|
||||
compatible = "fsl,anatop-regulator";
|
||||
regulator-name = "vddarm";
|
||||
regulator-min-microvolt = <725000>;
|
||||
regulator-max-microvolt = <1450000>;
|
||||
regulator-always-on;
|
||||
anatop-reg-offset = <0x140>;
|
||||
anatop-vol-bit-shift = <0>;
|
||||
anatop-vol-bit-width = <5>;
|
||||
anatop-delay-reg-offset = <0x170>;
|
||||
anatop-delay-bit-shift = <24>;
|
||||
anatop-delay-bit-width = <2>;
|
||||
anatop-min-bit-val = <1>;
|
||||
anatop-min-voltage = <725000>;
|
||||
anatop-max-voltage = <1450000>;
|
||||
};
|
||||
|
||||
reg_pu: regulator-vddpu@140 {
|
||||
compatible = "fsl,anatop-regulator";
|
||||
regulator-name = "vddpu";
|
||||
regulator-min-microvolt = <725000>;
|
||||
regulator-max-microvolt = <1450000>;
|
||||
regulator-always-on;
|
||||
anatop-reg-offset = <0x140>;
|
||||
anatop-vol-bit-shift = <9>;
|
||||
anatop-vol-bit-width = <5>;
|
||||
anatop-delay-reg-offset = <0x170>;
|
||||
anatop-delay-bit-shift = <26>;
|
||||
anatop-delay-bit-width = <2>;
|
||||
anatop-min-bit-val = <1>;
|
||||
anatop-min-voltage = <725000>;
|
||||
anatop-max-voltage = <1450000>;
|
||||
};
|
||||
|
||||
reg_soc: regulator-vddsoc@140 {
|
||||
compatible = "fsl,anatop-regulator";
|
||||
regulator-name = "vddsoc";
|
||||
regulator-min-microvolt = <725000>;
|
||||
regulator-max-microvolt = <1450000>;
|
||||
regulator-always-on;
|
||||
anatop-reg-offset = <0x140>;
|
||||
anatop-vol-bit-shift = <18>;
|
||||
anatop-vol-bit-width = <5>;
|
||||
anatop-delay-reg-offset = <0x170>;
|
||||
anatop-delay-bit-shift = <28>;
|
||||
anatop-delay-bit-width = <2>;
|
||||
anatop-min-bit-val = <1>;
|
||||
anatop-min-voltage = <725000>;
|
||||
anatop-max-voltage = <1450000>;
|
||||
};
|
||||
};
|
||||
|
||||
tempmon: tempmon {
|
||||
compatible = "fsl,imx6q-tempmon";
|
||||
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
fsl,tempmon = <&anatop>;
|
||||
fsl,tempmon-data = <&ocotp>;
|
||||
clocks = <&clks 172>;
|
||||
};
|
||||
|
||||
usbphy1: usbphy@020c9000 {
|
||||
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
|
||||
reg = <0x020c9000 0x1000>;
|
||||
interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 182>;
|
||||
fsl,anatop = <&anatop>;
|
||||
};
|
||||
|
||||
usbphy2: usbphy@020ca000 {
|
||||
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
|
||||
reg = <0x020ca000 0x1000>;
|
||||
interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 183>;
|
||||
fsl,anatop = <&anatop>;
|
||||
};
|
||||
|
||||
snvs@020cc000 {
|
||||
compatible = "fsl,sec-v4.0-mon", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x020cc000 0x4000>;
|
||||
|
||||
snvs-rtc-lp@34 {
|
||||
compatible = "fsl,sec-v4.0-mon-rtc-lp";
|
||||
reg = <0x34 0x58>;
|
||||
interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
epit1: epit@020d0000 { /* EPIT1 */
|
||||
reg = <0x020d0000 0x4000>;
|
||||
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
epit2: epit@020d4000 { /* EPIT2 */
|
||||
reg = <0x020d4000 0x4000>;
|
||||
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
src: src@020d8000 {
|
||||
compatible = "fsl,imx6q-src", "fsl,imx51-src";
|
||||
reg = <0x020d8000 0x4000>;
|
||||
interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
gpc: gpc@020dc000 {
|
||||
compatible = "fsl,imx6q-gpc";
|
||||
reg = <0x020dc000 0x4000>;
|
||||
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 90 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpr: iomuxc-gpr@020e0000 {
|
||||
compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
|
||||
reg = <0x020e0000 0x38>;
|
||||
};
|
||||
|
||||
iomuxc: iomuxc@020e0000 {
|
||||
compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
|
||||
reg = <0x020e0000 0x4000>;
|
||||
};
|
||||
|
||||
ldb: ldb@020e0008 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
|
||||
gpr = <&gpr>;
|
||||
status = "disabled";
|
||||
|
||||
lvds-channel@0 {
|
||||
reg = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lvds-channel@1 {
|
||||
reg = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
hdmi: hdmi@0120000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x00120000 0x9000>;
|
||||
interrupts = <0 115 0x04>;
|
||||
gpr = <&gpr>;
|
||||
clocks = <&clks 123>, <&clks 124>;
|
||||
clock-names = "iahb", "isfr";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dcic1: dcic@020e4000 {
|
||||
reg = <0x020e4000 0x4000>;
|
||||
interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
dcic2: dcic@020e8000 {
|
||||
reg = <0x020e8000 0x4000>;
|
||||
interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sdma: sdma@020ec000 {
|
||||
compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
|
||||
reg = <0x020ec000 0x4000>;
|
||||
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 155>, <&clks 155>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
|
||||
};
|
||||
};
|
||||
|
||||
aips-bus@02100000 { /* AIPS2 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x02100000 0x100000>;
|
||||
ranges;
|
||||
|
||||
caam@02100000 {
|
||||
reg = <0x02100000 0x40000>;
|
||||
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
aipstz@0217c000 { /* AIPSTZ2 */
|
||||
reg = <0x0217c000 0x4000>;
|
||||
};
|
||||
|
||||
usbotg: usb@02184000 {
|
||||
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
||||
reg = <0x02184000 0x200>;
|
||||
interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 162>;
|
||||
fsl,usbphy = <&usbphy1>;
|
||||
fsl,usbmisc = <&usbmisc 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbh1: usb@02184200 {
|
||||
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
||||
reg = <0x02184200 0x200>;
|
||||
interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 162>;
|
||||
fsl,usbphy = <&usbphy2>;
|
||||
fsl,usbmisc = <&usbmisc 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbh2: usb@02184400 {
|
||||
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
||||
reg = <0x02184400 0x200>;
|
||||
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 162>;
|
||||
fsl,usbmisc = <&usbmisc 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbh3: usb@02184600 {
|
||||
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
||||
reg = <0x02184600 0x200>;
|
||||
interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 162>;
|
||||
fsl,usbmisc = <&usbmisc 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbmisc: usbmisc@02184800 {
|
||||
#index-cells = <1>;
|
||||
compatible = "fsl,imx6q-usbmisc";
|
||||
reg = <0x02184800 0x200>;
|
||||
clocks = <&clks 162>;
|
||||
};
|
||||
|
||||
fec: ethernet@02188000 {
|
||||
compatible = "fsl,imx6q-fec";
|
||||
reg = <0x02188000 0x4000>;
|
||||
interrupts-extended =
|
||||
<&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 117>, <&clks 117>, <&clks 190>;
|
||||
clock-names = "ipg", "ahb", "ptp";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mlb@0218c000 {
|
||||
reg = <0x0218c000 0x4000>;
|
||||
interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 117 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 126 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
usdhc1: usdhc@02190000 {
|
||||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x02190000 0x4000>;
|
||||
interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 163>, <&clks 163>, <&clks 163>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc2: usdhc@02194000 {
|
||||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x02194000 0x4000>;
|
||||
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 164>, <&clks 164>, <&clks 164>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc3: usdhc@02198000 {
|
||||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x02198000 0x4000>;
|
||||
interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 165>, <&clks 165>, <&clks 165>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc4: usdhc@0219c000 {
|
||||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x0219c000 0x4000>;
|
||||
interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 166>, <&clks 166>, <&clks 166>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@021a0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x021a0000 0x4000>;
|
||||
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 125>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@021a4000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x021a4000 0x4000>;
|
||||
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 126>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@021a8000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x021a8000 0x4000>;
|
||||
interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 127>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
romcp@021ac000 {
|
||||
reg = <0x021ac000 0x4000>;
|
||||
};
|
||||
|
||||
mmdc0: mmdc@021b0000 { /* MMDC0 */
|
||||
compatible = "fsl,imx6q-mmdc";
|
||||
reg = <0x021b0000 0x4000>;
|
||||
};
|
||||
|
||||
mmdc1: mmdc@021b4000 { /* MMDC1 */
|
||||
reg = <0x021b4000 0x4000>;
|
||||
};
|
||||
|
||||
weim: weim@021b8000 {
|
||||
compatible = "fsl,imx6q-weim";
|
||||
reg = <0x021b8000 0x4000>;
|
||||
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 196>;
|
||||
};
|
||||
|
||||
ocotp: ocotp@021bc000 {
|
||||
compatible = "fsl,imx6q-ocotp", "syscon";
|
||||
reg = <0x021bc000 0x4000>;
|
||||
};
|
||||
|
||||
tzasc@021d0000 { /* TZASC1 */
|
||||
reg = <0x021d0000 0x4000>;
|
||||
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
tzasc@021d4000 { /* TZASC2 */
|
||||
reg = <0x021d4000 0x4000>;
|
||||
interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
audmux: audmux@021d8000 {
|
||||
compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
|
||||
reg = <0x021d8000 0x4000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mipi_csi: mipi@021dc000 {
|
||||
reg = <0x021dc000 0x4000>;
|
||||
};
|
||||
|
||||
mipi@021e0000 { /* MIPI-DSI */
|
||||
reg = <0x021e0000 0x4000>;
|
||||
};
|
||||
|
||||
vdoa@021e4000 {
|
||||
reg = <0x021e4000 0x4000>;
|
||||
interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart2: serial@021e8000 {
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021e8000 0x4000>;
|
||||
interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@021ec000 {
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021ec000 0x4000>;
|
||||
interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@021f0000 {
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021f0000 0x4000>;
|
||||
interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@021f4000 {
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021f4000 0x4000>;
|
||||
interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
ipu1: ipu@02400000 {
|
||||
#crtc-cells = <1>;
|
||||
compatible = "fsl,imx6q-ipu";
|
||||
reg = <0x02400000 0x400000>;
|
||||
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 130>, <&clks 131>, <&clks 132>;
|
||||
clock-names = "bus", "di0", "di1";
|
||||
resets = <&src 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
Loading…
Reference in New Issue