arm: initial support for Marvell Dove SoCs
This commit adds minimal support for the Marvell Dove SoC (88AP510) as first SoC of the Marvell Orion family. Orion SoCs have a different timer, therefore current mach-mvebu and Armada 370/XP Kconfig and Makefiles are slightly modified and a new clocksource drivers is added. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sebastian Hesselbarth
Sascha Hauer
parent
87f486c7f1
commit
98a8c2f28b
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@ -82,7 +82,6 @@ config ARCH_IMX
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config ARCH_MVEBU
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bool "Marvell EBU platforms"
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select COMMON_CLK
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select CLOCKSOURCE_MVEBU
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select CLKDEV_LOOKUP
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select HAS_DEBUG_LL
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@ -17,10 +17,17 @@ choice
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config ARCH_ARMADA_370
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bool "Armada 370"
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select CPU_V7
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select CLOCKSOURCE_MVEBU
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config ARCH_ARMADA_XP
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bool "Armada XP"
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select CPU_V7
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select CLOCKSOURCE_MVEBU
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config ARCH_DOVE
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bool "Dove 88AP510"
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select CPU_V7
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select CLOCKSOURCE_ORION
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endchoice
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@ -51,4 +58,13 @@ endchoice
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endif # ARCH_ARMADA_XP
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if ARCH_DOVE
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choice
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prompt "Dove 88AP510 Board Type"
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endchoice
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endif # ARCH_DOVE
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endif # ARCH_MVEBU
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@ -1 +1,3 @@
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obj-y += core.o
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obj-$(CONFIG_ARCH_ARMADA_370) += core.o
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obj-$(CONFIG_ARCH_ARMADA_XP) += core.o
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obj-$(CONFIG_ARCH_DOVE) += dove.o
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@ -0,0 +1,161 @@
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/*
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* Copyright
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* (C) 2013 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <ns16550.h>
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#include <mach/dove-regs.h>
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#include <asm/memory.h>
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#include <asm/barebox-arm.h>
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static struct clk *tclk;
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static inline void dove_remap_reg_base(uint32_t intbase,
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uint32_t mcbase)
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{
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uint32_t val;
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/* remap ahb slave base */
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val = readl(DOVE_CPU_CTRL) & 0xffff0000;
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val |= (mcbase & 0xffff0000) >> 16;
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writel(val, DOVE_CPU_CTRL);
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/* remap axi bridge address */
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val = readl(DOVE_AXI_CTRL) & 0x007fffff;
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val |= mcbase & 0xff800000;
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writel(val, DOVE_AXI_CTRL);
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/* remap memory controller base address */
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val = readl(DOVE_SDRAM_BASE + SDRAM_REGS_BASE_DECODE) & 0x0000ffff;
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val |= mcbase & 0xffff0000;
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writel(val, DOVE_SDRAM_BASE + SDRAM_REGS_BASE_DECODE);
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/* remap internal register */
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val = intbase & 0xfff00000;
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writel(val, DOVE_BRIDGE_BASE + INT_REGS_BASE_MAP);
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}
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static inline void dove_memory_find(unsigned long *phys_base,
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unsigned long *phys_size)
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{
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int n;
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*phys_base = ~0;
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*phys_size = 0;
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for (n = 0; n < 2; n++) {
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uint32_t map = readl(DOVE_SDRAM_BASE + SDRAM_MAPn(n));
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uint32_t base, size;
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/* skip disabled areas */
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if ((map & SDRAM_MAP_VALID) != SDRAM_MAP_VALID)
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continue;
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base = map & SDRAM_START_MASK;
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if (base < *phys_base)
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*phys_base = base;
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/* real size is encoded as ld(2^(16+length)) */
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size = (map & SDRAM_LENGTH_MASK) >> SDRAM_LENGTH_SHIFT;
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*phys_size += 1 << (16 + size);
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}
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}
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void __naked __noreturn dove_barebox_entry(void)
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{
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unsigned long phys_base, phys_size;
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dove_memory_find(&phys_base, &phys_size);
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barebox_arm_entry(phys_base, phys_size, 0);
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}
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static struct NS16550_plat uart_plat[] = {
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[0] = { .shift = 2, },
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[1] = { .shift = 2, },
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[2] = { .shift = 2, },
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[3] = { .shift = 2, },
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};
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int dove_add_uart(int num)
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{
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struct NS16550_plat *plat;
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if (num < 0 || num > 4)
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return -EINVAL;
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plat = &uart_plat[num];
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plat->clock = clk_get_rate(tclk);
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if (!add_ns16550_device(DEVICE_ID_DYNAMIC,
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(unsigned int)DOVE_UARTn_BASE(num),
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32, IORESOURCE_MEM_32BIT, plat))
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return -ENODEV;
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return 0;
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}
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/*
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* Dove TCLK sample-at-reset configuation
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*
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* SAR0[24:23] : TCLK frequency
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* 0 = 166 MHz
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* 1 = 125 MHz
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* others reserved.
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*/
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static int dove_init_clocks(void)
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{
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uint32_t strap, sar = readl(DOVE_SAR_BASE + SAR0);
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unsigned int rate;
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strap = (sar & TCLK_FREQ_MASK) >> TCLK_FREQ_SHIFT;
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switch (strap) {
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case 0:
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rate = 166666667;
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break;
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case 1:
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rate = 125000000;
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break;
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default:
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panic("Unknown TCLK strapping %d\n", strap);
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}
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tclk = clk_fixed("tclk", rate);
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return clk_register_clkdev(tclk, NULL, "orion-timer");
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}
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static int dove_init_soc(void)
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{
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unsigned long phys_base, phys_size;
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dove_init_clocks();
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add_generic_device("orion-timer", DEVICE_ID_SINGLE, NULL,
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(unsigned int)DOVE_TIMER_BASE, 0x30,
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IORESOURCE_MEM, NULL);
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dove_memory_find(&phys_base, &phys_size);
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arm_add_mem_device("ram0", phys_base, phys_size);
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return 0;
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}
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postcore_initcall(dove_init_soc);
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void __noreturn reset_cpu(unsigned long addr)
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{
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/* enable and assert RSTOUTn */
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writel(SOFT_RESET_OUT_EN, DOVE_BRIDGE_BASE + BRIDGE_RSTOUT_MASK);
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writel(SOFT_RESET_EN, DOVE_BRIDGE_BASE + BRIDGE_SYS_SOFT_RESET);
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while (1)
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;
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}
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EXPORT_SYMBOL(reset_cpu);
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@ -0,0 +1,59 @@
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/*
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* Copyright
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* (C) 2013 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __MACH_MVEBU_DOVE_REGS_H
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#define __MACH_MVEBU_DOVE_REGS_H
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/* At Boot-up register base is at 0xd000000 */
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#define DOVE_INT_REGS_BOOTUP 0xd0000000
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#define DOVE_MC_REGS_BOOTUP 0xd0800000
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/* Linux wants it remapped to 0xf1000000 */
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#define DOVE_INT_REGS_REMAP 0xf1000000
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#define DOVE_MC_REGS_REMAP 0xf1800000
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#define DOVE_INT_REGS_BASE IOMEM(DOVE_INT_REGS_BOOTUP)
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#define DOVE_MC_REGS_BASE IOMEM(DOVE_MC_REGS_BOOTUP)
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#define DOVE_UART_BASE (DOVE_INT_REGS_BASE + 0x12000)
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#define DOVE_UARTn_BASE(n) (DOVE_UART_BASE + ((n) * 0x100))
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#define DOVE_BRIDGE_BASE (DOVE_INT_REGS_BASE + 0x20000)
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#define INT_REGS_BASE_MAP 0x080
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#define BRIDGE_RSTOUT_MASK 0x108
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#define SOFT_RESET_OUT_EN BIT(2)
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#define BRIDGE_SYS_SOFT_RESET 0x10c
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#define SOFT_RESET_EN BIT(0)
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#define DOVE_TIMER_BASE (DOVE_INT_REGS_BASE + 0x20300)
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#define DOVE_SAR_BASE (DOVE_INT_REGS_BASE + 0xd0214)
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#define SAR0 0x000
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#define TCLK_FREQ_SHIFT 23
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#define TCLK_FREQ_MASK (0x3 << TCLK_FREQ_SHIFT)
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#define SAR1 0x004
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#define DOVE_AXI_CTRL (DOVE_INT_REGS_BASE + 0xd0224)
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#define DOVE_CPU_CTRL (DOVE_INT_REGS_BASE + 0xd025c)
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#define DOVE_SDRAM_BASE (DOVE_MC_REGS_BASE)
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#define SDRAM_REGS_BASE_DECODE 0x010
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#define SDRAM_MAPn(n) (0x100 + ((n) * 0x10))
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#define SDRAM_START_MASK (0x1ff << 23)
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#define SDRAM_LENGTH_SHIFT 16
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#define SDRAM_LENGTH_MASK (0x00f << SDRAM_LENGTH_SHIFT)
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#define SDRAM_ADDRESS_MASK (0x1ff << 7)
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#define SDRAM_MAP_VALID BIT(0)
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#endif /* __MACH_MVEBU_DOVE_REGS_H */
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@ -0,0 +1,23 @@
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/*
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* Copyright
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* (C) 2013 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __MACH_MVEBU_DOVE_H
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#define __MACH_MVEBU_DOVE_H
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int dove_add_uart(int num);
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void __naked __noreturn dove_barebox_entry(void);
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#endif /* __MACH_MVEBU_DOVE_H */
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@ -21,3 +21,7 @@ config CLOCKSOURCE_MVEBU
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config CLOCKSOURCE_NOMADIK
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bool
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depends on ARM
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config CLOCKSOURCE_ORION
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bool
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depends on ARCH_MVEBU
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@ -4,3 +4,4 @@ obj-$(CONFIG_CLOCKSOURCE_BCM2835) += bcm2835.o
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obj-$(CONFIG_CLOCKSOURCE_CLPS711X) += clps711x.o
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obj-$(CONFIG_CLOCKSOURCE_MVEBU) += mvebu.o
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obj-$(CONFIG_CLOCKSOURCE_NOMADIK) += nomadik.o
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obj-$(CONFIG_CLOCKSOURCE_ORION) += orion.o
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@ -0,0 +1,76 @@
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/*
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* Copyright
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* (C) 2013 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <clock.h>
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#include <linux/clk.h>
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#include <io.h>
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#define TIMER_CTRL 0x00
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#define TIMER0_EN BIT(0)
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#define TIMER0_RELOAD_EN BIT(1)
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#define TIMER1_EN BIT(2)
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#define TIMER1_RELOAD_EN BIT(3)
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#define TIMER0_RELOAD 0x10
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#define TIMER0_VAL 0x14
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#define TIMER1_RELOAD 0x18
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#define TIMER1_VAL 0x1c
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static __iomem void *timer_base;
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static uint64_t orion_clocksource_read(void)
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{
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return __raw_readl(timer_base + TIMER0_VAL);
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}
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static struct clocksource clksrc = {
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.read = orion_clocksource_read,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 10,
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};
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static int orion_timer_probe(struct device_d *dev)
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{
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struct clk *tclk;
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uint32_t val;
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timer_base = dev_request_mem_region(dev, 0);
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tclk = clk_get(dev, "tclk");
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/* setup TIMER0 as free-running clock source */
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__raw_writel(~0, timer_base + TIMER0_VAL);
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__raw_writel(~0, timer_base + TIMER0_RELOAD);
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val = __raw_readl(timer_base + TIMER_CTRL);
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__raw_writel(val | TIMER0_EN | TIMER0_RELOAD_EN,
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timer_base + TIMER_CTRL);
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clksrc.mult = clocksource_hz2mult(clk_get_rate(tclk), clksrc.shift);
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init_clock(&clksrc);
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return 0;
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}
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static struct driver_d orion_timer_driver = {
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.name = "orion-timer",
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.probe = orion_timer_probe,
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};
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static int orion_timer_init(void)
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{
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return platform_driver_register(&orion_timer_driver);
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}
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postcore_initcall(orion_timer_init);
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