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barebox
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Merge branch 'for-next/imx-image' 

Conflicts:
	arch/arm/dts/Makefile
This commit is contained in:
Sascha Hauer 2014-03-07 09:24:46 +01:00
parent 048b03641e d7db7df187
commit 9c2aa61703
47 changed files with 918 additions and 1065 deletions
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22
arch/arm/Makefile
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@ -205,6 +205,28 @@ ifeq ($(CONFIG_ARCH_MVEBU),y)
KBUILD_IMAGE := barebox.kwb barebox.kwbuart
endif
barebox.imximg: $(KBUILD_BINARY) FORCE
$(call if_changed,imx_image)
boarddir = $(srctree)/arch/arm/boards
imxcfg-$(CONFIG_MACH_FREESCALE_MX53_SMD) += $(boarddir)/freescale-mx53-smd/flash-header.imxcfg
imxcfg-$(CONFIG_MACH_MX6Q_ARM2) += $(boarddir)/freescale-mx6-arm2/flash-header.imxcfg
imxcfg-$(CONFIG_MACH_CCMX51) += $(boarddir)/ccxmx51/flash-header.imxcfg
imxcfg-$(CONFIG_MACH_TX51) += $(boarddir)/karo-tx51/flash-header-karo-tx51.imxcfg
imxcfg-$(CONFIG_MACH_GUF_VINCELL) += $(boarddir)/guf-vincell/flash-header.imxcfg
imxcfg-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += $(boarddir)/eukrea_cpuimx51/flash-header.imxcfg
imxcfg-$(CONFIG_MACH_FREESCALE_MX25_3STACK) += $(boarddir)/freescale-mx25-3ds/flash-header.imxcfg
imxcfg-$(CONFIG_MACH_FREESCALE_MX35_3STACK) += $(boarddir)/freescale-mx35-3ds/flash-header.imxcfg
imxcfg-$(CONFIG_MACH_TQMA53) += $(boarddir)/tqma53/flash-header.imxcfg
imxcfg-$(CONFIG_MACH_EUKREA_CPUIMX25) += $(boarddir)/eukrea_cpuimx25/flash-header.imxcfg
imxcfg-$(CONFIG_MACH_EUKREA_CPUIMX35) += $(boarddir)/eukrea_cpuimx35/flash-header.imxcfg
imxcfg-$(CONFIG_TX53_REV_1011) += $(boarddir)/karo-tx53/flash-header-tx53-rev1011.imxcfg
imxcfg-$(CONFIG_TX53_REV_XX30) += $(boarddir)/karo-tx53/flash-header-tx53-revxx30.imxcfg
ifneq ($(imxcfg-y),)
CFG_barebox.imximg := $(imxcfg-y)
KBUILD_IMAGE := barebox.imximg
endif
pbl := arch/arm/pbl
$(pbl)/zbarebox.S $(pbl)/zbarebox.bin $(pbl)/zbarebox: barebox.bin FORCE
$(Q)$(MAKE) $(build)=$(pbl) $@

1
arch/arm/boards/ccxmx51/Makefile
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@ -1,4 +1,3 @@
obj-y += ccxmx51.o
lwl-y += flash_header.o
lwl-y += lowlevel.o
obj-$(CONFIG_MACH_CCMX51_BASEBOARD) += ccxmx51js.o

60
arch/arm/boards/ccxmx51/flash-header.imxcfg Normal file
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@ -0,0 +1,60 @@
soc imx51
loadaddr 0x90000000
dcdofs 0x400
wm 32 0x73fa88a0 0x00000200
wm 32 0x73fa850c 0x000020c5
wm 32 0x73fa8510 0x000020c5
wm 32 0x73fa883c 0x00000002
wm 32 0x73fa8848 0x00000002
wm 32 0x73fa84b8 0x000000e7
wm 32 0x73fa84bc 0x00000045
wm 32 0x73fa84c0 0x00000045
wm 32 0x73fa84c4 0x00000045
wm 32 0x73fa84c8 0x00000045
wm 32 0x73fa8820 0x00000000
wm 32 0x73fa84a4 0x00000003
wm 32 0x73fa84a8 0x00000003
wm 32 0x73fa84ac 0x000000e3
wm 32 0x73fa84b0 0x000000e3
wm 32 0x73fa84b4 0x000000e3
wm 32 0x73fa84cc 0x000000e3
wm 32 0x73fa84d0 0x000000e2
wm 32 0x73fa882c 0x00000004
wm 32 0x73fa88a4 0x00000004
wm 32 0x73fa88ac 0x00000004
wm 32 0x73fa88b8 0x00000004
wm 32 0x83fd9000 0x82a20000
wm 32 0x83fd9008 0x82a20000
wm 32 0x83fd9010 0x000ad0d0
wm 32 0x83fd9004 0x3f3584ab
wm 32 0x83fd900c 0x3f3584ab
wm 32 0x83fd9014 0x04008008
wm 32 0x83fd9014 0x0000801a
wm 32 0x83fd9014 0x0000801b
wm 32 0x83fd9014 0x00448019
wm 32 0x83fd9014 0x07328018
wm 32 0x83fd9014 0x04008008
wm 32 0x83fd9014 0x00008010
wm 32 0x83fd9014 0x00008010
wm 32 0x83fd9014 0x06328018
wm 32 0x83fd9014 0x03808019
wm 32 0x83fd9014 0x00408019
wm 32 0x83fd9014 0x00008000
wm 32 0x83fd9014 0x0400800c
wm 32 0x83fd9014 0x0000801e
wm 32 0x83fd9014 0x0000801f
wm 32 0x83fd9014 0x0000801d
wm 32 0x83fd9014 0x0732801c
wm 32 0x83fd9014 0x0400800c
wm 32 0x83fd9014 0x00008014
wm 32 0x83fd9014 0x00008014
wm 32 0x83fd9014 0x0632801c
wm 32 0x83fd9014 0x0380801d
wm 32 0x83fd9014 0x0040801d
wm 32 0x83fd9014 0x00008004
wm 32 0x83fd9000 0xb2a20000
wm 32 0x83fd9008 0xb2a20000
wm 32 0x83fd9010 0x000ad6d0
wm 32 0x83fd9034 0x90000000
wm 32 0x83fd9014 0x00000000

84
arch/arm/boards/ccxmx51/flash_header.c
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@ -1,84 +0,0 @@
#include <common.h>
#include <mach/imx-flash-header.h>
#include <asm/barebox-arm-head.h>
void __naked __flash_header_start go(void)
{
barebox_arm_head();
}
struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
{ .ptr_type = 4, .addr = 0x73fa88a0, .val = 0x00000200, },
{ .ptr_type = 4, .addr = 0x73fa850c, .val = 0x000020c5, },
{ .ptr_type = 4, .addr = 0x73fa8510, .val = 0x000020c5, },
{ .ptr_type = 4, .addr = 0x73fa883c, .val = 0x00000002, },
{ .ptr_type = 4, .addr = 0x73fa8848, .val = 0x00000002, },
{ .ptr_type = 4, .addr = 0x73fa84b8, .val = 0x000000e7, },
{ .ptr_type = 4, .addr = 0x73fa84bc, .val = 0x00000045, },
{ .ptr_type = 4, .addr = 0x73fa84c0, .val = 0x00000045, },
{ .ptr_type = 4, .addr = 0x73fa84c4, .val = 0x00000045, },
{ .ptr_type = 4, .addr = 0x73fa84c8, .val = 0x00000045, },
{ .ptr_type = 4, .addr = 0x73fa8820, .val = 0x00000000, },
{ .ptr_type = 4, .addr = 0x73fa84a4, .val = 0x00000003, },
{ .ptr_type = 4, .addr = 0x73fa84a8, .val = 0x00000003, },
{ .ptr_type = 4, .addr = 0x73fa84ac, .val = 0x000000e3, },
{ .ptr_type = 4, .addr = 0x73fa84b0, .val = 0x000000e3, },
{ .ptr_type = 4, .addr = 0x73fa84b4, .val = 0x000000e3, },
{ .ptr_type = 4, .addr = 0x73fa84cc, .val = 0x000000e3, },
{ .ptr_type = 4, .addr = 0x73fa84d0, .val = 0x000000e2, },
{ .ptr_type = 4, .addr = 0x73fa882c, .val = 0x00000004, },
{ .ptr_type = 4, .addr = 0x73fa88a4, .val = 0x00000004, },
{ .ptr_type = 4, .addr = 0x73fa88ac, .val = 0x00000004, },
{ .ptr_type = 4, .addr = 0x73fa88b8, .val = 0x00000004, },
{ .ptr_type = 4, .addr = 0x83fd9000, .val = 0x82a20000, },
{ .ptr_type = 4, .addr = 0x83fd9008, .val = 0x82a20000, },
{ .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad0d0, },
{ .ptr_type = 4, .addr = 0x83fd9004, .val = 0x3f3584ab, },
{ .ptr_type = 4, .addr = 0x83fd900c, .val = 0x3f3584ab, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801a, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801b, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00448019, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x07328018, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x06328018, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x03808019, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00408019, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008000, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801e, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801f, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801d, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0732801c, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0632801c, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0380801d, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0040801d, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008004, },
{ .ptr_type = 4, .addr = 0x83fd9000, .val = 0xb2a20000, },
{ .ptr_type = 4, .addr = 0x83fd9008, .val = 0xb2a20000, },
{ .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad6d0, },
{ .ptr_type = 4, .addr = 0x83fd9034, .val = 0x90000000, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00000000, },
};
#define APP_DEST 0x90000000
struct imx_flash_header __flash_header_section flash_header = {
.app_code_jump_vector = APP_DEST + 0x1000,
.app_code_barker = APP_CODE_BARKER,
.app_code_csf = 0,
.dcd_ptr_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd),
.super_root_key = 0,
.dcd = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd_barker),
.app_dest = APP_DEST,
.dcd_barker = DCD_BARKER,
.dcd_block_len = sizeof (dcd_entry),
};
unsigned long __image_len_section barebox_len = DCD_BAREBOX_SIZE;

1
arch/arm/boards/eukrea_cpuimx25/Makefile
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@ -17,5 +17,4 @@
#
obj-y += eukrea_cpuimx25.o
lwl-$(CONFIG_ARCH_IMX_INTERNAL_BOOT) += flash_header.o
lwl-y += lowlevel.o

16
arch/arm/boards/eukrea_cpuimx25/flash-header.imxcfg Normal file
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@ -0,0 +1,16 @@
soc imx25
loadaddr 0x80000000
dcdofs 0x400
wm 32 0xb8001010 0x00000004
wm 32 0xb8001000 0x92100000
wm 8 0x80000400 0x12344321
wm 32 0xb8001000 0xa2100000
wm 32 0x80000000 0x12344321
wm 32 0x80000000 0x12344321
wm 32 0xb8001000 0xb2100000
wm 8 0x80000033 0xda
wm 8 0x81000000 0xff
wm 32 0xb8001000 0x82216080
wm 32 0xb8001004 0x00295729
wm 32 0x53f80008 0x20034000

61
arch/arm/boards/eukrea_cpuimx25/flash_header.c
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@ -1,61 +0,0 @@
/*
* (C) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
* (c) 2010 Eukrea Electromatique, Eric Bénard <eric@eukrea.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <mach/imx-flash-header.h>
#include <mach/imx25-regs.h>
#include <asm/barebox-arm-head.h>
void __naked __flash_header_start go(void)
{
barebox_arm_head();
}
struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
{ .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000004, },
{ .ptr_type = 4, .addr = 0xb8001000, .val = 0x92100000, },
{ .ptr_type = 1, .addr = 0x80000400, .val = 0x12344321, },
{ .ptr_type = 4, .addr = 0xb8001000, .val = 0xa2100000, },
{ .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, },
{ .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, },
{ .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2100000, },
{ .ptr_type = 1, .addr = 0x80000033, .val = 0xda, },
{ .ptr_type = 1, .addr = 0x81000000, .val = 0xff, },
{ .ptr_type = 4, .addr = 0xb8001000, .val = 0x82216080, },
{ .ptr_type = 4, .addr = 0xb8001004, .val = 0x00295729, },
{ .ptr_type = 4, .addr = 0x53f80008, .val = 0x20034000, },
};
struct imx_flash_header __flash_header_section flash_header = {
.app_code_jump_vector = DEST_BASE + 0x1000,
.app_code_barker = APP_CODE_BARKER,
.app_code_csf = 0,
.dcd_ptr_ptr = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd),
.super_root_key = 0,
.dcd = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd_barker),
.app_dest = DEST_BASE,
.dcd_barker = DCD_BARKER,
.dcd_block_len = sizeof(dcd_entry),
};
unsigned long __image_len_section barebox_len = DCD_BAREBOX_SIZE;

1
arch/arm/boards/eukrea_cpuimx35/Makefile
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@ -18,4 +18,3 @@
obj-y += eukrea_cpuimx35.o
lwl-y += lowlevel.o
lwl-$(CONFIG_ARCH_IMX_INTERNAL_BOOT) += flash_header.o

19
arch/arm/boards/eukrea_cpuimx35/flash-header.imxcfg Normal file
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@ -0,0 +1,19 @@
soc imx35
loadaddr 0x80000000
dcdofs 0x400
wm 32 0x53F80004 0x00821000
wm 32 0x53F80004 0x00821000
wm 32 0xb8001010 0x00000004
wm 32 0xB8001010 0x0000000C
wm 32 0xb8001004 0x0009572B
wm 32 0xb8001000 0x92220000
wm 8 0x80000400 0xda
wm 32 0xb8001000 0xa2220000
wm 32 0x80000000 0x12344321
wm 32 0x80000000 0x12344321
wm 32 0xb8001000 0xb2220000
wm 8 0x80000033 0xda
wm 8 0x82000000 0xda
wm 32 0xb8001000 0x82224080
wm 32 0xb8001010 0x00000004

43
arch/arm/boards/eukrea_cpuimx35/flash_header.c
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@ -1,43 +0,0 @@
#include <common.h>
#include <mach/imx-flash-header.h>
#include <mach/imx35-regs.h>
#include <asm/barebox-arm-head.h>
void __naked __flash_header_start go(void)
{
barebox_arm_head();
}
struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
{ .ptr_type = 4, .addr = 0x53F80004, .val = 0x00821000, },
{ .ptr_type = 4, .addr = 0x53F80004, .val = 0x00821000, },
{ .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000004, },
{ .ptr_type = 4, .addr = 0xB8001010, .val = 0x0000000C, },
{ .ptr_type = 4, .addr = 0xb8001004, .val = 0x0009572B, },
{ .ptr_type = 4, .addr = 0xb8001000, .val = 0x92220000, },
{ .ptr_type = 1, .addr = 0x80000400, .val = 0xda, },
{ .ptr_type = 4, .addr = 0xb8001000, .val = 0xa2220000, },
{ .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, },
{ .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, },
{ .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2220000, },
{ .ptr_type = 1, .addr = 0x80000033, .val = 0xda, },
{ .ptr_type = 1, .addr = 0x82000000, .val = 0xda, },
{ .ptr_type = 4, .addr = 0xb8001000, .val = 0x82224080, },
{ .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000004, },
};
#define CPUIMX35_DEST_BASE 0x80000000
#define CPUIMX35_FLASH_HEADER_BASE (CPUIMX35_DEST_BASE + FLASH_HEADER_OFFSET)
struct imx_flash_header __flash_header_section flash_header = {
.app_code_jump_vector = CPUIMX35_DEST_BASE + 0x1000,
.app_code_barker = APP_CODE_BARKER,
.app_code_csf = 0,
.dcd_ptr_ptr = CPUIMX35_FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd),
.super_root_key = 0,
.dcd = CPUIMX35_FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd_barker),
.app_dest = CPUIMX35_DEST_BASE,
.dcd_barker = DCD_BARKER,
.dcd_block_len = sizeof(dcd_entry),
};
unsigned long __image_len_section barebox_len = DCD_BAREBOX_SIZE;

1
arch/arm/boards/eukrea_cpuimx51/Makefile
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@ -1,3 +1,2 @@
obj-y += eukrea_cpuimx51.o
lwl-y += flash_header.o
lwl-y += lowlevel.o

59
arch/arm/boards/eukrea_cpuimx51/flash-header.imxcfg Normal file
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@ -0,0 +1,59 @@
soc imx51
dcdofs 0x400
loadaddr 0x90000000
wm 32 0x73fa88a0 0x00000200
wm 32 0x73fa850c 0x000020c5
wm 32 0x73fa8510 0x000020c5
wm 32 0x73fa883c 0x00000002
wm 32 0x73fa8848 0x00000002
wm 32 0x73fa84b8 0x000000e7
wm 32 0x73fa84bc 0x00000045
wm 32 0x73fa84c0 0x00000045
wm 32 0x73fa84c4 0x00000045
wm 32 0x73fa84c8 0x00000045
wm 32 0x73fa8820 0x00000000
wm 32 0x73fa84a4 0x00000003
wm 32 0x73fa84a8 0x00000003
wm 32 0x73fa84ac 0x000000e3
wm 32 0x73fa84b0 0x000000e3
wm 32 0x73fa84b4 0x000000e3
wm 32 0x73fa84cc 0x000000e3
wm 32 0x73fa84d0 0x000000e2
wm 32 0x73fa882c 0x00000004
wm 32 0x73fa88a4 0x00000004
wm 32 0x73fa88ac 0x00000004
wm 32 0x73fa88b8 0x00000004
wm 32 0x83fd9000 0x82a20000
wm 32 0x83fd9008 0x82a20000
wm 32 0x83fd9010 0x000ad0d0
wm 32 0x83fd9004 0x3f3584ab
wm 32 0x83fd900c 0x3f3584ab
wm 32 0x83fd9014 0x04008008
wm 32 0x83fd9014 0x0000801a
wm 32 0x83fd9014 0x0000801b
wm 32 0x83fd9014 0x00448019
wm 32 0x83fd9014 0x07328018
wm 32 0x83fd9014 0x04008008
wm 32 0x83fd9014 0x00008010
wm 32 0x83fd9014 0x00008010
wm 32 0x83fd9014 0x06328018
wm 32 0x83fd9014 0x03808019
wm 32 0x83fd9014 0x00408019
wm 32 0x83fd9014 0x00008000
wm 32 0x83fd9014 0x0400800c
wm 32 0x83fd9014 0x0000801e
wm 32 0x83fd9014 0x0000801f
wm 32 0x83fd9014 0x0000801d
wm 32 0x83fd9014 0x0732801c
wm 32 0x83fd9014 0x0400800c
wm 32 0x83fd9014 0x00008014
wm 32 0x83fd9014 0x00008014
wm 32 0x83fd9014 0x0632801c
wm 32 0x83fd9014 0x0380801d
wm 32 0x83fd9014 0x0040801d
wm 32 0x83fd9014 0x00008004
wm 32 0x83fd9000 0xb2a20000
wm 32 0x83fd9008 0xb2a20000
wm 32 0x83fd9010 0x000ad6d0
wm 32 0x83fd9034 0x90000000
wm 32 0x83fd9014 0x00000000

83
arch/arm/boards/eukrea_cpuimx51/flash_header.c
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@ -1,83 +0,0 @@
#include <common.h>
#include <mach/imx-flash-header.h>
#include <asm/barebox-arm-head.h>
void __naked __flash_header_start go(void)
{
barebox_arm_head();
}
struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
{ .ptr_type = 4, .addr = 0x73fa88a0, .val = 0x00000200, },
{ .ptr_type = 4, .addr = 0x73fa850c, .val = 0x000020c5, },
{ .ptr_type = 4, .addr = 0x73fa8510, .val = 0x000020c5, },
{ .ptr_type = 4, .addr = 0x73fa883c, .val = 0x00000002, },
{ .ptr_type = 4, .addr = 0x73fa8848, .val = 0x00000002, },
{ .ptr_type = 4, .addr = 0x73fa84b8, .val = 0x000000e7, },
{ .ptr_type = 4, .addr = 0x73fa84bc, .val = 0x00000045, },
{ .ptr_type = 4, .addr = 0x73fa84c0, .val = 0x00000045, },
{ .ptr_type = 4, .addr = 0x73fa84c4, .val = 0x00000045, },
{ .ptr_type = 4, .addr = 0x73fa84c8, .val = 0x00000045, },
{ .ptr_type = 4, .addr = 0x73fa8820, .val = 0x00000000, },
{ .ptr_type = 4, .addr = 0x73fa84a4, .val = 0x00000003, },
{ .ptr_type = 4, .addr = 0x73fa84a8, .val = 0x00000003, },
{ .ptr_type = 4, .addr = 0x73fa84ac, .val = 0x000000e3, },
{ .ptr_type = 4, .addr = 0x73fa84b0, .val = 0x000000e3, },
{ .ptr_type = 4, .addr = 0x73fa84b4, .val = 0x000000e3, },
{ .ptr_type = 4, .addr = 0x73fa84cc, .val = 0x000000e3, },
{ .ptr_type = 4, .addr = 0x73fa84d0, .val = 0x000000e2, },
{ .ptr_type = 4, .addr = 0x73fa882c, .val = 0x00000004, },
{ .ptr_type = 4, .addr = 0x73fa88a4, .val = 0x00000004, },
{ .ptr_type = 4, .addr = 0x73fa88ac, .val = 0x00000004, },
{ .ptr_type = 4, .addr = 0x73fa88b8, .val = 0x00000004, },
{ .ptr_type = 4, .addr = 0x83fd9000, .val = 0x82a20000, },
{ .ptr_type = 4, .addr = 0x83fd9008, .val = 0x82a20000, },
{ .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad0d0, },
{ .ptr_type = 4, .addr = 0x83fd9004, .val = 0x3f3584ab, },
{ .ptr_type = 4, .addr = 0x83fd900c, .val = 0x3f3584ab, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801a, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801b, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00448019, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x07328018, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x06328018, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x03808019, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00408019, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008000, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801e, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801f, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801d, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0732801c, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0632801c, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0380801d, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0040801d, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008004, },
{ .ptr_type = 4, .addr = 0x83fd9000, .val = 0xb2a20000, },
{ .ptr_type = 4, .addr = 0x83fd9008, .val = 0xb2a20000, },
{ .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad6d0, },
{ .ptr_type = 4, .addr = 0x83fd9034, .val = 0x90000000, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00000000, },
};
#define APP_DEST 0x90000000
struct imx_flash_header __flash_header_section flash_header = {
.app_code_jump_vector = APP_DEST + 0x1000,
.app_code_barker = APP_CODE_BARKER,
.app_code_csf = 0,
.dcd_ptr_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd),
.super_root_key = 0,
.dcd = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd_barker),
.app_dest = APP_DEST,
.dcd_barker = DCD_BARKER,
.dcd_block_len = sizeof (dcd_entry),
};
unsigned long __image_len_section barebox_len = DCD_BAREBOX_SIZE;

61
arch/arm/boards/freescale-mx25-3ds/3stack.c
View File

@ -42,67 +42,6 @@
#include <mach/devices-imx25.h>
#include <asm/barebox-arm-head.h>
void __naked __flash_header_start go(void)
{
barebox_arm_head();
}
struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
{ .ptr_type = 4, .addr = 0xb8002050, .val = 0x0000d843, },
{ .ptr_type = 4, .addr = 0xb8002054, .val = 0x22252521, },
{ .ptr_type = 4, .addr = 0xb8002058, .val = 0x22220a00, },
#if defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_64MB_DDR2
{ .ptr_type = 4, .addr = 0xb8001004, .val = 0x0076e83a, },
{ .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000304, },
{ .ptr_type = 4, .addr = 0xb8001000, .val = 0x92210000, },
{ .ptr_type = 4, .addr = 0x80000f00, .val = 0x12344321, },
{ .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2210000, },
{ .ptr_type = 1, .addr = 0x82000000, .val = 0xda, },
{ .ptr_type = 1, .addr = 0x83000000, .val = 0xda, },
{ .ptr_type = 1, .addr = 0x81000400, .val = 0xda, },
{ .ptr_type = 1, .addr = 0x80000333, .val = 0xda, },
{ .ptr_type = 4, .addr = 0xb8001000, .val = 0x92210000, },
{ .ptr_type = 4, .addr = 0x80000400, .val = 0x12344321, },
{ .ptr_type = 4, .addr = 0xb8001000, .val = 0xa2210000, },
{ .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, },
{ .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, },
{ .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2210000, },
{ .ptr_type = 1, .addr = 0x80000233, .val = 0xda, },
{ .ptr_type = 1, .addr = 0x81000780, .val = 0xda, },
{ .ptr_type = 1, .addr = 0x81000400, .val = 0xda, },
{ .ptr_type = 4, .addr = 0xb8001000, .val = 0x82216080, },
#elif defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_128MB_MDDR
{ .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000004, },
{ .ptr_type = 4, .addr = 0xb8001000, .val = 0x92100000, },
{ .ptr_type = 1, .addr = 0x80000400, .val = 0x21, },
{ .ptr_type = 4, .addr = 0xb8001000, .val = 0xa2100000, },
{ .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, },
{ .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, },
{ .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2100000, },
{ .ptr_type = 1, .addr = 0x80000033, .val = 0xda, },
{ .ptr_type = 1, .addr = 0x81000000, .val = 0xff, },
{ .ptr_type = 4, .addr = 0xb8001000, .val = 0x82216880, },
{ .ptr_type = 4, .addr = 0xb8001004, .val = 0x00295729, },
#else
#error "Unsupported SDRAM type"
#endif
{ .ptr_type = 4, .addr = 0x53f80008, .val = 0x20034000, },
};
struct imx_flash_header __flash_header_section flash_header = {
.app_code_jump_vector = DEST_BASE + 0x1000,
.app_code_barker = APP_CODE_BARKER,
.app_code_csf = 0,
.dcd_ptr_ptr = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd),
.super_root_key = 0,
.dcd = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd_barker),
.app_dest = DEST_BASE,
.dcd_barker = DCD_BARKER,
.dcd_block_len = sizeof(dcd_entry),
};
unsigned long __image_len_section barebox_len = DCD_BAREBOX_SIZE;
static struct fec_platform_data fec_info = {
.xcv_type = PHY_INTERFACE_MODE_RMII,
.phy_addr = 1,

42
arch/arm/boards/freescale-mx25-3ds/flash-header.imxcfg Normal file
View File

@ -0,0 +1,42 @@
soc imx25
loadaddr 0x80000000
dcdofs 0x400
wm 32 0xb8002050 0x0000d843
wm 32 0xb8002054 0x22252521
wm 32 0xb8002058 0x22220a00
#if defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_64MB_DDR2
wm 32 0xb8001004 0x0076e83a
wm 32 0xb8001010 0x00000304
wm 32 0xb8001000 0x92210000
wm 32 0x80000f00 0x12344321
wm 32 0xb8001000 0xb2210000
wm 8 0x82000000 0xda
wm 8 0x83000000 0xda
wm 8 0x81000400 0xda
wm 8 0x80000333 0xda
wm 32 0xb8001000 0x92210000
wm 32 0x80000400 0x12344321
wm 32 0xb8001000 0xa2210000
wm 32 0x80000000 0x87654321
wm 32 0x80000000 0x87654321
wm 32 0xb8001000 0xb2210000
wm 8 0x80000233 0xda
wm 8 0x81000780 0xda
wm 8 0x81000400 0xda
wm 32 0xb8001000 0x82216080
#elif defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_128MB_MDDR
wm 32 0xb8001010 0x00000004
wm 32 0xb8001000 0x92100000
wm 8 0x80000400 0x21
wm 32 0xb8001000 0xa2100000
wm 32 0x80000000 0x12344321
wm 32 0x80000000 0x12344321
wm 32 0xb8001000 0xb2100000
wm 8 0x80000033 0xda
wm 8 0x81000000 0xff
wm 32 0xb8001000 0x82216880
wm 32 0xb8001004 0x00295729
#else
#error "Unsupported SDRAM type"
#endif
wm 32 0x53f80008 0x20034000

2
arch/arm/boards/freescale-mx35-3ds/Makefile
View File

@ -1,4 +1,2 @@
obj-y += 3stack.o
lwl-y += lowlevel_init.o
lwl-$(CONFIG_ARCH_IMX_INTERNAL_BOOT) += flash_header.o

34
arch/arm/boards/freescale-mx35-3ds/flash-header.imxcfg Normal file
View File

@ -0,0 +1,34 @@
soc imx35
loadaddr 0x80000000
dcdofs 0x400
wm 32 0xb8002050 0x0000d843
wm 32 0xb8002054 0x22252521
wm 32 0xb8002058 0x22220a00
wm 32 0xb8001010 0x00000304
wm 32 0xb8001010 0x0000030c
wm 32 0xb8001004 0x007ffc3f
wm 32 0xb800100c 0x007ffc3f
wm 32 0xb8001000 0x92220000
wm 32 0xb8001008 0x92220000
wm 32 0x80000400 0x12345678
wm 32 0x90000400 0x12345678
wm 32 0xb8001000 0xa2220000
wm 32 0xb8001008 0xa2220000
wm 32 0x80000000 0x87654321
wm 32 0x90000000 0x87654321
wm 32 0x80000000 0x87654321
wm 32 0x90000000 0x87654321
wm 32 0xb8001000 0xb2220000
wm 32 0xb8001008 0xb2220000
wm 8 0x80000233 0xda
wm 8 0x90000233 0xda
wm 8 0x82000780 0xda
wm 8 0x92000780 0xda
wm 8 0x82000400 0xda
wm 8 0x92000400 0xda
wm 32 0xb8001000 0x82226080
wm 32 0xb8001008 0x82226080
wm 32 0xb8001004 0x007ffc3f
wm 32 0xb800100c 0x007ffc3f
wm 32 0xb8001010 0x00000304

72
arch/arm/boards/freescale-mx35-3ds/flash_header.c
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@ -1,72 +0,0 @@
#include <common.h>
#include <mach/imx-flash-header.h>
#include <mach/imx35-regs.h>
#include <asm/barebox-arm-head.h>
void __naked __flash_header_start go(void)
{
barebox_arm_head();
}
struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
{ .ptr_type = 4, .addr = 0xb8002050, .val = 0x0000d843, },
{ .ptr_type = 4, .addr = 0xB8002054, .val = 0x22252521, },
{ .ptr_type = 4, .addr = 0xB8002058, .val = 0x22220a00, },
{ .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000304, },
{ .ptr_type = 4, .addr = 0xB8001010, .val = 0x0000030C, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc3f, },
{ .ptr_type = 4, .addr = 0xB800100C, .val = 0x007ffc3f, },
{ .ptr_type = 4, .addr = 0xB8001000, .val = 0x92220000, },
{ .ptr_type = 4, .addr = 0xB8001008, .val = 0x92220000, },
{ .ptr_type = 4, .addr = 0x80000400, .val = 0x12345678, },
{ .ptr_type = 4, .addr = 0x90000400, .val = 0x12345678, },
{ .ptr_type = 4, .addr = 0xB8001000, .val = 0xA2220000, },
{ .ptr_type = 4, .addr = 0xB8001008, .val = 0xA2220000, },
{ .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, },
{ .ptr_type = 4, .addr = 0x90000000, .val = 0x87654321, },
{ .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, },
{ .ptr_type = 4, .addr = 0x90000000, .val = 0x87654321, },
{ .ptr_type = 4, .addr = 0xB8001000, .val = 0xB2220000, },
{ .ptr_type = 4, .addr = 0xB8001008, .val = 0xB2220000, },
{ .ptr_type = 1, .addr = 0x80000233, .val = 0xda, },
{ .ptr_type = 1, .addr = 0x90000233, .val = 0xda, },
{ .ptr_type = 1, .addr = 0x82000780, .val = 0xda, },
{ .ptr_type = 1, .addr = 0x92000780, .val = 0xda, },
{ .ptr_type = 1, .addr = 0x82000400, .val = 0xda, },
{ .ptr_type = 1, .addr = 0x92000400, .val = 0xda, },
{ .ptr_type = 4, .addr = 0xB8001000, .val = 0x82226080, },
{ .ptr_type = 4, .addr = 0xB8001008, .val = 0x82226080, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc3f, },
{ .ptr_type = 4, .addr = 0xB800100C, .val = 0x007ffc3f, },
{ .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000304, },
};
struct imx_flash_header __flash_header_section flash_header = {
.app_code_jump_vector = DEST_BASE + 0x1000,
.app_code_barker = APP_CODE_BARKER,
.app_code_csf = 0,
.dcd_ptr_ptr = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd),
.super_root_key = 0,
.dcd = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd_barker),
.app_dest = DEST_BASE,
.dcd_barker = DCD_BARKER,
.dcd_block_len = sizeof(dcd_entry),
};
unsigned long __image_len_section barebox_len = DCD_BAREBOX_SIZE;

1
arch/arm/boards/freescale-mx53-smd/Makefile
View File

@ -1,3 +1,2 @@
obj-y += board.o
lwl-y += flash_header.o
lwl-y += lowlevel.o

54
arch/arm/boards/freescale-mx53-smd/flash-header.imxcfg Normal file
View File

@ -0,0 +1,54 @@
loadaddr 0x70000000
soc imx53
dcdofs 0x400
wm 32 0x53fa8554 0x00300000
wm 32 0x53fa8558 0x00300040
wm 32 0x53fa8560 0x00300000
wm 32 0x53fa8564 0x00300040
wm 32 0x53fa8568 0x00300040
wm 32 0x53fa8570 0x00300000
wm 32 0x53fa8574 0x00300000
wm 32 0x53fa8578 0x00300000
wm 32 0x53fa857c 0x00300040
wm 32 0x53fa8580 0x00300040
wm 32 0x53fa8584 0x00300000
wm 32 0x53fa8588 0x00300000
wm 32 0x53fa8590 0x00300040
wm 32 0x53fa8594 0x00300000
wm 32 0x53fa86f0 0x00300000
wm 32 0x53fa86f4 0x00000000
wm 32 0x53fa86fc 0x00000000
wm 32 0x53fa8714 0x00000000
wm 32 0x53fa8718 0x00300000
wm 32 0x53fa871c 0x00300000
wm 32 0x53fa8720 0x00300000
wm 32 0x53fa8724 0x04000000
wm 32 0x53fa8728 0x00300000
wm 32 0x53fa872c 0x00300000
wm 32 0x63fd9088 0x35343535
wm 32 0x63fd9090 0x4d444c44
wm 32 0x63fd907c 0x01370138
wm 32 0x63fd9080 0x013b013c
wm 32 0x63fd9018 0x00011740
wm 32 0x63fd9000 0xc3190000
wm 32 0x63fd900c 0x9f5152e3
wm 32 0x63fd9010 0xb68e8a63
wm 32 0x63fd9014 0x01ff00db
wm 32 0x63fd902c 0x000026d2
wm 32 0x63fd9030 0x009f0e21
wm 32 0x63fd9008 0x12273030
wm 32 0x63fd9004 0x0002002d
wm 32 0x63fd901c 0x00008032
wm 32 0x63fd901c 0x00008033
wm 32 0x63fd901c 0x00028031
wm 32 0x63fd901c 0x052080b0
wm 32 0x63fd901c 0x04008040
wm 32 0x63fd901c 0x0000803a
wm 32 0x63fd901c 0x0000803b
wm 32 0x63fd901c 0x00028039
wm 32 0x63fd901c 0x05208138
wm 32 0x63fd901c 0x04008048
wm 32 0x63fd9020 0x00005800
wm 32 0x63fd9040 0x04b80003
wm 32 0x63fd9058 0x00022227
wm 32 0x63fd901c 0x00000000

102
arch/arm/boards/freescale-mx53-smd/flash_header.c
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@ -1,102 +0,0 @@
/*
* Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <common.h>
#include <asm/byteorder.h>
#include <mach/imx-flash-header.h>
#include <asm/barebox-arm-head.h>
void __naked __flash_header_start go(void)
{
barebox_arm_head();
}
struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
{ .addr = cpu_to_be32(0x53fa8554), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8558), .val = cpu_to_be32(0x00300040), },
{ .addr = cpu_to_be32(0x53fa8560), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8564), .val = cpu_to_be32(0x00300040), },
{ .addr = cpu_to_be32(0x53fa8568), .val = cpu_to_be32(0x00300040), },
{ .addr = cpu_to_be32(0x53fa8570), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8574), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8578), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa857c), .val = cpu_to_be32(0x00300040), },
{ .addr = cpu_to_be32(0x53fa8580), .val = cpu_to_be32(0x00300040), },
{ .addr = cpu_to_be32(0x53fa8584), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8588), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8590), .val = cpu_to_be32(0x00300040), },
{ .addr = cpu_to_be32(0x53fa8594), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa86f0), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa86f4), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa86fc), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa8714), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa8718), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa871c), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8720), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8724), .val = cpu_to_be32(0x04000000), },
{ .addr = cpu_to_be32(0x53fa8728), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa872c), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x63fd9088), .val = cpu_to_be32(0x35343535), },
{ .addr = cpu_to_be32(0x63fd9090), .val = cpu_to_be32(0x4d444c44), },
{ .addr = cpu_to_be32(0x63fd907c), .val = cpu_to_be32(0x01370138), },
{ .addr = cpu_to_be32(0x63fd9080), .val = cpu_to_be32(0x013b013c), },
{ .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00011740), },
{ .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0xc3190000), },
{ .addr = cpu_to_be32(0x63fd900c), .val = cpu_to_be32(0x9f5152e3), },
{ .addr = cpu_to_be32(0x63fd9010), .val = cpu_to_be32(0xb68e8a63), },
{ .addr = cpu_to_be32(0x63fd9014), .val = cpu_to_be32(0x01ff00db), },
{ .addr = cpu_to_be32(0x63fd902c), .val = cpu_to_be32(0x000026d2), },
{ .addr = cpu_to_be32(0x63fd9030), .val = cpu_to_be32(0x009f0e21), },
{ .addr = cpu_to_be32(0x63fd9008), .val = cpu_to_be32(0x12273030), },
{ .addr = cpu_to_be32(0x63fd9004), .val = cpu_to_be32(0x0002002d), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008033), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028031), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x052080b0), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008040), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803a), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803b), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028039), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x05208138), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008048), },
{ .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00005800), },
{ .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x04b80003), },
{ .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00022227), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), },
};
#define APP_DEST 0x70000000
struct imx_flash_header_v2 __flash_header_section flash_header = {
.header.tag = IVT_HEADER_TAG,
.header.length = cpu_to_be16(32),
.header.version = IVT_VERSION,
.entry = APP_DEST + 0x1000,
.dcd_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, dcd),
.boot_data_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, boot_data),
.self = APP_DEST + 0x400,
.boot_data.start = APP_DEST,
.boot_data.size = DCD_BAREBOX_SIZE,
.dcd.header.tag = DCD_HEADER_TAG,
.dcd.header.length = cpu_to_be16(sizeof(struct imx_dcd) + sizeof(dcd_entry)),
.dcd.header.version = DCD_VERSION,
.dcd.command.tag = DCD_COMMAND_WRITE_TAG,
.dcd.command.length = cpu_to_be16(sizeof(struct imx_dcd_command) + sizeof(dcd_entry)),
.dcd.command.param = DCD_COMMAND_WRITE_PARAM,
};

1
arch/arm/boards/freescale-mx6-arm2/Makefile
View File

@ -1,3 +1,2 @@
obj-y += board.o
lwl-y += flash_header.o
lwl-y += lowlevel.o

122
arch/arm/boards/freescale-mx6-arm2/flash-header.imxcfg Normal file
View File

@ -0,0 +1,122 @@
soc imx6
loadaddr 0x10000000
dcdofs 0x400
wm 32 0x020e05a8 0x00000030
wm 32 0x020e05b0 0x00000030
wm 32 0x020e0524 0x00000030
wm 32 0x020e051c 0x00000030
wm 32 0x020e0518 0x00000030
wm 32 0x020e050c 0x00000030
wm 32 0x020e05b8 0x00000030
wm 32 0x020e05c0 0x00000030
wm 32 0x020e05ac 0x00020030
wm 32 0x020e05b4 0x00020030
wm 32 0x020e0528 0x00020030
wm 32 0x020e0520 0x00020030
wm 32 0x020e0514 0x00020030
wm 32 0x020e0510 0x00020030
wm 32 0x020e05bc 0x00020030
wm 32 0x020e05c4 0x00020030
wm 32 0x020e056c 0x00020030
wm 32 0x020e0578 0x00020030
wm 32 0x020e0588 0x00020030
wm 32 0x020e0594 0x00020030
wm 32 0x020e057c 0x00020030
wm 32 0x020e0590 0x00003000
wm 32 0x020e0598 0x00003000
wm 32 0x020e058c 0x00000000
wm 32 0x020e059c 0x00003030
wm 32 0x020e05a0 0x00003030
wm 32 0x020e0784 0x00000030
wm 32 0x020e0788 0x00000030
wm 32 0x020e0794 0x00000030
wm 32 0x020e079c 0x00000030
wm 32 0x020e07a0 0x00000030
wm 32 0x020e07a4 0x00000030
wm 32 0x020e07a8 0x00000030
wm 32 0x020e0748 0x00000030
wm 32 0x020e074c 0x00000030
wm 32 0x020e0750 0x00020000
wm 32 0x020e0758 0x00000000
wm 32 0x020e0774 0x00020000
wm 32 0x020e078c 0x00000030
wm 32 0x020e0798 0x000C0000
wm 32 0x021b081c 0x33333333
wm 32 0x021b0820 0x33333333
wm 32 0x021b0824 0x33333333
wm 32 0x021b0828 0x33333333
wm 32 0x021b481c 0x33333333
wm 32 0x021b4820 0x33333333
wm 32 0x021b4824 0x33333333
wm 32 0x021b4828 0x33333333
wm 32 0x021b0018 0x00081740
wm 32 0x021b001c 0x00008000
wm 32 0x021b000c 0x555A7975
wm 32 0x021b0010 0xFF538E64
wm 32 0x021b0014 0x01FF00DB
wm 32 0x021b002c 0x000026D2
wm 32 0x021b0030 0x005B0E21
wm 32 0x021b0008 0x09444040
wm 32 0x021b0004 0x00025576
wm 32 0x021b0040 0x00000027
wm 32 0x021b0000 0xC31A0000
wm 32 0x021b001c 0x04088032
wm 32 0x021b001c 0x0408803A
wm 32 0x021b001c 0x00008033
wm 32 0x021b001c 0x0000803B
wm 32 0x021b001c 0x00428031
wm 32 0x021b001c 0x00428039
wm 32 0x021b001c 0x09408030
wm 32 0x021b001c 0x09408038
wm 32 0x021b001c 0x04008040
wm 32 0x021b001c 0x04008048
wm 32 0x021b0800 0xA1380003
wm 32 0x021b4800 0xA1380003
wm 32 0x021b0020 0x00005800
wm 32 0x021b0818 0x00022227
wm 32 0x021b4818 0x00022227
wm 32 0x021b083c 0x434B0350
wm 32 0x021b0840 0x034C0359
wm 32 0x021b483c 0x434B0350
wm 32 0x021b4840 0x03650348
wm 32 0x021b0848 0x4436383B
wm 32 0x021b4848 0x39393341
wm 32 0x021b0850 0x35373933
wm 32 0x021b4850 0x48254A36
wm 32 0x021b080c 0x001F001F
wm 32 0x021b0810 0x001F001F
wm 32 0x021b480c 0x00440044
wm 32 0x021b4810 0x00440044
wm 32 0x021b08b8 0x00000800
wm 32 0x021b48b8 0x00000800
wm 32 0x021b001c 0x00000000
wm 32 0x021b0404 0x00011006
/* enable AXI cache for VDOA/VPU/IPU */
wm 32 0x020e0010 0xf00000ff
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
wm 32 0x020e0018 0x007f007f
wm 32 0x020e001c 0x007f007f

171
arch/arm/boards/freescale-mx6-arm2/flash_header.c
View File

@ -1,171 +0,0 @@
/*
* Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <common.h>
#include <asm/byteorder.h>
#include <asm/barebox-arm-head.h>
#include <mach/imx-flash-header.h>
#include <mach/imx6-regs.h>
void __naked __flash_header_start go(void)
{
barebox_arm_head();
}
#define DCD(a, v) { .addr = cpu_to_be32(a), .val = cpu_to_be32(v), }
struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
DCD(MX6_IOMUXC_BASE_ADDR + 0x5a8, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x5b0, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x524, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x51c, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x518, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x50c, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x5b8, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x5c0, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x5ac, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x5b4, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x528, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x520, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x514, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x510, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x5bc, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x5c4, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x56c, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x578, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x588, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x594, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x57c, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x590, 0x00003000),
DCD(MX6_IOMUXC_BASE_ADDR + 0x598, 0x00003000),
DCD(MX6_IOMUXC_BASE_ADDR + 0x58c, 0x00000000),
DCD(MX6_IOMUXC_BASE_ADDR + 0x59c, 0x00003030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x5a0, 0x00003030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x784, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x788, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x794, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x79c, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x7a0, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x7a4, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x7a8, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x748, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x74c, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x750, 0x00020000),
DCD(MX6_IOMUXC_BASE_ADDR + 0x758, 0x00000000),
DCD(MX6_IOMUXC_BASE_ADDR + 0x774, 0x00020000),
DCD(MX6_IOMUXC_BASE_ADDR + 0x78c, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x798, 0x000C0000),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x81c, 0x33333333),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x820, 0x33333333),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x824, 0x33333333),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x828, 0x33333333),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x81c, 0x33333333),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x820, 0x33333333),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x824, 0x33333333),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x828, 0x33333333),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x018, 0x00081740),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00008000),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x00c, 0x555A7975),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x010, 0xFF538E64),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x030, 0x005B0E21),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x008, 0x09444040),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x004, 0x00025576),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x040, 0x00000027),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x000, 0xC31A0000),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x04088032),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x0408803A),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00008033),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x0000803B),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00428031),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00428039),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x09408030),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x09408038),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x04008040),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x04008048),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x800, 0xA1380003),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x800, 0xA1380003),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x020, 0x00005800),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x818, 0x00022227),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x818, 0x00022227),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x83c, 0x434B0350),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x840, 0x034C0359),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x83c, 0x434B0350),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x840, 0x03650348),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x848, 0x4436383B),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x848, 0x39393341),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x850, 0x35373933),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x850, 0x48254A36),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x810, 0x001F001F),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x80c, 0x00440044),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x810, 0x00440044),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00000000),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x404, 0x00011006),
/* enable AXI cache for VDOA/VPU/IPU */
DCD(MX6_IOMUXC_BASE_ADDR + 0x010, 0xf00000ff),
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DCD(MX6_IOMUXC_BASE_ADDR + 0x018, 0x007f007f),
DCD(MX6_IOMUXC_BASE_ADDR + 0x01c, 0x007f007f),
};
#define APP_DEST 0x10000000
struct imx_flash_header_v2 __flash_header_section flash_header = {
.header.tag = IVT_HEADER_TAG,
.header.length = cpu_to_be16(32),
.header.version = IVT_VERSION,
.entry = APP_DEST + 0x1000,
.dcd_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, dcd),
.boot_data_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, boot_data),
.self = APP_DEST + 0x400,
.boot_data.start = APP_DEST,
.boot_data.size = 0x40000,
.dcd.header.tag = DCD_HEADER_TAG,
.dcd.header.length = cpu_to_be16(sizeof(struct imx_dcd) + sizeof(dcd_entry)),
.dcd.header.version = DCD_VERSION,
.dcd.command.tag = DCD_COMMAND_WRITE_TAG,
.dcd.command.length = cpu_to_be16(sizeof(struct imx_dcd_command) + sizeof(dcd_entry)),
.dcd.command.param = DCD_COMMAND_WRITE_PARAM,
};

4
arch/arm/boards/freescale-mx6-sabresd/Makefile
View File

@ -1,3 +1,3 @@
obj-y += board.o
lwl-y += flash_header.o
obj-y += board.o flash-header-mx6-sabresd.dcd.o
extra-y += flash-header-mx6-sabresd.dcd.S flash-header-mx6-sabresd.dcd
lwl-y += lowlevel.o

33
arch/arm/boards/freescale-mx6-sabresd/board.c
View File

@ -40,14 +40,6 @@
#define PHY_ID_AR8031 0x004dd074
#define AR_PHY_ID_MASK 0xffffffff
static int sabresd_mem_init(void)
{
arm_add_mem_device("ram0", 0x10000000, SZ_1G);
return 0;
}
mem_initcall(sabresd_mem_init);
static int ar8031_phy_fixup(struct phy_device *dev)
{
u16 val;
@ -71,27 +63,21 @@ static int ar8031_phy_fixup(struct phy_device *dev)
return 0;
}
static void sabresd_phy_reset(void)
{
/* Reset AR8031 PHY */
gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
udelay(500);
gpio_set_value(IMX_GPIO_NR(1, 25), 1);
}
static int sabresd_devices_init(void)
{
if (!of_machine_is_compatible("fsl,imx6q-sabresd"))
return 0;
armlinux_set_architecture(3980);
devfs_add_partition("disk0", 0, SZ_1M, DEVFS_PARTITION_FIXED, "self0");
devfs_add_partition("disk0", SZ_1M + SZ_1M, SZ_512K, DEVFS_PARTITION_FIXED, "env0");
return 0;
}
device_initcall(sabresd_devices_init);
static int sabresd_coredevices_init(void)
{
sabresd_phy_reset();
if (!of_machine_is_compatible("fsl,imx6q-sabresd"))
return 0;
phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK,
ar8031_phy_fixup);
@ -102,14 +88,17 @@ static int sabresd_coredevices_init(void)
* Do this before the fec initializes but after our
* gpios are available.
*/
fs_initcall(sabresd_coredevices_init);
coredevice_initcall(sabresd_coredevices_init);
static int sabresd_core_init(void)
static int sabresd_postcore_init(void)
{
if (!of_machine_is_compatible("fsl,imx6q-sabresd"))
return 0;
imx6_init_lowlevel();
barebox_set_hostname("sabresd");
return 0;
}
core_initcall(sabresd_core_init);
postcore_initcall(sabresd_postcore_init);

128
arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6-sabresd.imxcfg Normal file
View File

@ -0,0 +1,128 @@
loadaddr 0x10000000
soc imx6
dcdofs 0x400
wm 32 0x20e05a8 0x00000030
wm 32 0x20e05b0 0x00000030
wm 32 0x20e0524 0x00000030
wm 32 0x20e051c 0x00000030
wm 32 0x20e0518 0x00000030
wm 32 0x20e050c 0x00000030
wm 32 0x20e05b8 0x00000030
wm 32 0x20e05c0 0x00000030
wm 32 0x20e05ac 0x00020030
wm 32 0x20e05b4 0x00020030
wm 32 0x20e0528 0x00020030
wm 32 0x20e0520 0x00020030
wm 32 0x20e0514 0x00020030
wm 32 0x20e0510 0x00020030
wm 32 0x20e05bc 0x00020030
wm 32 0x20e05c4 0x00020030
wm 32 0x20e056c 0x00020030
wm 32 0x20e0578 0x00020030
wm 32 0x20e0588 0x00020030
wm 32 0x20e0594 0x00020030
wm 32 0x20e057c 0x00020030
wm 32 0x20e0590 0x00003000
wm 32 0x20e0598 0x00003000
wm 32 0x20e058c 0x00000000
wm 32 0x20e059c 0x00003030
wm 32 0x20e05a0 0x00003030
wm 32 0x20e0784 0x00000030
wm 32 0x20e0788 0x00000030
wm 32 0x20e0794 0x00000030
wm 32 0x20e079c 0x00000030
wm 32 0x20e07a0 0x00000030
wm 32 0x20e07a4 0x00000030
wm 32 0x20e07a8 0x00000030
wm 32 0x20e0748 0x00000030
wm 32 0x20e074c 0x00000030
wm 32 0x20e0750 0x00020000
wm 32 0x20e0758 0x00000000
wm 32 0x20e0774 0x00020000
wm 32 0x20e078c 0x00000030
wm 32 0x20e0798 0x000C0000
wm 32 0x21b081c 0x33333333
wm 32 0x21b0820 0x33333333
wm 32 0x21b0824 0x33333333
wm 32 0x21b0828 0x33333333
wm 32 0x21b481c 0x33333333
wm 32 0x21b4820 0x33333333
wm 32 0x21b4824 0x33333333
wm 32 0x21b4828 0x33333333
wm 32 0x21b0018 0x00081740
wm 32 0x21b001c 0x00008000
wm 32 0x21b000c 0x555A7975
wm 32 0x21b0010 0xFF538E64
wm 32 0x21b0014 0x01FF00DB
wm 32 0x21b002c 0x000026D2
wm 32 0x21b0030 0x005B0E21
wm 32 0x21b0008 0x09444040
wm 32 0x21b0004 0x00025576
wm 32 0x21b0040 0x00000027
wm 32 0x21b0000 0x831A0000
wm 32 0x21b001c 0x04088032
wm 32 0x21b001c 0x0408803A
wm 32 0x21b001c 0x00008033
wm 32 0x21b001c 0x0000803B
wm 32 0x21b001c 0x00428031
wm 32 0x21b001c 0x00428039
wm 32 0x21b001c 0x09408030
wm 32 0x21b001c 0x09408038
wm 32 0x21b001c 0x04008040
wm 32 0x21b001c 0x04008048
wm 32 0x21b0800 0xA1380003
wm 32 0x21b4800 0xA1380003
wm 32 0x21b0020 0x00005800
wm 32 0x21b0818 0x00022227
wm 32 0x21b4818 0x00022227
wm 32 0x21b083c 0x434B0350
wm 32 0x21b0840 0x034C0359
wm 32 0x21b483c 0x434B0350
wm 32 0x21b4840 0x03650348
wm 32 0x21b0848 0x4436383B
wm 32 0x21b4848 0x39393341
wm 32 0x21b0850 0x35373933
wm 32 0x21b4850 0x48254A36
wm 32 0x21b080c 0x001F001F
wm 32 0x21b0810 0x001F001F
wm 32 0x21b480c 0x00440044
wm 32 0x21b4810 0x00440044
wm 32 0x21b08b8 0x00000800
wm 32 0x21b48b8 0x00000800
wm 32 0x21b001c 0x00000000
wm 32 0x21b0404 0x00011006
wm 32 0x020c4068 0x00c03f3f
wm 32 0x020c406c 0x0030fc03
wm 32 0x020c4070 0x0fffc000
wm 32 0x020c4074 0x3ff00000
wm 32 0x020c4078 0x00fff300
wm 32 0x020c407c 0x0f0000c3
wm 32 0x020c4080 0x000003ff
# enable AXI cache for VDOA/VPU/IPU
wm 32 0x20e0010 0xf00000cf
# set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
wm 32 0x20e0018 0x007f007f
wm 32 0x20e001c 0x007f007f

178
arch/arm/boards/freescale-mx6-sabresd/flash_header.c
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@ -1,178 +0,0 @@
/*
* Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <common.h>
#include <asm/byteorder.h>
#include <mach/imx-flash-header.h>
#include <mach/imx6-regs.h>
#include <asm/barebox-arm-head.h>
void __naked __flash_header_start go(void)
{
barebox_arm_head();
}
#define DCD(a, v) { .addr = cpu_to_be32(a), .val = cpu_to_be32(v), }
struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
DCD(MX6_IOMUXC_BASE_ADDR + 0x5a8, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x5b0, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x524, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x51c, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x518, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x50c, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x5b8, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x5c0, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x5ac, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x5b4, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x528, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x520, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x514, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x510, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x5bc, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x5c4, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x56c, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x578, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x588, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x594, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x57c, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x590, 0x00003000),
DCD(MX6_IOMUXC_BASE_ADDR + 0x598, 0x00003000),
DCD(MX6_IOMUXC_BASE_ADDR + 0x58c, 0x00000000),
DCD(MX6_IOMUXC_BASE_ADDR + 0x59c, 0x00003030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x5a0, 0x00003030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x784, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x788, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x794, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x79c, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x7a0, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x7a4, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x7a8, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x748, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x74c, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x750, 0x00020000),
DCD(MX6_IOMUXC_BASE_ADDR + 0x758, 0x00000000),
DCD(MX6_IOMUXC_BASE_ADDR + 0x774, 0x00020000),
DCD(MX6_IOMUXC_BASE_ADDR + 0x78c, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x798, 0x000C0000),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x81c, 0x33333333),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x820, 0x33333333),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x824, 0x33333333),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x828, 0x33333333),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x81c, 0x33333333),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x820, 0x33333333),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x824, 0x33333333),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x828, 0x33333333),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x018, 0x00081740),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00008000),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x00c, 0x555A7975),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x010, 0xFF538E64),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x030, 0x005B0E21),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x008, 0x09444040),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x004, 0x00025576),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x040, 0x00000027),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x000, 0x831A0000),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x04088032),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x0408803A),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00008033),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x0000803B),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00428031),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00428039),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x09408030),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x09408038),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x04008040),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x04008048),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x800, 0xA1380003),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x800, 0xA1380003),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x020, 0x00005800),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x818, 0x00022227),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x818, 0x00022227),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x83c, 0x434B0350),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x840, 0x034C0359),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x83c, 0x434B0350),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x840, 0x03650348),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x848, 0x4436383B),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x848, 0x39393341),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x850, 0x35373933),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x850, 0x48254A36),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x810, 0x001F001F),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x80c, 0x00440044),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x810, 0x00440044),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00000000),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x404, 0x00011006),
DCD(MX6_CCM_BASE_ADDR + 0x068, 0x00c03f3f),
DCD(MX6_CCM_BASE_ADDR + 0x06c, 0x0030fc03),
DCD(MX6_CCM_BASE_ADDR + 0x070, 0x0fffc000),
DCD(MX6_CCM_BASE_ADDR + 0x074, 0x3ff00000),
DCD(MX6_CCM_BASE_ADDR + 0x078, 0x00fff300),
DCD(MX6_CCM_BASE_ADDR + 0x07c, 0x0f0000c3),
DCD(MX6_CCM_BASE_ADDR + 0x080, 0x000003ff),
/* enable AXI cache for VDOA/VPU/IPU */
DCD(MX6_IOMUXC_BASE_ADDR + 0x010, 0xf00000cf),
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DCD(MX6_IOMUXC_BASE_ADDR + 0x018, 0x007f007f),
DCD(MX6_IOMUXC_BASE_ADDR + 0x01c, 0x007f007f),
};
#define APP_DEST CONFIG_TEXT_BASE
struct imx_flash_header_v2 __flash_header_section flash_header = {
.header.tag = IVT_HEADER_TAG,
.header.length = cpu_to_be16(32),
.header.version = IVT_VERSION,
.entry = (u32)_stext,
.dcd_ptr = APP_DEST + FLASH_HEADER_OFFSET + offsetof(struct imx_flash_header_v2, dcd),
.boot_data_ptr = APP_DEST + FLASH_HEADER_OFFSET + offsetof(struct imx_flash_header_v2, boot_data),
.self = APP_DEST + FLASH_HEADER_OFFSET,
.boot_data.start = APP_DEST,
.boot_data.size = barebox_image_size,
.dcd.header.tag = DCD_HEADER_TAG,
.dcd.header.length = cpu_to_be16(sizeof(struct imx_dcd) + sizeof(dcd_entry)),
.dcd.header.version = DCD_VERSION,
.dcd.command.tag = DCD_COMMAND_WRITE_TAG,
.dcd.command.length = cpu_to_be16(sizeof(struct imx_dcd_command) + sizeof(dcd_entry)),
.dcd.command.param = DCD_COMMAND_WRITE_PARAM,
};

11
arch/arm/boards/freescale-mx6-sabresd/lowlevel.c
View File

@ -3,8 +3,15 @@
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
void __naked barebox_arm_reset_vector(void)
extern char __dtb_imx6q_sabresd_start[];
ENTRY_FUNCTION(start_imx6q_sabresd, r0, r1, r2)
{
uint32_t fdt;
arm_cpu_lowlevel_init();
barebox_arm_entry(0x10000000, SZ_1G, 0);
fdt = (uint32_t)__dtb_imx6q_sabresd_start - get_runtime_offset();
barebox_arm_entry(0x10000000, SZ_1G, fdt);
}

2
arch/arm/boards/guf-vincell/Makefile
View File

@ -1,2 +1,2 @@
obj-y += board.o
lwl-y += flash_header.o lowlevel.o
lwl-y += lowlevel.o

3
arch/arm/boards/guf-vincell/flash-header.imxcfg Normal file
View File

@ -0,0 +1,3 @@
soc imx53
loadaddr 0xf8020000
dcdofs 0x400

41
arch/arm/boards/guf-vincell/flash_header.c
View File

@ -1,41 +0,0 @@
/*
* Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <common.h>
#include <sizes.h>
#include <asm/byteorder.h>
#include <asm/barebox-arm-head.h>
#include <mach/imx-flash-header.h>
void __naked __flash_header_start go(void)
{
barebox_arm_head();
}
#define APP_DEST 0xf8020000
struct imx_flash_header_v2 __flash_header_section flash_header = {
.header.tag = IVT_HEADER_TAG,
.header.length = cpu_to_be16(32),
.header.version = IVT_VERSION,
.entry = APP_DEST + 0x1000,
.dcd_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, dcd),
.boot_data_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, boot_data),
.self = APP_DEST + 0x400,
.boot_data.start = APP_DEST,
.boot_data.size = DCD_BAREBOX_SIZE,
};

1
arch/arm/boards/karo-tx51/Makefile
View File

@ -1,3 +1,2 @@
obj-y += tx51.o
lwl-$(CONFIG_ARCH_IMX_INTERNAL_BOOT) += flash_header.o
lwl-y += lowlevel.o

13
arch/arm/boards/karo-tx51/flash-header-karo-tx51.imxcfg Normal file
View File

@ -0,0 +1,13 @@
soc imx51
loadaddr 0x90000000
dcdofs 0x400
wm 32 0x83fd9000 0x80000000
wm 32 0x83fd9014 0x04008008
wm 32 0x83fd9014 0x00008010
wm 32 0x83fd9014 0x00008010
wm 32 0x83fd9014 0x00338018
wm 32 0x83fd9000 0xb2220000
wm 32 0x83fd9004 0xb08564a9
wm 32 0x83fd9034 0x20020000
wm 32 0x83fd9010 0x000a0080
wm 32 0x83fd9014 0x00000000

52
arch/arm/boards/karo-tx51/flash_header.c
View File

@ -1,52 +0,0 @@
/**
* Copyright (C) 2012 Christian Kapeller, <christian.kapeller@cmotion.eu>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <common.h>
#include <asm/barebox-arm-head.h>
#include <mach/imx-flash-header.h>
void __naked __flash_header_start go(void)
{
barebox_arm_head();
}
struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
{ .ptr_type = 4, .addr = 0x83fd9000, .val = 0x80000000, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00338018, },
{ .ptr_type = 4, .addr = 0x83fd9000, .val = 0xb2220000, },
{ .ptr_type = 4, .addr = 0x83fd9004, .val = 0xb08564a9, },
{ .ptr_type = 4, .addr = 0x83fd9034, .val = 0x20020000, },
{ .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000a0080, },
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00000000, },
};
#define APP_DEST 0x90000000
struct imx_flash_header __flash_header_section flash_header = {
.app_code_jump_vector = APP_DEST + 0x1000,
.app_code_barker = APP_CODE_BARKER,
.app_code_csf = 0,
.dcd_ptr_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd),
.super_root_key = 0,
.dcd = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd_barker),
.app_dest = APP_DEST,
.dcd_barker = DCD_BARKER,
.dcd_block_len = sizeof (dcd_entry),
};
unsigned long __image_len_section barebox_len = DCD_BAREBOX_SIZE;

1
arch/arm/boards/karo-tx53/Makefile
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@ -1,3 +1,2 @@
obj-y += board.o
lwl-y += flash_header.o
lwl-y += lowlevel.o

97
arch/arm/boards/karo-tx53/flash-header-tx53-rev1011.imxcfg Normal file
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@ -0,0 +1,97 @@
loadaddr 0x71000000
soc imx53
dcdofs 0x400
wm 32 0x53fd406c 0xffffffff
wm 32 0x53fd4070 0xffffffff
wm 32 0x53fd4074 0xffffffff
wm 32 0x53fd4078 0xffffffff
wm 32 0x53fd407c 0xffffffff
wm 32 0x53fd4080 0xffffffff
wm 32 0x53fd4088 0xffffffff
wm 32 0x53fa8174 0x00000011
wm 32 0x63fd800c 0x00000000
wm 32 0x53fa8554 0x00200000
wm 32 0x53fa8560 0x00200000
wm 32 0x53fa8594 0x00200000
wm 32 0x53fa8584 0x00200000
wm 32 0x53fa8558 0x00200040
wm 32 0x53fa8568 0x00200040
wm 32 0x53fa8590 0x00200040
wm 32 0x53fa857c 0x00200040
wm 32 0x53fa8564 0x00200040
wm 32 0x53fa8580 0x00200040
wm 32 0x53fa8570 0x00200000
wm 32 0x53fa8578 0x00200000
wm 32 0x53fa872c 0x00200000
wm 32 0x53fa8728 0x00200000
wm 32 0x53fa871c 0x00200000
wm 32 0x53fa8718 0x00200000
wm 32 0x53fa8574 0x00280000
wm 32 0x53fa8588 0x00280000
wm 32 0x53fa86f0 0x00280000
wm 32 0x53fa8720 0x00280000
wm 32 0x53fa86fc 0x00000000
wm 32 0x53fa86f4 0x00000200
wm 32 0x53fa8714 0x00000000
wm 32 0x53fa8724 0x06000000
wm 32 0x63fd9088 0x36353b38
wm 32 0x63fd9090 0x49434942
wm 32 0x63fd90f8 0x00000800
wm 32 0x63fd907c 0x01350138
wm 32 0x63fd9080 0x01380139
wm 32 0x63fd9018 0x00001710
wm 32 0x63fd9000 0x84110000
wm 32 0x63fd900c 0x4d5122d2
wm 32 0x63fd9010 0xb6f18a22
wm 32 0x63fd9014 0x00c700db
wm 32 0x63fd902c 0x000026d2
wm 32 0x63fd9030 0x009f000e
wm 32 0x63fd9008 0x12272000
wm 32 0x63fd9004 0x00030012
wm 32 0x63fd901c 0x04008010
wm 32 0x63fd901c 0x00008020
wm 32 0x63fd901c 0x00008020
wm 32 0x63fd901c 0x0a528030
wm 32 0x63fd901c 0x03868031
wm 32 0x63fd901c 0x00068031
wm 32 0x63fd901c 0x00008032
wm 32 0x63fd9020 0x00005800
wm 32 0x63fd9058 0x00033332
wm 32 0x63fd901c 0x00000000
wm 32 0x63fd901c 0x00448031
wm 32 0x63fd901c 0x04008018
wm 32 0x63fd901c 0x00000000
wm 32 0x63fd9040 0x04b80003
wm 32 0x53fa8004 0x00194005
wm 32 0x53fa819c 0x00000000
wm 32 0x53fa81a0 0x00000000
wm 32 0x53fa81a4 0x00000000
wm 32 0x53fa81a8 0x00000000
wm 32 0x53fa81ac 0x00000000
wm 32 0x53fa81b0 0x00000000
wm 32 0x53fa81b4 0x00000000
wm 32 0x53fa81b8 0x00000000
wm 32 0x53fa81dc 0x00000000
wm 32 0x53fa81e0 0x00000000
wm 32 0x53fa8228 0x00000000
wm 32 0x53fa822c 0x00000000
wm 32 0x53fa8230 0x00000000
wm 32 0x53fa8234 0x00000000
wm 32 0x53fa8238 0x00000000
wm 32 0x53fa84ec 0x000000e4
wm 32 0x53fa84f0 0x000000e4
wm 32 0x53fa84f4 0x000000e4
wm 32 0x53fa84f8 0x000000e4
wm 32 0x53fa84fc 0x000000e4
wm 32 0x53fa8500 0x000000e4
wm 32 0x53fa8504 0x000000e4
wm 32 0x53fa8508 0x000000e4
wm 32 0x53fa852c 0x00000004
wm 32 0x53fa8530 0x00000004
wm 32 0x53fa85a0 0x00000004
wm 32 0x53fa85a4 0x00000004
wm 32 0x53fa85a8 0x000000e4
wm 32 0x53fa85ac 0x000000e4
wm 32 0x53fa85b0 0x00000004

127
arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg Normal file
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@ -0,0 +1,127 @@
loadaddr 0x71000000
soc imx53
dcdofs 0x400
wm 32 0x53fd4068 0xffcc0fff
wm 32 0x53fd406c 0x000fffc3
wm 32 0x53fd4070 0x033c0000
wm 32 0x53fd4074 0x00000000
wm 32 0x53fd4078 0x00000000
wm 32 0x53fd407c 0x00fff033
wm 32 0x53fd4080 0x0f00030f
wm 32 0x53fd4084 0xfff00000
wm 32 0x53fd4088 0x00000000
wm 32 0x53fa8174 0x00000011
wm 32 0x53fa8318 0x00000011
wm 32 0x63fd800c 0x00000000
wm 32 0x53fd4014 0x00888944
wm 32 0x53fd4018 0x00016154
wm 32 0x53fa8724 0x04000000
wm 32 0x53fa86f4 0x00000000
wm 32 0x53fa8714 0x00000000
wm 32 0x53fa86fc 0x00000080
wm 32 0x53fa8710 0x00000000
wm 32 0x53fa8708 0x00000040
wm 32 0x53fa8584 0x00280000
wm 32 0x53fa8594 0x00280000
wm 32 0x53fa8560 0x00280000
wm 32 0x53fa8554 0x00280000
wm 32 0x53fa857c 0x00a80040
wm 32 0x53fa8590 0x00a80040
wm 32 0x53fa8568 0x00a80040
wm 32 0x53fa8558 0x00a80040
wm 32 0x53fa8580 0x00280040
wm 32 0x53fa8578 0x00280000
wm 32 0x53fa8564 0x00280040
wm 32 0x53fa8570 0x00280000
wm 32 0x53fa858c 0x000000c0
wm 32 0x53fa855c 0x000000c0
wm 32 0x53fa8574 0x00280000
wm 32 0x53fa8588 0x00280000
wm 32 0x53fa86f0 0x00280000
wm 32 0x53fa8720 0x00280000
wm 32 0x53fa8718 0x00280000
wm 32 0x53fa871c 0x00280000
wm 32 0x53fa8728 0x00280000
wm 32 0x53fa872c 0x00280000
wm 32 0x63fd904c 0x001f001f
wm 32 0x63fd9050 0x001f001f
wm 32 0x63fd907c 0x011e011e
wm 32 0x63fd9080 0x011f0120
wm 32 0x63fd9088 0x3a393d3b
wm 32 0x63fd9090 0x3f3f3f3f
wm 32 0x63fd9018 0x00011740
wm 32 0x63fd9000 0x83190000
wm 32 0x63fd900c 0x3f435316
wm 32 0x63fd9010 0xb66e0a63
wm 32 0x63fd9014 0x01ff00db
wm 32 0x63fd902c 0x000026d2
wm 32 0x63fd9030 0x00430f24
wm 32 0x63fd9008 0x1b221010
wm 32 0x63fd9004 0x00030012
wm 32 0x63fd901c 0x00008032
wm 32 0x63fd901c 0x00008033
wm 32 0x63fd901c 0x00408031
wm 32 0x63fd901c 0x055080b0
wm 32 0x63fd9020 0x00005800
wm 32 0x63fd9058 0x00011112
wm 32 0x63fd90d0 0x00000003
wm 32 0x63fd901c 0x04008010
wm 32 0x63fd901c 0x00008040
wm 32 0x63fd9040 0x0539002b
check 32 while_all_bits_set 0x63fd9040 0x00010000
wm 32 0x63fd901c 0x00048033
wm 32 0x63fd901c 0x00848231
wm 32 0x63fd901c 0x00000000
wm 32 0x63fd9048 0x00000001
check 32 while_all_bits_set 0x63fd9048 0x00000001
wm 32 0x63fd901c 0x00048031
wm 32 0x63fd901c 0x00008033
wm 32 0x63fd901c 0x04008010
wm 32 0x63fd901c 0x00048033
wm 32 0x63fd907c 0x90000000
check 32 while_all_bits_set 0x63fd907c 0x90000000
wm 32 0x63fd901c 0x00008033
wm 32 0x63fd901c 0x00000000
wm 32 0x63fd901c 0x04008010
wm 32 0x63fd901c 0x00048033
wm 32 0x63fd90a4 0x00000010
check 32 while_all_bits_set 0x63fd90a4 0x00000010
wm 32 0x63fd901c 0x00008033
wm 32 0x63fd901c 0x04008010
wm 32 0x63fd901c 0x00048033
wm 32 0x63fd90a0 0x00000010
check 32 while_all_bits_set 0x63fd90a0 0x00000010
wm 32 0x63fd901c 0x00008033
wm 32 0x63fd901c 0x00000000
wm 32 0x53fa8004 0x00194005
wm 32 0x53fa819c 0x00000000
wm 32 0x53fa81a0 0x00000000
wm 32 0x53fa81a4 0x00000000
wm 32 0x53fa81a8 0x00000000
wm 32 0x53fa81ac 0x00000000
wm 32 0x53fa81b0 0x00000000
wm 32 0x53fa81b4 0x00000000
wm 32 0x53fa81b8 0x00000000
wm 32 0x53fa81dc 0x00000000
wm 32 0x53fa81e0 0x00000000
wm 32 0x53fa8228 0x00000000
wm 32 0x53fa822c 0x00000000
wm 32 0x53fa8230 0x00000000
wm 32 0x53fa8234 0x00000000
wm 32 0x53fa8238 0x00000000
wm 32 0x53fa84ec 0x000000e4
wm 32 0x53fa84f0 0x000000e4
wm 32 0x53fa84f4 0x000000e4
wm 32 0x53fa84f8 0x000000e4
wm 32 0x53fa84fc 0x000000e4
wm 32 0x53fa8500 0x000000e4
wm 32 0x53fa8504 0x000000e4
wm 32 0x53fa8508 0x000000e4
wm 32 0x53fa852c 0x00000004
wm 32 0x53fa8530 0x00000004
wm 32 0x53fa85a0 0x00000004
wm 32 0x53fa85a4 0x00000004
wm 32 0x53fa85a8 0x000000e4
wm 32 0x53fa85ac 0x000000e4
wm 32 0x53fa85b0 0x00000004

73
arch/arm/boards/karo-tx53/flash_header.c
View File

@ -1,73 +0,0 @@
/*
* Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <common.h>
#include <asm/byteorder.h>
#include <mach/imx-flash-header.h>
#include <asm/barebox-arm-head.h>
void __naked __flash_header_start go(void)
{
barebox_arm_imx_fcb_head();
}
/*
* FIXME: These are the dcd values for a Ka-Ro TX53 1011 which
* is not in production. It has 1GB DDR2 memory.
*/
#ifdef CONFIG_TX53_REV_1011
#define DCD_NAME_1011 struct imx_dcd_v2_entry __dcd_entry_section dcd_entry
#include "dcd-data-1011.h"
#elif defined(CONFIG_TX53_REV_XX30)
#define DCD_NAME_XX30 u32 __dcd_entry_section dcd_entry
#include "dcd-data-xx30.h"
#endif
#define APP_DEST 0x71000000
int tx53_dcdentry_size = sizeof(dcd_entry);
void *tx53_dcd_entry = &dcd_entry;
struct imx_flash_header_v2 __flash_header_section flash_header = {
.header.tag = IVT_HEADER_TAG,
.header.length = cpu_to_be16(32),
.header.version = IVT_VERSION,
.entry = APP_DEST + 0x1000,
.dcd_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, dcd),
.boot_data_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, boot_data),
.self = APP_DEST + 0x400,
.boot_data.start = APP_DEST,
.boot_data.size = DCD_BAREBOX_SIZE,
.dcd.header.tag = DCD_HEADER_TAG,
.dcd.header.length = cpu_to_be16(sizeof(struct imx_dcd) + sizeof(dcd_entry)),
.dcd.header.version = DCD_VERSION,
.dcd.command.tag = DCD_COMMAND_WRITE_TAG,
#ifdef CONFIG_TX53_REV_1011
.dcd.command.length = cpu_to_be16(sizeof(struct imx_dcd_command) + sizeof(dcd_entry)),
#elif defined(CONFIG_TX53_REV_XX30)
.dcd.command.length = cpu_to_be16(0x21c),
#endif
.dcd.command.param = DCD_COMMAND_WRITE_PARAM,
};

66
arch/arm/boards/tqma53/flash-header.imxcfg Normal file
View File

@ -0,0 +1,66 @@
soc imx53
loadaddr 0x70000000
dcdofs 0x400
/* IOMUX */
wm 32 0x53fa8554 cpu_to_be32(0x00300000
wm 32 0x53fa8558 cpu_to_be32(0x00300040
wm 32 0x53fa8560 cpu_to_be32(0x00300000
wm 32 0x53fa8564 cpu_to_be32(0x00300040
wm 32 0x53fa8568 cpu_to_be32(0x00300040
wm 32 0x53fa8570 cpu_to_be32(0x00300000
wm 32 0x53fa8574 cpu_to_be32(0x00300000
wm 32 0x53fa8578 cpu_to_be32(0x00300000
wm 32 0x53fa857c cpu_to_be32(0x00300040
wm 32 0x53fa8580 cpu_to_be32(0x00300040
wm 32 0x53fa8584 cpu_to_be32(0x00300000
wm 32 0x53fa8588 cpu_to_be32(0x00300000
wm 32 0x53fa8590 cpu_to_be32(0x00300040
wm 32 0x53fa8594 cpu_to_be32(0x00300000
wm 32 0x53fa86f0 cpu_to_be32(0x00300000
wm 32 0x53fa86f4 cpu_to_be32(0x00000000
wm 32 0x53fa86fc cpu_to_be32(0x00000000
wm 32 0x53fa8714 cpu_to_be32(0x00000000
wm 32 0x53fa8718 cpu_to_be32(0x00300000
wm 32 0x53fa871c cpu_to_be32(0x00300000
wm 32 0x53fa8720 cpu_to_be32(0x00300000
wm 32 0x53fa8724 cpu_to_be32(0x04000000
wm 32 0x53fa8728 cpu_to_be32(0x00300000
wm 32 0x53fa872c cpu_to_be32(0x00300000
/* ESDCTL */
wm 32 0x63fd9088 cpu_to_be32(0x35343535
wm 32 0x63fd9090 cpu_to_be32(0x4d444c44
wm 32 0x63fd907c cpu_to_be32(0x01370138
wm 32 0x63fd9080 cpu_to_be32(0x013b013c
wm 32 0x63fd90f8 cpu_to_be32(0x00000800
#ifdef CONFIG_MACH_TQMA53_1GB_RAM
/* sync with u-boot: add WALAT for 4 chip variant */
wm 32 0x63fd9018 cpu_to_be32(0x00011740
wm 32 0x63fd9000 cpu_to_be32(0xc3190000
#else
wm 32 0x63fd9018 cpu_to_be32(0x00101740
wm 32 0x63fd9000 cpu_to_be32(0x83190000
#endif
wm 32 0x63fd900c cpu_to_be32(0x9f5152e3
wm 32 0x63fd9010 cpu_to_be32(0xb68e8a63
wm 32 0x63fd9014 cpu_to_be32(0x01ff00db
wm 32 0x63fd902c cpu_to_be32(0x000026d2
/* Engcm12377 / errata sheet 03/2013 */
wm 32 0x63fd9030 cpu_to_be32(0x009f0e23
wm 32 0x63fd9008 cpu_to_be32(0x12273030
wm 32 0x63fd9004 cpu_to_be32(0x0002002d
wm 32 0x63fd901c cpu_to_be32(0x00008032
wm 32 0x63fd901c cpu_to_be32(0x00008033
wm 32 0x63fd901c cpu_to_be32(0x00028031
wm 32 0x63fd901c cpu_to_be32(0x052080b0
wm 32 0x63fd901c cpu_to_be32(0x04008040
wm 32 0x63fd901c cpu_to_be32(0x0000803a
wm 32 0x63fd901c cpu_to_be32(0x0000803b
wm 32 0x63fd901c cpu_to_be32(0x00028039
wm 32 0x63fd901c cpu_to_be32(0x05208138
wm 32 0x63fd901c cpu_to_be32(0x04008048
wm 32 0x63fd9020 cpu_to_be32(0x00005800
/* prevent reserved value, use default TZQ_CS */
wm 32 0x63fd9040 cpu_to_be32(0x05380003
wm 32 0x63fd9058 cpu_to_be32(0x00022227
wm 32 0x63fd901C cpu_to_be32(0x00000000

4
arch/arm/configs/freescale-mx6-sabresd_defconfig
View File

@ -1,5 +1,5 @@
CONFIG_ARCH_IMX=y
CONFIG_ARCH_IMX6=y
CONFIG_IMX_MULTI_BOARDS=y
CONFIG_MACH_SABRESD=y
CONFIG_IMX_IIM=y
CONFIG_IMX_IIM_FUSE_BLOW=y
@ -8,6 +8,7 @@ CONFIG_CMD_ARM_MMUINFO=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_MMU=y
CONFIG_TEXT_BASE=0x08f80000
CONFIG_MALLOC_SIZE=0x4000000
CONFIG_MALLOC_TLSF=y
CONFIG_KALLSYMS=y
@ -27,7 +28,6 @@ CONFIG_CMD_READLINE=y
CONFIG_CMD_MENU=y
CONFIG_CMD_MENU_MANAGEMENT=y
CONFIG_CMD_TIME=y
CONFIG_CMD_DIRNAME=y
CONFIG_CMD_TFTP=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_MEMINFO=y

1
arch/arm/dts/Makefile
View File

@ -56,6 +56,7 @@ pbl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o
pbl-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o
pbl-$(CONFIG_MACH_SOLIDRUN_HUMMINGBOARD) += imx6dl-hummingboard.dtb.o
pbl-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o
pbl-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o
pbl-$(CONFIG_MACH_GUF_SANTARO) += imx6q-guf-santaro.dtb.o
pbl-$(CONFIG_MACH_NITROGEN6X) += imx6q-nitrogen6x.dtb.o imx6dl-nitrogen6x.dtb.o
pbl-$(CONFIG_MACH_UDOO) += imx6q-udoo.dtb.o

5
arch/arm/dts/imx6q-sabresd.dts
View File

@ -21,6 +21,11 @@
chosen {
linux,stdout-path = &uart1;
environment@0 {
compatible = "barebox,environment";
device-path = &usdhc3, "partname:barebox-environment";
};
};
};

13
arch/arm/dts/imx6qdl-sabresd.dtsi
View File

@ -311,4 +311,17 @@
cd-gpios = <&gpio2 0 0>;
wp-gpios = <&gpio2 1 0>;
status = "okay";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "barebox";
reg = <0x0 0x80000>;
};
partition@1 {
label = "barebox-environment";
reg = <0x80000 0x80000>;
};
};

8
arch/arm/mach-imx/Kconfig
View File

@ -231,6 +231,10 @@ config MACH_SABRELITE
select HAVE_DEFAULT_ENVIRONMENT_NEW
select HAVE_PBL_MULTI_IMAGES
config MACH_SABRESD
bool "Freescale i.MX6 SabreSD"
select ARCH_IMX6
config MACH_NITROGEN6X
bool "BoundaryDevices Nitrogen6x"
select ARCH_IMX6
@ -472,10 +476,6 @@ config MACH_MX6Q_ARM2
bool "Freescale i.MX6q Armadillo2"
select ARCH_IMX6
config MACH_SABRESD
bool "Freescale i.MX6 SabreSD"
select ARCH_IMX6
endchoice
# ----------------------------------------------------------

5
images/Makefile.imx
View File

@ -119,6 +119,11 @@ CFG_start_imx6dl_sabrelite.pblx.imximg = $(board)/freescale-mx6-sabrelite/flash-
FILE_barebox-freescale-imx6dl-sabrelite.img = start_imx6dl_sabrelite.pblx.imximg
image-$(CONFIG_MACH_SABRELITE) += barebox-freescale-imx6dl-sabrelite.img
pblx-$(CONFIG_MACH_SABRESD) += start_imx6q_sabresd
CFG_start_imx6q_sabresd.pblx.imximg = $(board)/freescale-mx6-sabresd/flash-header-mx6-sabresd.imxcfg
FILE_barebox-freescale-imx6q-sabresd.img = start_imx6q_sabresd.pblx.imximg
image-$(CONFIG_MACH_SABRESD) += barebox-freescale-imx6q-sabresd.img
pblx-$(CONFIG_MACH_SOLIDRUN_HUMMINGBOARD) += start_imx6dl_hummingboard
CFG_start_imx6dl_hummingboard.pblx.imximg = $(board)/solidrun-hummingboard/flash-header-solidrun-hummingboard.imxcfg
FILE_barebox-solidrun-imx6dl-hummingboard.img = start_imx6dl_hummingboard.pblx.imximg

4
scripts/Makefile.lib
View File

@ -374,7 +374,9 @@ cmd_imximage_S_dcd= \
echo '.balign STRUCT_ALIGNMENT'; \
) > $@
imxcfg_cpp_flags = -Wp,-MD,$(depfile) -nostdinc -x assembler-with-cpp
imxcfg_cpp_flags = -Wp,-MD,$(depfile) -nostdinc -x assembler-with-cpp \
-I $(srctree)/include -I $(MACH)/include \
-include $(srctree)/include/generated/autoconf.h
dcd-tmp = $(subst $(comma),_,$(dot-target).dcd.tmp)