macb: add cadence Gigabit GEM support
based on the kernel code detect it via IP version In the GEM we can use a full packet buffer for receive but the buffer size need to be 64bit size aligned. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Jean-Christophe PLAGNIOL-VILLARD
Sascha Hauer
parent
aa2095304a
commit
9c305a0dbe
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@ -53,10 +53,10 @@
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#define MACB_RX_BUFFER_SIZE 128
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#define RX_BUFFER_MULTIPLE 64 /* bytes */
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#define RX_RING_SIZE 32 /* must be power of 2 */
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#define RX_NB_PACKET 10
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#define TX_RING_SIZE 2 /* must be power of 2 */
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#define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
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#define RX_RING_BYTES(bp) (sizeof(struct macb_dma_desc) * bp->rx_ring_size)
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#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
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struct macb_device {
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@ -71,8 +71,12 @@ struct macb_device {
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struct macb_dma_desc *rx_ring;
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struct macb_dma_desc *tx_ring;
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int rx_buffer_size;
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int rx_ring_size;
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int phy_addr;
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struct clk *pclk;
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const struct device_d *dev;
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struct eth_device netdev;
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@ -81,8 +85,20 @@ struct macb_device {
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struct mii_bus miibus;
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unsigned int phy_flags;
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bool is_gem;
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};
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static inline bool macb_is_gem(struct macb_device *macb)
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{
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return macb->is_gem;
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}
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static inline bool read_is_gem(struct macb_device *macb)
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{
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return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2;
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}
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static int macb_send(struct eth_device *edev, void *packet,
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int length)
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{
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@ -140,7 +156,7 @@ static void reclaim_rx_buffers(struct macb_device *macb,
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while (i > new_tail) {
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macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
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i++;
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if (i > RX_RING_SIZE)
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if (i > macb->rx_ring_size)
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i = 0;
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}
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@ -153,6 +169,37 @@ static void reclaim_rx_buffers(struct macb_device *macb,
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macb->rx_tail = new_tail;
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}
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static int gem_recv(struct eth_device *edev)
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{
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struct macb_device *macb = edev->priv;
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unsigned int rx_tail = macb->rx_tail;
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void *buffer;
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int length;
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u32 status;
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dev_dbg(macb->dev, "%s\n", __func__);
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for (;;) {
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barrier();
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if (!(macb->rx_ring[rx_tail].addr & MACB_BIT(RX_USED)))
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return -1;
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barrier();
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status = macb->rx_ring[rx_tail].ctrl;
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length = MACB_BFEXT(RX_FRMLEN, status);
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if (status & MACB_BIT(RX_SOF)) {
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buffer = macb->rx_buffer + macb->rx_buffer_size * macb->rx_tail;
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net_receive(buffer, length);
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macb->rx_ring[rx_tail].ctrl &= ~MACB_BIT(RX_USED);
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barrier();
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}
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rx_tail++;
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macb->rx_tail++;
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}
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return 0;
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}
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static int macb_recv(struct eth_device *edev)
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{
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struct macb_device *macb = edev->priv;
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@ -176,12 +223,12 @@ static int macb_recv(struct eth_device *edev)
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}
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if (status & MACB_BIT(RX_EOF)) {
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buffer = macb->rx_buffer + MACB_RX_BUFFER_SIZE * macb->rx_tail;
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buffer = macb->rx_buffer + macb->rx_buffer_size * macb->rx_tail;
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length = MACB_BFEXT(RX_FRMLEN, status);
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if (wrapped) {
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unsigned int headlen, taillen;
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headlen = MACB_RX_BUFFER_SIZE * (RX_RING_SIZE
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headlen = macb->rx_buffer_size * (macb->rx_ring_size
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- macb->rx_tail);
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taillen = length - headlen;
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memcpy((void *)NetRxPackets[0],
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@ -192,11 +239,11 @@ static int macb_recv(struct eth_device *edev)
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}
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net_receive(buffer, length);
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if (++rx_tail >= RX_RING_SIZE)
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if (++rx_tail >= macb->rx_ring_size)
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rx_tail = 0;
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reclaim_rx_buffers(macb, rx_tail);
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} else {
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if (++rx_tail >= RX_RING_SIZE) {
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if (++rx_tail >= macb->rx_ring_size) {
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wrapped = 1;
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rx_tail = 0;
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}
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@ -214,13 +261,17 @@ static void macb_adjust_link(struct eth_device *edev)
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reg = macb_readl(macb, NCFGR);
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reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
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if (macb_is_gem(macb))
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reg &= ~GEM_BIT(GBE);
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if (edev->phydev->duplex)
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reg |= MACB_BIT(FD);
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if (edev->phydev->speed == SPEED_100)
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reg |= MACB_BIT(SPD);
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if (edev->phydev->speed == SPEED_1000)
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reg |= GEM_BIT(GBE);
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macb_writel(macb, NCFGR, reg);
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macb_or_gem_writel(macb, NCFGR, reg);
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}
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static int macb_open(struct eth_device *edev)
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@ -238,6 +289,29 @@ static int macb_open(struct eth_device *edev)
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macb->interface);
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}
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/*
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* Configure the receive DMA engine
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* - use the correct receive buffer size
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* - set the possibility to use INCR16 bursts
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* (if not supported by FIFO, it will fallback to default)
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* - set both rx/tx packet buffers to full memory size
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* - set discard rx packets if no DMA resource
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* These are configurable parameters for GEM.
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*/
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static void macb_configure_dma(struct macb_device *bp)
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{
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u32 dmacfg;
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if (macb_is_gem(bp)) {
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dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
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dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
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dmacfg |= GEM_BF(FBLDO, 16);
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dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
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dmacfg |= GEM_BIT(DDRP);
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gem_writel(bp, DMACFG, dmacfg);
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}
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}
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static void macb_init(struct macb_device *macb)
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{
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unsigned long paddr, val = 0;
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@ -252,12 +326,12 @@ static void macb_init(struct macb_device *macb)
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/* initialize DMA descriptors */
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paddr = (ulong)macb->rx_buffer;
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for (i = 0; i < RX_RING_SIZE; i++) {
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for (i = 0; i < macb->rx_ring_size; i++) {
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macb->rx_ring[i].addr = paddr;
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macb->rx_ring[i].ctrl = 0;
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paddr += MACB_RX_BUFFER_SIZE;
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paddr += macb->rx_buffer_size;
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}
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macb->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
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macb->rx_ring[macb->rx_ring_size - 1].addr |= MACB_BIT(RX_WRAP);
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for (i = 0; i < TX_RING_SIZE; i++) {
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macb->tx_ring[i].addr = 0;
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@ -267,18 +341,29 @@ static void macb_init(struct macb_device *macb)
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macb->rx_tail = macb->tx_head = macb->tx_tail = 0;
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macb_configure_dma(macb);
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macb_writel(macb, RBQP, (ulong)macb->rx_ring);
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macb_writel(macb, TBQP, (ulong)macb->tx_ring);
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if (macb->interface == PHY_INTERFACE_MODE_RMII)
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val |= MACB_BIT(RMII);
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else
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val &= ~MACB_BIT(RMII);
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switch(macb->interface) {
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case PHY_INTERFACE_MODE_RGMII:
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val = GEM_BIT(RGMII);
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break;
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case PHY_INTERFACE_MODE_RMII:
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if (IS_ENABLED(CONFIG_ARCH_AT91))
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val = MACB_BIT(RMII) | MACB_BIT(CLKEN);
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else
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val = 0;
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break;
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default:
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if (IS_ENABLED(CONFIG_ARCH_AT91))
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val = MACB_BIT(CLKEN);
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else
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val = MACB_BIT(MII);
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}
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#if defined(CONFIG_ARCH_AT91)
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val |= MACB_BIT(CLKEN);
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#endif
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macb_writel(macb, USRIO, val);
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macb_or_gem_writel(macb, USRIO, val);
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}
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@ -386,12 +471,75 @@ static int macb_set_ethaddr(struct eth_device *edev, unsigned char *adr)
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dev_dbg(macb->dev, "%s\n", __func__);
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/* set hardware address */
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macb_writel(macb, SA1B, adr[0] | adr[1] << 8 | adr[2] << 16 | adr[3] << 24);
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macb_writel(macb, SA1T, adr[4] | adr[5] << 8);
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macb_or_gem_writel(macb, SA1B, adr[0] | adr[1] << 8 | adr[2] << 16 | adr[3] << 24);
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macb_or_gem_writel(macb, SA1T, adr[4] | adr[5] << 8);
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return 0;
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}
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static u32 gem_mdc_clk_div(struct macb_device *bp)
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{
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u32 config;
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unsigned long pclk_hz = clk_get_rate(bp->pclk);
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if (pclk_hz <= 20000000)
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config = GEM_BF(CLK, GEM_CLK_DIV8);
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else if (pclk_hz <= 40000000)
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config = GEM_BF(CLK, GEM_CLK_DIV16);
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else if (pclk_hz <= 80000000)
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config = GEM_BF(CLK, GEM_CLK_DIV32);
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else if (pclk_hz <= 120000000)
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config = GEM_BF(CLK, GEM_CLK_DIV48);
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else if (pclk_hz <= 160000000)
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config = GEM_BF(CLK, GEM_CLK_DIV64);
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else
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config = GEM_BF(CLK, GEM_CLK_DIV96);
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return config;
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}
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static u32 macb_mdc_clk_div(struct macb_device *bp)
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{
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u32 config;
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unsigned long pclk_hz;
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if (macb_is_gem(bp))
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return gem_mdc_clk_div(bp);
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pclk_hz = clk_get_rate(bp->pclk);
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if (pclk_hz <= 20000000)
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config = MACB_BF(CLK, MACB_CLK_DIV8);
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else if (pclk_hz <= 40000000)
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config = MACB_BF(CLK, MACB_CLK_DIV16);
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else if (pclk_hz <= 80000000)
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config = MACB_BF(CLK, MACB_CLK_DIV32);
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else
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config = MACB_BF(CLK, MACB_CLK_DIV64);
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return config;
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}
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/*
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* Get the DMA bus width field of the network configuration register that we
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* should program. We find the width from decoding the design configuration
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* register to find the maximum supported data bus width.
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*/
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static u32 macb_dbw(struct macb_device *bp)
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{
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if (!macb_is_gem(bp))
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return 0;
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switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
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case 4:
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return GEM_BF(DBW, GEM_DBW128);
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case 2:
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return GEM_BF(DBW, GEM_DBW64);
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case 1:
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default:
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return GEM_BF(DBW, GEM_DBW32);
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}
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}
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static void macb_reset_hw(struct macb_device *bp)
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{
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/* Disable RX and TX forcefully */
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@ -409,14 +557,35 @@ static void macb_reset_hw(struct macb_device *bp)
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macb_readl(bp, ISR);
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}
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static void macb_init_rx_buffer_size(struct macb_device *bp, size_t size)
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{
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if (!macb_is_gem(bp)) {
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bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
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bp->rx_ring_size = roundup(RX_NB_PACKET * PKTSIZE / MACB_RX_BUFFER_SIZE, 2);
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} else {
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bp->rx_buffer_size = size;
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bp->rx_ring_size = RX_NB_PACKET;
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if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
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dev_dbg(bp->dev,
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"RX buffer must be multiple of %d bytes, expanding\n",
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RX_BUFFER_MULTIPLE);
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bp->rx_buffer_size =
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roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
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}
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bp->rx_buffer = dma_alloc_coherent(bp->rx_buffer_size * bp->rx_ring_size);
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}
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dev_dbg(bp->dev, "[%d] rx_buffer_size [%d]\n",
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size, bp->rx_buffer_size);
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}
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static int macb_probe(struct device_d *dev)
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{
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struct eth_device *edev;
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struct macb_device *macb;
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unsigned long macb_hz;
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u32 ncfgr;
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struct at91_ether_platform_data *pdata;
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struct clk *pclk;
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if (!dev->platform_data) {
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dev_err(dev, "macb: no platform_data\n");
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@ -432,7 +601,6 @@ static int macb_probe(struct device_d *dev)
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edev->open = macb_open;
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edev->send = macb_send;
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edev->recv = macb_recv;
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edev->halt = macb_halt;
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edev->get_ethaddr = pdata->get_ethaddr ? pdata->get_ethaddr : macb_get_ethaddr;
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edev->set_ethaddr = macb_set_ethaddr;
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@ -451,8 +619,9 @@ static int macb_probe(struct device_d *dev)
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macb->phy_flags = pdata->phy_flags;
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macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE * RX_RING_SIZE);
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macb->rx_ring = dma_alloc_coherent(RX_RING_BYTES);
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macb_init_rx_buffer_size(macb, PKTSIZE);
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macb->rx_buffer = dma_alloc_coherent(macb->rx_buffer_size * macb->rx_ring_size);
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macb->rx_ring = dma_alloc_coherent(RX_RING_BYTES(macb));
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macb->tx_ring = dma_alloc_coherent(TX_RING_BYTES);
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macb->regs = dev_request_mem_region(dev, 0);
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@ -461,29 +630,25 @@ static int macb_probe(struct device_d *dev)
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* Do some basic initialization so that we at least can talk
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* to the PHY
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*/
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pclk = clk_get(dev, "macb_clk");
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if (IS_ERR(pclk)) {
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macb->pclk = clk_get(dev, "macb_clk");
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if (IS_ERR(macb->pclk)) {
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dev_err(dev, "no macb_clk\n");
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return PTR_ERR(pclk);
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return PTR_ERR(macb->pclk);
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}
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clk_enable(pclk);
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clk_enable(macb->pclk);
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if (macb_is_gem(macb))
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edev->recv = gem_recv;
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else
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edev->recv = macb_recv;
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macb->is_gem = read_is_gem(macb);
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macb_reset_hw(macb);
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macb_hz = clk_get_rate(pclk);
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if (macb_hz < 20000000)
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ncfgr = MACB_BF(CLK, MACB_CLK_DIV8);
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else if (macb_hz < 40000000)
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ncfgr = MACB_BF(CLK, MACB_CLK_DIV16);
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else if (macb_hz < 80000000)
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ncfgr = MACB_BF(CLK, MACB_CLK_DIV32);
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else
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ncfgr = MACB_BF(CLK, MACB_CLK_DIV64);
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ncfgr = macb_mdc_clk_div(macb);
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ncfgr |= MACB_BIT(PAE); /* PAuse Enable */
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ncfgr |= MACB_BIT(DRFCS); /* Discard Rx FCS */
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ncfgr |= macb_dbw(macb);
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macb_writel(macb, NCFGR, ncfgr);
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macb_init(macb);
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@ -491,6 +656,9 @@ static int macb_probe(struct device_d *dev)
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mdiobus_register(&macb->miibus);
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eth_register(edev);
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dev_info(dev, "Cadence %s at 0x%p\n",
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macb_is_gem(macb) ? "GEM" : "MACB", macb->regs);
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return 0;
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}
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@ -67,6 +67,24 @@
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#define MACB_TPQ 0x00bc
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#define MACB_USRIO 0x00c0
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#define MACB_WOL 0x00c4
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#define MACB_MID 0x00fc
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/* GEM register offsets. */
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#define GEM_NCFGR 0x0004
|
||||
#define GEM_USRIO 0x000c
|
||||
#define GEM_DMACFG 0x0010
|
||||
#define GEM_HRB 0x0080
|
||||
#define GEM_HRT 0x0084
|
||||
#define GEM_SA1B 0x0088
|
||||
#define GEM_SA1T 0x008C
|
||||
#define GEM_OTX 0x0100
|
||||
#define GEM_DCFG1 0x0280
|
||||
#define GEM_DCFG2 0x0284
|
||||
#define GEM_DCFG3 0x0288
|
||||
#define GEM_DCFG4 0x028c
|
||||
#define GEM_DCFG5 0x0290
|
||||
#define GEM_DCFG6 0x0294
|
||||
#define GEM_DCFG7 0x0298
|
||||
|
||||
/* Bitfields in NCR */
|
||||
#define MACB_LB_OFFSET 0
|
||||
|
|
@ -134,6 +152,34 @@
|
|||
#define MACB_IRXFCS_OFFSET 19
|
||||
#define MACB_IRXFCS_SIZE 1
|
||||
|
||||
/* GEM specific NCFGR bitfields. */
|
||||
#define GEM_GBE_OFFSET 10
|
||||
#define GEM_GBE_SIZE 1
|
||||
#define GEM_CLK_OFFSET 18
|
||||
#define GEM_CLK_SIZE 3
|
||||
#define GEM_DBW_OFFSET 21
|
||||
#define GEM_DBW_SIZE 2
|
||||
|
||||
/* Constants for data bus width. */
|
||||
#define GEM_DBW32 0
|
||||
#define GEM_DBW64 1
|
||||
#define GEM_DBW128 2
|
||||
|
||||
/* Bitfields in DMACFG. */
|
||||
#define GEM_FBLDO_OFFSET 0
|
||||
#define GEM_FBLDO_SIZE 5
|
||||
#define GEM_RXBMS_OFFSET 8
|
||||
#define GEM_RXBMS_SIZE 2
|
||||
#define GEM_TXPBMS_OFFSET 10
|
||||
#define GEM_TXPBMS_SIZE 1
|
||||
#define GEM_TXCOEN_OFFSET 11
|
||||
#define GEM_TXCOEN_SIZE 1
|
||||
#define GEM_RXBS_OFFSET 16
|
||||
#define GEM_RXBS_SIZE 8
|
||||
#define GEM_DDRP_OFFSET 24
|
||||
#define GEM_DDRP_SIZE 1
|
||||
|
||||
|
||||
/* Bitfields in NSR */
|
||||
#define MACB_NSR_LINK_OFFSET 0
|
||||
#define MACB_NSR_LINK_SIZE 1
|
||||
|
|
@ -208,7 +254,7 @@
|
|||
#define MACB_SOF_OFFSET 30
|
||||
#define MACB_SOF_SIZE 2
|
||||
|
||||
/* Bitfields in USRIO */
|
||||
/* Bitfields in USRIO (AVR32) */
|
||||
#define MACB_MII_OFFSET 0
|
||||
#define MACB_MII_SIZE 1
|
||||
#define MACB_EAM_OFFSET 1
|
||||
|
|
@ -221,6 +267,8 @@
|
|||
/* Bitfields in USRIO (AT91) */
|
||||
#define MACB_RMII_OFFSET 0
|
||||
#define MACB_RMII_SIZE 1
|
||||
#define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */
|
||||
#define GEM_RGMII_SIZE 1
|
||||
#define MACB_CLKEN_OFFSET 1
|
||||
#define MACB_CLKEN_SIZE 1
|
||||
|
||||
|
|
@ -236,12 +284,30 @@
|
|||
#define MACB_WOL_MTI_OFFSET 19
|
||||
#define MACB_WOL_MTI_SIZE 1
|
||||
|
||||
/* Bitfields in MID */
|
||||
#define MACB_IDNUM_OFFSET 16
|
||||
#define MACB_IDNUM_SIZE 16
|
||||
#define MACB_REV_OFFSET 0
|
||||
#define MACB_REV_SIZE 16
|
||||
|
||||
/* Bitfields in DCFG1. */
|
||||
#define GEM_DBWDEF_OFFSET 25
|
||||
#define GEM_DBWDEF_SIZE 3
|
||||
|
||||
/* Constants for CLK */
|
||||
#define MACB_CLK_DIV8 0
|
||||
#define MACB_CLK_DIV16 1
|
||||
#define MACB_CLK_DIV32 2
|
||||
#define MACB_CLK_DIV64 3
|
||||
|
||||
/* GEM specific constants for CLK. */
|
||||
#define GEM_CLK_DIV8 0
|
||||
#define GEM_CLK_DIV16 1
|
||||
#define GEM_CLK_DIV32 2
|
||||
#define GEM_CLK_DIV48 3
|
||||
#define GEM_CLK_DIV64 4
|
||||
#define GEM_CLK_DIV96 5
|
||||
|
||||
/* Constants for MAN register */
|
||||
#define MACB_MAN_SOF 1
|
||||
#define MACB_MAN_WRITE 1
|
||||
|
|
@ -262,11 +328,52 @@
|
|||
<< MACB_##name##_OFFSET)) \
|
||||
| MACB_BF(name,value))
|
||||
|
||||
#define GEM_BIT(name) \
|
||||
(1 << GEM_##name##_OFFSET)
|
||||
#define GEM_BF(name, value) \
|
||||
(((value) & ((1 << GEM_##name##_SIZE) - 1)) \
|
||||
<< GEM_##name##_OFFSET)
|
||||
#define GEM_BFEXT(name, value)\
|
||||
(((value) >> GEM_##name##_OFFSET) \
|
||||
& ((1 << GEM_##name##_SIZE) - 1))
|
||||
#define GEM_BFINS(name, value, old) \
|
||||
(((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
|
||||
<< GEM_##name##_OFFSET)) \
|
||||
| GEM_BF(name, value))
|
||||
|
||||
/* Register access macros */
|
||||
#define macb_readl(port,reg) \
|
||||
__raw_readl((port)->regs + MACB_##reg)
|
||||
#define macb_writel(port,reg,value) \
|
||||
__raw_writel((value), (port)->regs + MACB_##reg)
|
||||
#define gem_readl(port, reg) \
|
||||
__raw_readl((port)->regs + GEM_##reg)
|
||||
#define gem_writel(port, reg, value) \
|
||||
__raw_writel((value), (port)->regs + GEM_##reg)
|
||||
|
||||
/*
|
||||
* Conditional GEM/MACB macros. These perform the operation to the correct
|
||||
* register dependent on whether the device is a GEM or a MACB. For registers
|
||||
* and bitfields that are common across both devices, use macb_{read,write}l
|
||||
* to avoid the cost of the conditional.
|
||||
*/
|
||||
#define macb_or_gem_writel(__bp, __reg, __value) \
|
||||
({ \
|
||||
if (macb_is_gem((__bp))) \
|
||||
gem_writel((__bp), __reg, __value); \
|
||||
else \
|
||||
macb_writel((__bp), __reg, __value); \
|
||||
})
|
||||
|
||||
#define macb_or_gem_readl(__bp, __reg) \
|
||||
({ \
|
||||
u32 __v; \
|
||||
if (macb_is_gem((__bp))) \
|
||||
__v = gem_readl((__bp), __reg); \
|
||||
else \
|
||||
__v = macb_readl((__bp), __reg); \
|
||||
__v; \
|
||||
})
|
||||
|
||||
/**
|
||||
* struct macb_dma_desc - Hardware DMA descriptor
|
||||
|
|
|
|||
Loading…
Reference in New Issue