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at91: drop AT91_BASE_PIOx for soc specific one for none boot code 

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Jean-Christophe PLAGNIOL-VILLARD 2012-12-28 20:16:14 +01:00 committed by Sascha Hauer
parent a0f94be44e
commit 9ce0055e9c
7 changed files with 28 additions and 28 deletions
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8
arch/arm/mach-at91/at91rm9200.c
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@ -232,10 +232,10 @@ static void __init at91rm9200_initialize(void)
at91rm9200_register_clocks();
/* Register GPIO subsystem */
at91_add_rm9200_gpio(0, AT91_BASE_PIOA);
at91_add_rm9200_gpio(1, AT91_BASE_PIOB);
at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
at91_add_rm9200_gpio(3, AT91_BASE_PIOD);
at91_add_rm9200_gpio(0, AT91RM9200_BASE_PIOA);
at91_add_rm9200_gpio(1, AT91RM9200_BASE_PIOB);
at91_add_rm9200_gpio(2, AT91RM9200_BASE_PIOC);
at91_add_rm9200_gpio(3, AT91RM9200_BASE_PIOD);
}
AT91_SOC_START(rm9200)

6
arch/arm/mach-at91/at91sam9260.c
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@ -231,9 +231,9 @@ static void at91sam9260_initialize(void)
at91sam9260_register_clocks();
/* Register GPIO subsystem */
at91_add_rm9200_gpio(0, AT91_BASE_PIOA);
at91_add_rm9200_gpio(1, AT91_BASE_PIOB);
at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
at91_add_rm9200_gpio(0, AT91SAM9260_BASE_PIOA);
at91_add_rm9200_gpio(1, AT91SAM9260_BASE_PIOB);
at91_add_rm9200_gpio(2, AT91SAM9260_BASE_PIOC);
at91_add_pit(AT91SAM9260_BASE_PIT);
at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9260_BASE_SMC, 0x200);

6
arch/arm/mach-at91/at91sam9261.c
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@ -223,9 +223,9 @@ static void at91sam9261_initialize(void)
at91sam9261_register_clocks();
/* Register GPIO subsystem */
at91_add_rm9200_gpio(0, AT91_BASE_PIOA);
at91_add_rm9200_gpio(1, AT91_BASE_PIOB);
at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
at91_add_rm9200_gpio(0, AT91SAM9261_BASE_PIOA);
at91_add_rm9200_gpio(1, AT91SAM9261_BASE_PIOB);
at91_add_rm9200_gpio(2, AT91SAM9261_BASE_PIOC);
at91_add_pit(AT91SAM9261_BASE_PIT);
at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9261_BASE_SMC, 0x200);

10
arch/arm/mach-at91/at91sam9263.c
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@ -240,11 +240,11 @@ static void at91sam9263_initialize(void)
at91sam9263_register_clocks();
/* Register GPIO subsystem */
at91_add_rm9200_gpio(0, AT91_BASE_PIOA);
at91_add_rm9200_gpio(1, AT91_BASE_PIOB);
at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
at91_add_rm9200_gpio(3, AT91_BASE_PIOD);
at91_add_rm9200_gpio(4, AT91_BASE_PIOE);
at91_add_rm9200_gpio(0, AT91SAM9263_BASE_PIOA);
at91_add_rm9200_gpio(1, AT91SAM9263_BASE_PIOB);
at91_add_rm9200_gpio(2, AT91SAM9263_BASE_PIOC);
at91_add_rm9200_gpio(3, AT91SAM9263_BASE_PIOD);
at91_add_rm9200_gpio(4, AT91SAM9263_BASE_PIOE);
at91_add_pit(AT91SAM9263_BASE_PIT);
at91_add_sam9_smc(0, AT91SAM9263_BASE_SMC0, 0x200);

10
arch/arm/mach-at91/at91sam9g45.c
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@ -252,11 +252,11 @@ static void at91sam9g45_initialize(void)
at91sam9g45_register_clocks();
/* Register GPIO subsystem */
at91_add_rm9200_gpio(0, AT91_BASE_PIOA);
at91_add_rm9200_gpio(1, AT91_BASE_PIOB);
at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
at91_add_rm9200_gpio(3, AT91_BASE_PIOD);
at91_add_rm9200_gpio(4, AT91_BASE_PIOE);
at91_add_rm9200_gpio(0, AT91SAM9G45_BASE_PIOA);
at91_add_rm9200_gpio(1, AT91SAM9G45_BASE_PIOB);
at91_add_rm9200_gpio(2, AT91SAM9G45_BASE_PIOC);
at91_add_rm9200_gpio(3, AT91SAM9G45_BASE_PIOD);
at91_add_rm9200_gpio(4, AT91SAM9G45_BASE_PIOE);
at91_add_pit(AT91SAM9G45_BASE_PIT);
at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9G45_BASE_SMC, 0x200);

8
arch/arm/mach-at91/at91sam9n12.c
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@ -213,10 +213,10 @@ static void at91sam9n12_initialize(void)
at91sam9n12_register_clocks();
/* Register GPIO subsystem */
at91_add_sam9x5_gpio(0, AT91_BASE_PIOA);
at91_add_sam9x5_gpio(1, AT91_BASE_PIOB);
at91_add_sam9x5_gpio(2, AT91_BASE_PIOC);
at91_add_sam9x5_gpio(3, AT91_BASE_PIOD);
at91_add_sam9x5_gpio(0, AT91SAM9N12_BASE_PIOA);
at91_add_sam9x5_gpio(1, AT91SAM9N12_BASE_PIOB);
at91_add_sam9x5_gpio(2, AT91SAM9N12_BASE_PIOC);
at91_add_sam9x5_gpio(3, AT91SAM9N12_BASE_PIOD);
at91_add_pit(AT91SAM9N12_BASE_PIT);
at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9N12_BASE_SMC, 0x200);

8
arch/arm/mach-at91/at91sam9x5.c
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@ -298,10 +298,10 @@ static void at91sam9x5_initialize(void)
at91sam9x5_register_clocks();
/* Register GPIO subsystem */
at91_add_sam9x5_gpio(0, AT91_BASE_PIOA);
at91_add_sam9x5_gpio(1, AT91_BASE_PIOB);
at91_add_sam9x5_gpio(2, AT91_BASE_PIOC);
at91_add_sam9x5_gpio(3, AT91_BASE_PIOD);
at91_add_sam9x5_gpio(0, AT91SAM9X5_BASE_PIOA);
at91_add_sam9x5_gpio(1, AT91SAM9X5_BASE_PIOB);
at91_add_sam9x5_gpio(2, AT91SAM9X5_BASE_PIOC);
at91_add_sam9x5_gpio(3, AT91SAM9X5_BASE_PIOD);
at91_add_pit(AT91SAM9X5_BASE_PIT);
at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9X5_BASE_SMC, 0x200);