ARM: add support for the i.MX53
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Marc Kleine-Budde
Sascha Hauer
parent
672b286a7f
commit
9eaaf1b1ca
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@ -50,8 +50,8 @@ choice
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used to setup SDRAM. The internal ROM code then initializes SDRAM
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using the register/value table, loads the whole barebox image to
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SDRAM and starts it. The internal boot mode is available on newer
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i.MX processors (i.MX25, i.MX35 and i.MX51). and supports booting
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from NOR, NAND, MMC/SD and serial ROMs.
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i.MX processors (i.MX25, i.MX35, i.MX51 and i.MX53). and supports
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booting from NOR, NAND, MMC/SD and serial ROMs.
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The external boot mode only supports booting from NAND and NOR. With
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NOR flash the image is just started in NOR flash. With NAND flash
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the NAND controller loads the first 2kbyte from NAND into the NAND
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@ -62,7 +62,7 @@ choice
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config ARCH_IMX_INTERNAL_BOOT
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bool "support internal boot mode"
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depends on ARCH_IMX25 || ARCH_IMX35 || ARCH_IMX51
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depends on ARCH_IMX25 || ARCH_IMX35 || ARCH_IMX51 || ARCH_IMX53
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config ARCH_IMX_EXTERNAL_BOOT
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bool "support external boot mode"
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@ -154,6 +154,11 @@ config ARCH_IMX51
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select CPU_V7
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select ARCH_HAS_FEC_IMX
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config ARCH_IMX53
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bool "i.MX53"
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select CPU_V7
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select ARCH_HAS_FEC_IMX
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endchoice
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# ----------------------------------------------------------
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@ -397,6 +402,20 @@ endchoice
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endif
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# ----------------------------------------------------------
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if ARCH_IMX53
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choice
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prompt "i.MX53 Board Type"
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endchoice
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endif
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# ----------------------------------------------------------
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menu "Board specific settings "
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if MACH_PCM043
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@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_IMX27) += speed-imx27.o imx27.o iomux-v1.o
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obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o imx31.o iomux-v2.o
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obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o imx35.o iomux-v3.o
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obj-$(CONFIG_ARCH_IMX51) += speed-imx51.o imx51.o iomux-v3.o
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obj-$(CONFIG_ARCH_IMX53) += speed-imx53.o imx53.o iomux-v3.o
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obj-$(CONFIG_IMX_CLKO) += clko.o
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obj-$(CONFIG_IMX_IIM) += iim.o
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obj-$(CONFIG_NAND_IMX) += nand.o
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@ -0,0 +1,45 @@
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <init.h>
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#include <common.h>
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#include <asm/io.h>
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#include <sizes.h>
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#include <mach/imx53-regs.h>
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#include "gpio.h"
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void *imx_gpio_base[] = {
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(void *)MX53_GPIO1_BASE_ADDR,
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(void *)MX53_GPIO2_BASE_ADDR,
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(void *)MX53_GPIO3_BASE_ADDR,
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(void *)MX53_GPIO4_BASE_ADDR,
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(void *)MX53_GPIO5_BASE_ADDR,
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(void *)MX53_GPIO6_BASE_ADDR,
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(void *)MX53_GPIO7_BASE_ADDR,
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};
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int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32;
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static int imx53_init(void)
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{
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add_generic_device("imx_iim", 0, NULL, MX53_IIM_BASE_ADDR, SZ_4K,
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IORESOURCE_MEM, NULL);
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return 0;
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}
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coredevice_initcall(imx53_init);
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@ -586,6 +586,10 @@
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/* Assuming 24MHz input clock with doubler ON */
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/* MFI PDF */
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#define MX5_PLL_DP_OP_1000 ((10 << 4) + ((1 - 1) << 0))
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#define MX5_PLL_DP_MFD_1000 (12 - 1)
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#define MX5_PLL_DP_MFN_1000 5
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#define MX5_PLL_DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
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#define MX5_PLL_DP_MFD_850 (48 - 1)
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#define MX5_PLL_DP_MFN_850 41
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@ -0,0 +1,58 @@
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#include <mach/devices.h>
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static inline struct device_d *imx53_add_spi0(struct spi_imx_master *pdata)
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{
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return imx_add_spi((void *)MX53_ECSPI1_BASE_ADDR, 0, pdata);
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}
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static inline struct device_d *imx53_add_spi1(struct spi_imx_master *pdata)
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{
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return imx_add_spi((void *)MX53_ECSPI2_BASE_ADDR, 1, pdata);
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}
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static inline struct device_d *imx53_add_i2c0(struct i2c_platform_data *pdata)
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{
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return imx_add_i2c((void *)MX53_I2C1_BASE_ADDR, 0, pdata);
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}
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static inline struct device_d *imx53_add_i2c1(struct i2c_platform_data *pdata)
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{
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return imx_add_i2c((void *)MX53_I2C2_BASE_ADDR, 1, pdata);
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}
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static inline struct device_d *imx53_add_uart0(void)
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{
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return imx_add_uart((void *)MX53_UART1_BASE_ADDR, 0);
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}
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static inline struct device_d *imx53_add_uart1(void)
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{
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return imx_add_uart((void *)MX53_UART2_BASE_ADDR, 1);
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}
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static inline struct device_d *imx53_add_fec(struct fec_platform_data *pdata)
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{
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return imx_add_fec((void *)MX53_FEC_BASE_ADDR, pdata);
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}
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static inline struct device_d *imx53_add_mmc0(void *pdata)
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{
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return imx_add_esdhc((void *)MX53_ESDHC1_BASE_ADDR, 0, pdata);
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}
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static inline struct device_d *imx53_add_mmc1(void *pdata)
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{
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return imx_add_esdhc((void *)MX53_ESDHC2_BASE_ADDR, 0, pdata);
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}
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static inline struct device_d *imx53_add_mmc2(void *pdata)
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{
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return imx_add_esdhc((void *)MX53_ESDHC3_BASE_ADDR, 0, pdata);
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}
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static inline struct device_d *imx53_add_nand(struct imx_nand_platform_data *pdata)
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{
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return imx_add_nand((void *)MX53_NFC_AXI_BASE_ADDR, pdata);
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}
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@ -71,6 +71,11 @@ static inline int imx51_iim_register_fec_ethaddr(void)
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return 0;
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}
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static inline int imx53_iim_register_fec_ethaddr(void)
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{
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return imx51_iim_register_fec_ethaddr();
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}
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static inline int imx25_iim_register_fec_ethaddr(void)
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{
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int ret;
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@ -49,6 +49,11 @@ struct imx_dcd_entry {
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unsigned long val;
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};
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struct imx_dcd_v2_entry {
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__be32 addr;
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__be32 val;
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};
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#define DCD_BARKER 0xb17219e9
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struct imx_rsa_public_key {
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@ -73,4 +78,51 @@ struct imx_flash_header {
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unsigned long dcd_block_len;
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};
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#define IVT_HEADER_TAG 0xd1
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#define IVT_VERSION 0x40
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#define DCD_HEADER_TAG 0xd2
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#define DCD_VERSION 0x40
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#define DCD_COMMAND_WRITE_TAG 0xcc
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#define DCD_COMMAND_WRITE_PARAM 0x04
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struct imx_ivt_header {
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uint8_t tag;
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__be16 length;
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uint8_t version;
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} __attribute__((packed));
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struct imx_dcd_command {
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uint8_t tag;
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__be16 length;
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uint8_t param;
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} __attribute__((packed));
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struct imx_dcd {
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struct imx_ivt_header header;
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struct imx_dcd_command command;
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};
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struct imx_boot_data {
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uint32_t start;
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uint32_t size;
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uint32_t plugin;
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};
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struct imx_flash_header_v2 {
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struct imx_ivt_header header;
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uint32_t entry;
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uint32_t reserved1;
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uint32_t dcd_ptr;
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uint32_t boot_data_ptr;
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uint32_t self;
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uint32_t csf;
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uint32_t reserved2;
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struct imx_boot_data boot_data;
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struct imx_dcd dcd;
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};
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#endif /* __MACH_FLASH_HEADER_H */
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@ -52,7 +52,9 @@
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#elif defined CONFIG_ARCH_IMX25
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# include <mach/imx25-regs.h>
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#elif defined CONFIG_ARCH_IMX51
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#include <mach/imx51-regs.h>
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# include <mach/imx51-regs.h>
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#elif defined CONFIG_ARCH_IMX53
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# include <mach/imx53-regs.h>
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#else
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# error "unknown i.MX soc type"
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#endif
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@ -0,0 +1,139 @@
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#ifndef __MACH_IMX53_REGS_H
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#define __MACH_IMX53_REGS_H
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#define IMX_TIM1_BASE 0X53FA0000
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#define IMX_WDT_BASE 0X53F98000
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#define IMX_IOMUXC_BASE 0X53FA8000
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#define GPT_TCTL 0x00
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#define GPT_TPRER 0x04
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#define GPT_TCMP 0x10
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#define GPT_TCR 0x1c
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#define GPT_TCN 0x24
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#define GPT_TSTAT 0x08
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/* Part 2: Bitfields */
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#define TCTL_SWR (1<<15) /* Software reset */
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#define TCTL_FRR (1<<9) /* Freerun / restart */
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#define TCTL_CAP (3<<6) /* Capture Edge */
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#define TCTL_OM (1<<5) /* output mode */
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#define TCTL_IRQEN (1<<4) /* interrupt enable */
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#define TCTL_CLKSOURCE (6) /* Clock source bit position */
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#define TCTL_TEN (1) /* Timer enable */
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#define TPRER_PRES (0xff) /* Prescale */
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#define TSTAT_CAPT (1<<1) /* Capture event */
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#define TSTAT_COMP (1) /* Compare event */
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#define MX53_IROM_BASE_ADDR 0x0
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/*
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* SPBA global module enabled #0
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*/
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#define MX53_SPBA0_BASE_ADDR 0x50000000
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#define MX53_SPBA0_SIZE SZ_1M
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#define MX53_ESDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000)
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#define MX53_ESDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000)
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#define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000)
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#define MX53_ECSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000)
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#define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000)
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#define MX53_ESDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000)
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#define MX53_ESDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000)
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#define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000)
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#define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000)
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#define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000)
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#define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000)
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#define MX53_HSI2C_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00038000)
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#define MX53_SPBA_CTRL_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0003C000)
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/*
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* AIPS 1
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*/
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#define MX53_AIPS1_BASE_ADDR 0x53F00000
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#define MX53_AIPS1_SIZE SZ_1M
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#define MX53_OTG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00080000)
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#define MX53_GPIO1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00084000)
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#define MX53_GPIO2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00088000)
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#define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000)
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#define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000)
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#define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000)
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#define MX53_WDOG1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000)
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#define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000)
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#define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000)
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#define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000)
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#define MX53_IOMUXC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A8000)
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#define MX53_EPIT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000AC000)
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#define MX53_EPIT2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B0000)
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#define MX53_PWM1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B4000)
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#define MX53_PWM2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B8000)
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#define MX53_UART1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000BC000)
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#define MX53_UART2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000C0000)
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#define MX53_SRC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D0000)
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#define MX53_CCM_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D4000)
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#define MX53_GPC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D8000)
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#define MX53_GPIO5_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000DC000)
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#define MX53_GPIO6_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E0000)
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#define MX53_GPIO7_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E4000)
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#define MX53_ATA_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E8000)
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#define MX53_I2C3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000EC000)
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#define MX53_UART4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000F0000)
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/*
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* AIPS 2
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*/
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#define MX53_AIPS2_BASE_ADDR 0x63F00000
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#define MX53_AIPS2_SIZE SZ_1M
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#define MX53_PLL1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00080000)
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#define MX53_PLL2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00084000)
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#define MX53_PLL3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00088000)
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#define MX53_PLL4_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0008C000)
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#define MX53_UART5_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00090000)
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#define MX53_AHBMAX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00094000)
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#define MX53_IIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00098000)
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#define MX53_CSU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0009C000)
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#define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000)
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#define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000)
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#define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000)
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#define MX53_ECSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000)
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#define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000)
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#define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000)
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#define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000)
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#define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000)
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#define MX53_CSPI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000)
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#define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000)
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#define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000)
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#define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000)
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#define MX53_AUDMUX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D0000)
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#define MX53_RTC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D4000)
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#define MX53_M4IF_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D8000)
|
||||
#define MX53_ESDCTL_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D9000)
|
||||
#define MX53_WEIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DA000)
|
||||
#define MX53_NFC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DB000)
|
||||
#define MX53_EMI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DBF00)
|
||||
#define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000)
|
||||
#define MX53_MLB_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E4000)
|
||||
#define MX53_SSI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E8000)
|
||||
#define MX53_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000)
|
||||
#define MX53_TVE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F0000)
|
||||
#define MX53_VPU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F4000)
|
||||
#define MX53_SAHARA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F8000)
|
||||
#define MX53_PTP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000FC000)
|
||||
|
||||
#define MX53_NFC_AXI_BASE_ADDR 0xF7FF0000
|
||||
|
||||
/*
|
||||
* Memory regions and CS
|
||||
*/
|
||||
#define MX53_CSD0_BASE_ADDR 0x70000000
|
||||
#define MX53_CSD1_BASE_ADDR 0xB0000000
|
||||
#define MX53_CS0_BASE_ADDR 0xF0000000
|
||||
#define MX53_CS1_32MB_BASE_ADDR 0xF2000000
|
||||
#define MX53_CS1_64MB_BASE_ADDR 0xF4000000
|
||||
#define MX53_CS2_64MB_BASE_ADDR 0xF4000000
|
||||
#define MX53_CS2_96MB_BASE_ADDR 0xF6000000
|
||||
#define MX53_CS3_BASE_ADDR 0xF6000000
|
||||
|
||||
#endif /* __MACH_IMX53_REGS_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,204 @@
|
|||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm-generic/div64.h>
|
||||
#include <mach/imx-regs.h>
|
||||
#include "mach/clock-imx51_53.h"
|
||||
|
||||
static u32 ccm_readl(u32 ofs)
|
||||
{
|
||||
return readl(MX53_CCM_BASE_ADDR + ofs);
|
||||
}
|
||||
|
||||
static unsigned long ckil_get_rate(void)
|
||||
{
|
||||
return 32768;
|
||||
}
|
||||
|
||||
static unsigned long osc_get_rate(void)
|
||||
{
|
||||
return 24000000;
|
||||
}
|
||||
|
||||
static unsigned long fpm_get_rate(void)
|
||||
{
|
||||
return ckil_get_rate() * 512;
|
||||
}
|
||||
|
||||
static unsigned long pll_get_rate(void __iomem *pllbase)
|
||||
{
|
||||
long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
|
||||
unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
|
||||
u64 temp;
|
||||
unsigned long parent_rate;
|
||||
|
||||
dp_ctl = readl(pllbase + MX5_PLL_DP_CTL);
|
||||
|
||||
if ((dp_ctl & MX5_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0)
|
||||
parent_rate = fpm_get_rate();
|
||||
else
|
||||
parent_rate = osc_get_rate();
|
||||
|
||||
pll_hfsm = dp_ctl & MX5_PLL_DP_CTL_HFSM;
|
||||
dbl = dp_ctl & MX5_PLL_DP_CTL_DPDCK0_2_EN;
|
||||
|
||||
if (pll_hfsm == 0) {
|
||||
dp_op = readl(pllbase + MX5_PLL_DP_OP);
|
||||
dp_mfd = readl(pllbase + MX5_PLL_DP_MFD);
|
||||
dp_mfn = readl(pllbase + MX5_PLL_DP_MFN);
|
||||
} else {
|
||||
dp_op = readl(pllbase + MX5_PLL_DP_HFS_OP);
|
||||
dp_mfd = readl(pllbase + MX5_PLL_DP_HFS_MFD);
|
||||
dp_mfn = readl(pllbase + MX5_PLL_DP_HFS_MFN);
|
||||
}
|
||||
pdf = dp_op & MX5_PLL_DP_OP_PDF_MASK;
|
||||
mfi = (dp_op & MX5_PLL_DP_OP_MFI_MASK) >> MX5_PLL_DP_OP_MFI_OFFSET;
|
||||
mfi = (mfi <= 5) ? 5 : mfi;
|
||||
mfd = dp_mfd & MX5_PLL_DP_MFD_MASK;
|
||||
mfn = mfn_abs = dp_mfn & MX5_PLL_DP_MFN_MASK;
|
||||
/* Sign extend to 32-bits */
|
||||
if (mfn >= 0x04000000) {
|
||||
mfn |= 0xFC000000;
|
||||
mfn_abs = -mfn;
|
||||
}
|
||||
|
||||
ref_clk = 2 * parent_rate;
|
||||
if (dbl != 0)
|
||||
ref_clk *= 2;
|
||||
|
||||
ref_clk /= (pdf + 1);
|
||||
temp = (u64)ref_clk * mfn_abs;
|
||||
do_div(temp, mfd + 1);
|
||||
if (mfn < 0)
|
||||
temp = -temp;
|
||||
temp = (ref_clk * mfi) + temp;
|
||||
|
||||
return temp;
|
||||
}
|
||||
|
||||
static unsigned long pll1_main_get_rate(void)
|
||||
{
|
||||
return pll_get_rate((void __iomem *)MX53_PLL1_BASE_ADDR);
|
||||
}
|
||||
|
||||
static unsigned long pll2_sw_get_rate(void)
|
||||
{
|
||||
return pll_get_rate((void __iomem *)MX53_PLL2_BASE_ADDR);
|
||||
}
|
||||
|
||||
static unsigned long pll3_sw_get_rate(void)
|
||||
{
|
||||
return pll_get_rate((void __iomem *)MX53_PLL3_BASE_ADDR);
|
||||
}
|
||||
|
||||
static unsigned long pll4_sw_get_rate(void)
|
||||
{
|
||||
return pll_get_rate((void __iomem *)MX53_PLL4_BASE_ADDR);
|
||||
}
|
||||
|
||||
static unsigned long get_rate_select(int select,
|
||||
unsigned long (* get_rate1)(void),
|
||||
unsigned long (* get_rate2)(void),
|
||||
unsigned long (* get_rate3)(void),
|
||||
unsigned long (* get_rate4)(void))
|
||||
{
|
||||
switch (select) {
|
||||
case 0:
|
||||
return get_rate1() ? get_rate1() : 0;
|
||||
case 1:
|
||||
return get_rate2() ? get_rate2() : 0;
|
||||
case 2:
|
||||
return get_rate3 ? get_rate3() : 0;
|
||||
case 3:
|
||||
return get_rate4 ? get_rate4() : 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long imx_get_uartclk(void)
|
||||
{
|
||||
u32 reg, prediv, podf;
|
||||
unsigned long parent_rate;
|
||||
|
||||
reg = ccm_readl(MX5_CCM_CSCMR1);
|
||||
reg &= MX5_CCM_CSCMR1_UART_CLK_SEL_MASK;
|
||||
reg >>= MX5_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
|
||||
|
||||
parent_rate = get_rate_select(reg,
|
||||
pll1_main_get_rate,
|
||||
pll2_sw_get_rate,
|
||||
pll3_sw_get_rate,
|
||||
pll4_sw_get_rate);
|
||||
|
||||
reg = ccm_readl(MX5_CCM_CSCDR1);
|
||||
prediv = ((reg & MX5_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
|
||||
MX5_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
|
||||
podf = ((reg & MX5_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
|
||||
MX5_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
|
||||
|
||||
return parent_rate / (prediv * podf);
|
||||
}
|
||||
|
||||
static unsigned long imx_get_ahbclk(void)
|
||||
{
|
||||
u32 reg, div;
|
||||
|
||||
reg = ccm_readl(MX5_CCM_CBCDR);
|
||||
div = ((reg >> 10) & 0x7) + 1;
|
||||
|
||||
return pll2_sw_get_rate() / div;
|
||||
}
|
||||
|
||||
unsigned long imx_get_ipgclk(void)
|
||||
{
|
||||
u32 reg, div;
|
||||
|
||||
reg = ccm_readl(MX5_CCM_CBCDR);
|
||||
div = ((reg >> 8) & 0x3) + 1;
|
||||
|
||||
return imx_get_ahbclk() / div;
|
||||
}
|
||||
|
||||
unsigned long imx_get_gptclk(void)
|
||||
{
|
||||
return imx_get_ipgclk();
|
||||
}
|
||||
|
||||
unsigned long imx_get_fecclk(void)
|
||||
{
|
||||
return imx_get_ipgclk();
|
||||
}
|
||||
|
||||
unsigned long imx_get_mmcclk(void)
|
||||
{
|
||||
u32 reg, prediv, podf, rate;
|
||||
|
||||
reg = ccm_readl(MX5_CCM_CSCMR1);
|
||||
reg &= MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK;
|
||||
reg >>= MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET;
|
||||
rate = get_rate_select(reg,
|
||||
pll1_main_get_rate,
|
||||
pll2_sw_get_rate,
|
||||
pll3_sw_get_rate,
|
||||
pll4_sw_get_rate);
|
||||
|
||||
reg = ccm_readl(MX5_CCM_CSCDR1);
|
||||
prediv = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) >>
|
||||
MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET) + 1;
|
||||
podf = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) >>
|
||||
MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET) + 1;
|
||||
|
||||
return rate / (prediv * podf);
|
||||
}
|
||||
|
||||
void imx_dump_clocks(void)
|
||||
{
|
||||
printf("pll1: %ld\n", pll1_main_get_rate());
|
||||
printf("pll2: %ld\n", pll2_sw_get_rate());
|
||||
printf("pll3: %ld\n", pll3_sw_get_rate());
|
||||
printf("pll4: %ld\n", pll4_sw_get_rate());
|
||||
printf("uart: %ld\n", imx_get_uartclk());
|
||||
printf("ipg: %ld\n", imx_get_ipgclk());
|
||||
printf("fec: %ld\n", imx_get_fecclk());
|
||||
printf("gpt: %ld\n", imx_get_gptclk());
|
||||
}
|
||||
|
|
@ -55,7 +55,7 @@ config MCI_IMX
|
|||
|
||||
config MCI_IMX_ESDHC
|
||||
bool "i.MX esdhc"
|
||||
depends on ARCH_IMX25 || ARCH_IMX35 || ARCH_IMX51
|
||||
depends on ARCH_IMX25 || ARCH_IMX35 || ARCH_IMX51 || ARCH_IMX53
|
||||
help
|
||||
Enable this entry to add support to read and write SD cards on a
|
||||
Freescale i.MX25/35/51 based system.
|
||||
|
|
|
|||
|
|
@ -161,7 +161,8 @@
|
|||
# define UCR4_VAL UCR4_CTSTL_32
|
||||
#endif
|
||||
#if defined CONFIG_ARCH_IMX31 || defined CONFIG_ARCH_IMX35 || \
|
||||
defined CONFIG_ARCH_IMX25 || defined CONFIG_ARCH_IMX51
|
||||
defined CONFIG_ARCH_IMX25 || defined CONFIG_ARCH_IMX51 || \
|
||||
defined CONFIG_ARCH_IMX53
|
||||
# define UCR1_VAL (0)
|
||||
# define UCR3_VAL (0x700 | UCR3_RXDMUXSEL)
|
||||
# define UCR4_VAL UCR4_CTSTL_32
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ config DRIVER_SPI_IMX_0_0
|
|||
|
||||
config DRIVER_SPI_IMX_2_3
|
||||
bool
|
||||
depends on ARCH_IMX51
|
||||
depends on ARCH_IMX51 || ARCH_IMX53
|
||||
default y
|
||||
|
||||
endmenu
|
||||
|
|
|
|||
|
|
@ -373,7 +373,7 @@ static int imx_spi_probe(struct device_d *dev)
|
|||
version = SPI_IMX_VER_0_0;
|
||||
#endif
|
||||
#ifdef CONFIG_DRIVER_SPI_IMX_2_3
|
||||
if (cpu_is_mx51())
|
||||
if (cpu_is_mx51() || cpu_is_mx53())
|
||||
version = SPI_IMX_VER_2_3;
|
||||
#endif
|
||||
imx->chipselect = spi_imx_devtype_data[version].chipselect;
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
|
||||
#if defined CONFIG_ARCH_IMX25 || defined CONFIG_ARCH_IMX35 || defined CONFIG_ARCH_IMX51 || defined CONFIG_X86
|
||||
#if defined CONFIG_ARCH_IMX25 || defined CONFIG_ARCH_IMX35 || defined CONFIG_ARCH_IMX51 || defined CONFIG_ARCH_IMX53 || defined CONFIG_X86
|
||||
#include <mach/barebox.lds.h>
|
||||
#endif
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue