ARM i.MX6: sabrelite: switch to multi image support
The image will be named after the official name of this board: barebox-freescale-mx6-sabreline.img Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Philipp Zabel
Sascha Hauer
parent
1c8608cf58
commit
9f888766d5
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@ -1,3 +1,3 @@
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obj-y += board.o
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lwl-y += flash_header.o
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obj-y += board.o flash-header-mx6-sabrelite.dcd.o
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extra-y += flash-header-mx6-sabrelite.dcd.S flash-header-mx6-sabrelite.dcd
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lwl-y += lowlevel.o
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@ -0,0 +1,106 @@
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soc imx6
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loadaddr 0x20000000
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dcdofs 0x400
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wm 32 0x020e05a8 0x00000030
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wm 32 0x020e05b0 0x00000030
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wm 32 0x020e0524 0x00000030
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wm 32 0x020e051c 0x00000030
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wm 32 0x020e0518 0x00000030
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wm 32 0x020e050c 0x00000030
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wm 32 0x020e05b8 0x00000030
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wm 32 0x020e05c0 0x00000030
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wm 32 0x020e05ac 0x00020030
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wm 32 0x020e05b4 0x00020030
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wm 32 0x020e0528 0x00020030
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wm 32 0x020e0520 0x00020030
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wm 32 0x020e0514 0x00020030
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wm 32 0x020e0510 0x00020030
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wm 32 0x020e05bc 0x00020030
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wm 32 0x020e05c4 0x00020030
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wm 32 0x020e056c 0x00020030
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wm 32 0x020e0578 0x00020030
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wm 32 0x020e0588 0x00020030
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wm 32 0x020e0594 0x00020030
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wm 32 0x020e057c 0x00020030
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wm 32 0x020e0590 0x00003000
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wm 32 0x020e0598 0x00003000
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wm 32 0x020e058c 0x00000000
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wm 32 0x020e059c 0x00003030
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wm 32 0x020e05a0 0x00003030
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wm 32 0x020e0784 0x00000030
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wm 32 0x020e0788 0x00000030
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wm 32 0x020e0794 0x00000030
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wm 32 0x020e079c 0x00000030
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wm 32 0x020e07a0 0x00000030
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wm 32 0x020e07a4 0x00000030
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wm 32 0x020e07a8 0x00000030
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wm 32 0x020e0748 0x00000030
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wm 32 0x020e074c 0x00000030
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wm 32 0x020e0750 0x00020000
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wm 32 0x020e0758 0x00000000
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wm 32 0x020e0774 0x00020000
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wm 32 0x020e078c 0x00000030
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wm 32 0x020e0798 0x000c0000
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wm 32 0x021b081c 0x33333333
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wm 32 0x021b0820 0x33333333
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wm 32 0x021b0824 0x33333333
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wm 32 0x021b0828 0x33333333
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wm 32 0x021b481c 0x33333333
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wm 32 0x021b4820 0x33333333
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wm 32 0x021b4824 0x33333333
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wm 32 0x021b4828 0x33333333
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wm 32 0x021b0018 0x00081740
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wm 32 0x021b001c 0x00008000
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wm 32 0x021b000c 0x555a7975
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wm 32 0x021b0010 0xff538e64
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wm 32 0x021b0014 0x01ff00db
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wm 32 0x021b002c 0x000026d2
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wm 32 0x021b0030 0x005b0e21
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wm 32 0x021b0008 0x09444040
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wm 32 0x021b0004 0x00025576
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wm 32 0x021b0040 0x00000027
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wm 32 0x021b0000 0x831a0000
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wm 32 0x021b001c 0x04088032
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wm 32 0x021b001c 0x0408803a
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wm 32 0x021b001c 0x00008033
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wm 32 0x021b001c 0x0000803b
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wm 32 0x021b001c 0x00428031
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wm 32 0x021b001c 0x00428039
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wm 32 0x021b001c 0x09408030
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wm 32 0x021b001c 0x09408038
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wm 32 0x021b001c 0x04008040
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wm 32 0x021b001c 0x04008048
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wm 32 0x021b0800 0xa1380003
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wm 32 0x021b4800 0xa1380003
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wm 32 0x021b0020 0x00005800
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wm 32 0x021b0818 0x00022227
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wm 32 0x021b4818 0x00022227
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wm 32 0x021b083c 0x434b0350
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wm 32 0x021b0840 0x034c0359
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wm 32 0x021b483c 0x434b0350
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wm 32 0x021b4840 0x03650348
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wm 32 0x021b0848 0x4436383b
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wm 32 0x021b4848 0x39393341
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wm 32 0x021b0850 0x35373933
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wm 32 0x021b4850 0x48254A36
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wm 32 0x021b080c 0x001f001f
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wm 32 0x021b0810 0x001f001f
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wm 32 0x021b480c 0x00440044
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wm 32 0x021b4810 0x00440044
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wm 32 0x021b08b8 0x00000800
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wm 32 0x021b48b8 0x00000800
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wm 32 0x021b001c 0x00000000
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wm 32 0x021b0404 0x00011006
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wm 32 0x020c4068 0x00c03f3f
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wm 32 0x020c406c 0x0030fc03
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wm 32 0x020c4070 0x0fffc000
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wm 32 0x020c4074 0x3ff00000
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wm 32 0x020c4078 0x00fff300
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wm 32 0x020c407c 0x0f0000c3
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wm 32 0x020c4080 0x000003ff
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/* enable AXI cache for VDOA/VPU/IPU */
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wm 32 0x020e0010 0xf00000cf
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/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7 */
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wm 32 0x020e0018 0x007f007f
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wm 32 0x020e001c 0x007f007f
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@ -1,178 +0,0 @@
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/*
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* Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <asm/byteorder.h>
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#include <mach/imx-flash-header.h>
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#include <mach/imx6-regs.h>
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#include <asm/barebox-arm-head.h>
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void __naked __flash_header_start go(void)
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{
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barebox_arm_head();
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}
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#define DCD(a, v) { .addr = cpu_to_be32(a), .val = cpu_to_be32(v), }
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struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5a8, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5b0, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x524, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x51c, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x518, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x50c, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5b8, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5c0, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5ac, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5b4, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x528, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x520, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x514, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x510, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5bc, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5c4, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x56c, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x578, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x588, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x594, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x57c, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x590, 0x00003000),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x598, 0x00003000),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x58c, 0x00000000),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x59c, 0x00003030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5a0, 0x00003030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x784, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x788, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x794, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x79c, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x7a0, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x7a4, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x7a8, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x748, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x74c, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x750, 0x00020000),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x758, 0x00000000),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x774, 0x00020000),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x78c, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x798, 0x000C0000),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x81c, 0x33333333),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x820, 0x33333333),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x824, 0x33333333),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x828, 0x33333333),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x81c, 0x33333333),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x820, 0x33333333),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x824, 0x33333333),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x828, 0x33333333),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x018, 0x00081740),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00008000),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x00c, 0x555A7975),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x010, 0xFF538E64),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x030, 0x005B0E21),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x008, 0x09444040),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x004, 0x00025576),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x040, 0x00000027),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x000, 0x831A0000),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x04088032),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x0408803A),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00008033),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x0000803B),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00428031),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00428039),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x09408030),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x09408038),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x04008040),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x04008048),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x800, 0xA1380003),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x800, 0xA1380003),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x020, 0x00005800),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x818, 0x00022227),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x818, 0x00022227),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x83c, 0x434B0350),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x840, 0x034C0359),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x83c, 0x434B0350),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x840, 0x03650348),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x848, 0x4436383B),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x848, 0x39393341),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x850, 0x35373933),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x850, 0x48254A36),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x810, 0x001F001F),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x80c, 0x00440044),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x810, 0x00440044),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00000000),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x404, 0x00011006),
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DCD(MX6_CCM_BASE_ADDR + 0x068, 0x00c03f3f),
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DCD(MX6_CCM_BASE_ADDR + 0x06c, 0x0030fc03),
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DCD(MX6_CCM_BASE_ADDR + 0x070, 0x0fffc000),
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DCD(MX6_CCM_BASE_ADDR + 0x074, 0x3ff00000),
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DCD(MX6_CCM_BASE_ADDR + 0x078, 0x00fff300),
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DCD(MX6_CCM_BASE_ADDR + 0x07c, 0x0f0000c3),
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DCD(MX6_CCM_BASE_ADDR + 0x080, 0x000003ff),
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/* enable AXI cache for VDOA/VPU/IPU */
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DCD(MX6_IOMUXC_BASE_ADDR + 0x010, 0xf00000cf),
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/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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DCD(MX6_IOMUXC_BASE_ADDR + 0x018, 0x007f007f),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x01c, 0x007f007f),
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};
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#define APP_DEST CONFIG_TEXT_BASE
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struct imx_flash_header_v2 __flash_header_section flash_header = {
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.header.tag = IVT_HEADER_TAG,
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.header.length = cpu_to_be16(32),
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.header.version = IVT_VERSION,
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.entry = (u32)_stext,
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.dcd_ptr = APP_DEST + FLASH_HEADER_OFFSET + offsetof(struct imx_flash_header_v2, dcd),
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.boot_data_ptr = APP_DEST + FLASH_HEADER_OFFSET + offsetof(struct imx_flash_header_v2, boot_data),
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.self = APP_DEST + FLASH_HEADER_OFFSET,
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.boot_data.start = APP_DEST,
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.boot_data.size = barebox_image_size,
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.dcd.header.tag = DCD_HEADER_TAG,
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.dcd.header.length = cpu_to_be16(sizeof(struct imx_dcd) + sizeof(dcd_entry)),
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.dcd.header.version = DCD_VERSION,
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.dcd.command.tag = DCD_COMMAND_WRITE_TAG,
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.dcd.command.length = cpu_to_be16(sizeof(struct imx_dcd_command) + sizeof(dcd_entry)),
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.dcd.command.param = DCD_COMMAND_WRITE_PARAM,
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};
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@ -3,8 +3,17 @@
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#include <asm/barebox-arm-head.h>
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#include <asm/barebox-arm.h>
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void __naked barebox_arm_reset_vector(void)
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extern char __dtb_imx6q_sabrelite_start[];
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ENTRY_FUNCTION(start_imx6_sabrelite)(void)
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{
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uint32_t fdt;
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__barebox_arm_head();
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arm_cpu_lowlevel_init();
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barebox_arm_entry(0x10000000, SZ_1G, 0);
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fdt = (uint32_t)__dtb_imx6q_sabrelite_start - get_runtime_offset();
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barebox_arm_entry(0x10000000, SZ_1G, fdt);
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}
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@ -1,5 +1,3 @@
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CONFIG_BUILTIN_DTB=y
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CONFIG_BUILTIN_DTB_NAME="imx6q-sabrelite"
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CONFIG_ARCH_IMX=y
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CONFIG_IMX_MULTI_BOARDS=y
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CONFIG_MACH_SABRELITE=y
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@ -33,6 +33,7 @@ pbl-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o
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pbl-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o
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pbl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o
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pbl-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o
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pbl-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o
|
||||
|
||||
.SECONDARY: $(obj)/$(BUILTIN_DTB).dtb.S
|
||||
.SECONDARY: $(patsubst %,$(obj)/%.S,$(dtb-y))
|
||||
|
|
|
|||
|
|
@ -223,6 +223,7 @@ config MACH_SABRELITE
|
|||
bool "Freescale i.MX6 Sabre Lite"
|
||||
select ARCH_IMX6
|
||||
select HAVE_DEFAULT_ENVIRONMENT_NEW
|
||||
select HAVE_PBL_MULTI_IMAGES
|
||||
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -66,3 +66,8 @@ pblx-$(CONFIG_MACH_DFI_FS700_M60) += start_imx6q_dfi_fs700_m60_6q
|
|||
CFG_start_imx6q_dfi_fs700_m60_6q.pblx.imximg = $(board)/dfi-fs700-m60/flash-header-fs700-m60-6q.imxcfg
|
||||
FILE_barebox-dfi-fs700-m60-6q.img = start_imx6q_dfi_fs700_m60_6q.pblx.imximg
|
||||
image-$(CONFIG_MACH_DFI_FS700_M60) += barebox-dfi-fs700-m60-6q.img
|
||||
|
||||
pblx-$(CONFIG_MACH_SABRELITE) += start_imx6_sabrelite
|
||||
CFG_start_imx6_sabrelite.pblx.imximg = $(board)/freescale-mx6-sabrelite/flash-header-mx6-sabrelite.imxcfg
|
||||
FILE_barebox-freescale-imx6q-sabrelite.img = start_imx6_sabrelite.pblx.imximg
|
||||
image-$(CONFIG_MACH_SABRELITE) += barebox-freescale-imx6q-sabrelite.img
|
||||
|
|
|
|||
Loading…
Reference in New Issue