ARM: SoCFPGA: Add EBV SoCrates board support
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
e07ddb8b97
commit
9fc58d665e
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@ -75,6 +75,7 @@ obj-$(CONFIG_MACH_SABRELITE) += freescale-mx6-sabrelite/
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obj-$(CONFIG_MACH_SABRESD) += freescale-mx6-sabresd/
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obj-$(CONFIG_MACH_SAMA5D3XEK) += sama5d3xek/
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obj-$(CONFIG_MACH_SCB9328) += scb9328/
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obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += ebv-socrates/
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obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += terasic-sockit/
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obj-$(CONFIG_MACH_TNY_A9260) += tny-a926x/
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obj-$(CONFIG_MACH_TNY_A9263) += tny-a926x/
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@ -0,0 +1,2 @@
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obj-y += lowlevel.o board.o
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pbl-y += lowlevel.o
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@ -0,0 +1,37 @@
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#include <common.h>
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#include <types.h>
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#include <driver.h>
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#include <init.h>
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#include <asm/armlinux.h>
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#include <linux/micrel_phy.h>
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#include <linux/phy.h>
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#include <sizes.h>
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#include <fcntl.h>
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#include <fs.h>
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#include <mach/socfpga-regs.h>
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static int phy_fixup(struct phy_device *dev)
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{
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/* min rx data delay */
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phy_write(dev, 0x0b, 0x8105);
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phy_write(dev, 0x0c, 0x0000);
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/* max rx/tx clock delay, min rx/tx control delay */
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phy_write(dev, 0x0b, 0x8104);
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phy_write(dev, 0x0c, 0xa0d0);
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phy_write(dev, 0x0b, 0x104);
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return 0;
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}
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static int socrates_init(void)
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{
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if (!of_machine_is_compatible("ebv,socrates"))
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return 0;
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if (IS_ENABLED(CONFIG_PHYLIB))
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phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, phy_fixup);
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return 0;
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}
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postcore_initcall(socrates_init);
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@ -0,0 +1 @@
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/* nothing */
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@ -0,0 +1,99 @@
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#include <common.h>
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#include <sizes.h>
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#include <io.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/barebox-arm.h>
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#include <asm/cache.h>
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#include <mach/generic.h>
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#include <debug_ll.h>
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#include "sdram_config.h"
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#include <mach/sdram_config.h>
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#include "pinmux_config.c"
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#include "pll_config.h"
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#include <mach/pll_config.h>
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#include "sequencer_defines.h"
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#include "sequencer_auto.h"
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#include <mach/sequencer.c>
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#include "sequencer_auto_inst_init.c"
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#include "sequencer_auto_ac_init.c"
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static inline void ledon(void)
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{
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u32 val;
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val = readl(0xFF708000);
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val &= ~(1 << 28);
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writel(val, 0xFF708000);
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val = readl(0xFF708004);
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val |= 1 << 28;
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writel(val, 0xFF708004);
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}
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static inline void ledoff(void)
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{
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u32 val;
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val = readl(0xFF708000);
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val |= 1 << 28;
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writel(val, 0xFF708000);
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val = readl(0xFF708004);
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val |= 1 << 28;
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writel(val, 0xFF708004);
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}
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extern char __dtb_socfpga_cyclone5_socrates_start[];
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ENTRY_FUNCTION(start_socfpga_socrates)(void)
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{
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uint32_t fdt;
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__barebox_arm_head();
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arm_cpu_lowlevel_init();
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fdt = (uint32_t)__dtb_socfpga_cyclone5_socrates_start - get_runtime_offset();
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barebox_arm_entry(0x0, SZ_1G, fdt);
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}
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static noinline void socrates_entry(void)
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{
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int ret;
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arm_early_mmu_cache_invalidate();
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relocate_to_current_adr();
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setup_c();
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socfpga_lowlevel_init(&cm_default_cfg,
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sys_mgr_init_table, ARRAY_SIZE(sys_mgr_init_table));
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puts_ll("lowlevel init done\n");
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puts_ll("SDRAM setup...\n");
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socfpga_sdram_mmr_init();
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puts_ll("SDRAM calibration...\n");
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ret = socfpga_sdram_calibration(inst_rom_init, inst_rom_init_size,
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ac_rom_init, ac_rom_init_size);
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if (ret)
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hang();
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puts_ll("done\n");
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barebox_arm_entry(0x0, SZ_1G, 0);
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}
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ENTRY_FUNCTION(start_socfpga_socrates_xload)(void)
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{
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__barebox_arm_head();
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arm_cpu_lowlevel_init();
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arm_setup_stack(0xffff0000 + SZ_64K - SZ_4K - 16);
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socrates_entry();
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}
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@ -0,0 +1,210 @@
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/* pin MUX configuration data */
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static unsigned long sys_mgr_init_table[] = {
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0, /* EMACIO0 */
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2, /* EMACIO1 */
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2, /* EMACIO2 */
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2, /* EMACIO3 */
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2, /* EMACIO4 */
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2, /* EMACIO5 */
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2, /* EMACIO6 */
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2, /* EMACIO7 */
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2, /* EMACIO8 */
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0, /* EMACIO9 */
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2, /* EMACIO10 */
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2, /* EMACIO11 */
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2, /* EMACIO12 */
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2, /* EMACIO13 */
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0, /* EMACIO14 */
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0, /* EMACIO15 */
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0, /* EMACIO16 */
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0, /* EMACIO17 */
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0, /* EMACIO18 */
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0, /* EMACIO19 */
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3, /* FLASHIO0 */
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0, /* FLASHIO1 */
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3, /* FLASHIO2 */
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3, /* FLASHIO3 */
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0, /* FLASHIO4 */
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0, /* FLASHIO5 */
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0, /* FLASHIO6 */
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0, /* FLASHIO7 */
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0, /* FLASHIO8 */
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3, /* FLASHIO9 */
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3, /* FLASHIO10 */
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3, /* FLASHIO11 */
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0, /* GENERALIO0 */
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1, /* GENERALIO1 */
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1, /* GENERALIO2 */
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1, /* GENERALIO3 */
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1, /* GENERALIO4 */
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0, /* GENERALIO5 */
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0, /* GENERALIO6 */
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1, /* GENERALIO7 */
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1, /* GENERALIO8 */
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3, /* GENERALIO9 */
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3, /* GENERALIO10 */
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3, /* GENERALIO11 */
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3, /* GENERALIO12 */
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2, /* GENERALIO13 */
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2, /* GENERALIO14 */
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1, /* GENERALIO15 */
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1, /* GENERALIO16 */
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1, /* GENERALIO17 */
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1, /* GENERALIO18 */
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0, /* GENERALIO19 */
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0, /* GENERALIO20 */
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0, /* GENERALIO21 */
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0, /* GENERALIO22 */
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0, /* GENERALIO23 */
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0, /* GENERALIO24 */
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0, /* GENERALIO25 */
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0, /* GENERALIO26 */
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0, /* GENERALIO27 */
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0, /* GENERALIO28 */
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0, /* GENERALIO29 */
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0, /* GENERALIO30 */
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0, /* GENERALIO31 */
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2, /* MIXED1IO0 */
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2, /* MIXED1IO1 */
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2, /* MIXED1IO2 */
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2, /* MIXED1IO3 */
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2, /* MIXED1IO4 */
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2, /* MIXED1IO5 */
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2, /* MIXED1IO6 */
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2, /* MIXED1IO7 */
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2, /* MIXED1IO8 */
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2, /* MIXED1IO9 */
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2, /* MIXED1IO10 */
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2, /* MIXED1IO11 */
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2, /* MIXED1IO12 */
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2, /* MIXED1IO13 */
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0, /* MIXED1IO14 */
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3, /* MIXED1IO15 */
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3, /* MIXED1IO16 */
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3, /* MIXED1IO17 */
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3, /* MIXED1IO18 */
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3, /* MIXED1IO19 */
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3, /* MIXED1IO20 */
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0, /* MIXED1IO21 */
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0, /* MIXED2IO0 */
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0, /* MIXED2IO1 */
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0, /* MIXED2IO2 */
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0, /* MIXED2IO3 */
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0, /* MIXED2IO4 */
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0, /* MIXED2IO5 */
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0, /* MIXED2IO6 */
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0, /* MIXED2IO7 */
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0, /* GPLINMUX48 */
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0, /* GPLINMUX49 */
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0, /* GPLINMUX50 */
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0, /* GPLINMUX51 */
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0, /* GPLINMUX52 */
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0, /* GPLINMUX53 */
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0, /* GPLINMUX54 */
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0, /* GPLINMUX55 */
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0, /* GPLINMUX56 */
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0, /* GPLINMUX57 */
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0, /* GPLINMUX58 */
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0, /* GPLINMUX59 */
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0, /* GPLINMUX60 */
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0, /* GPLINMUX61 */
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0, /* GPLINMUX62 */
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0, /* GPLINMUX63 */
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0, /* GPLINMUX64 */
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0, /* GPLINMUX65 */
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0, /* GPLINMUX66 */
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0, /* GPLINMUX67 */
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0, /* GPLINMUX68 */
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0, /* GPLINMUX69 */
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0, /* GPLINMUX70 */
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1, /* GPLMUX0 */
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1, /* GPLMUX1 */
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1, /* GPLMUX2 */
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1, /* GPLMUX3 */
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1, /* GPLMUX4 */
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1, /* GPLMUX5 */
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1, /* GPLMUX6 */
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1, /* GPLMUX7 */
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1, /* GPLMUX8 */
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1, /* GPLMUX9 */
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1, /* GPLMUX10 */
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1, /* GPLMUX11 */
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1, /* GPLMUX12 */
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1, /* GPLMUX13 */
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1, /* GPLMUX14 */
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1, /* GPLMUX15 */
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1, /* GPLMUX16 */
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1, /* GPLMUX17 */
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1, /* GPLMUX18 */
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1, /* GPLMUX19 */
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1, /* GPLMUX20 */
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1, /* GPLMUX21 */
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1, /* GPLMUX22 */
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1, /* GPLMUX23 */
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1, /* GPLMUX24 */
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1, /* GPLMUX25 */
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1, /* GPLMUX26 */
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1, /* GPLMUX27 */
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1, /* GPLMUX28 */
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1, /* GPLMUX29 */
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1, /* GPLMUX30 */
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1, /* GPLMUX31 */
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1, /* GPLMUX32 */
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1, /* GPLMUX33 */
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1, /* GPLMUX34 */
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1, /* GPLMUX35 */
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1, /* GPLMUX36 */
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1, /* GPLMUX37 */
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1, /* GPLMUX38 */
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1, /* GPLMUX39 */
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1, /* GPLMUX40 */
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1, /* GPLMUX41 */
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1, /* GPLMUX42 */
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1, /* GPLMUX43 */
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1, /* GPLMUX44 */
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1, /* GPLMUX45 */
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1, /* GPLMUX46 */
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1, /* GPLMUX47 */
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1, /* GPLMUX48 */
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1, /* GPLMUX49 */
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1, /* GPLMUX50 */
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1, /* GPLMUX51 */
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1, /* GPLMUX52 */
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1, /* GPLMUX53 */
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1, /* GPLMUX54 */
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1, /* GPLMUX55 */
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1, /* GPLMUX56 */
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1, /* GPLMUX57 */
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1, /* GPLMUX58 */
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1, /* GPLMUX59 */
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1, /* GPLMUX60 */
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1, /* GPLMUX61 */
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1, /* GPLMUX62 */
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1, /* GPLMUX63 */
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1, /* GPLMUX64 */
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1, /* GPLMUX65 */
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1, /* GPLMUX66 */
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1, /* GPLMUX67 */
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1, /* GPLMUX68 */
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1, /* GPLMUX69 */
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1, /* GPLMUX70 */
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0, /* NANDUSEFPGA */
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0, /* UART0USEFPGA */
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0, /* RGMII1USEFPGA */
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0, /* SPIS0USEFPGA */
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0, /* CAN0USEFPGA */
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0, /* I2C0USEFPGA */
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0, /* SDMMCUSEFPGA */
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0, /* QSPIUSEFPGA */
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0, /* SPIS1USEFPGA */
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0, /* RGMII0USEFPGA */
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0, /* UART1USEFPGA */
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0, /* CAN1USEFPGA */
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0, /* USB1USEFPGA */
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0, /* I2C3USEFPGA */
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0, /* I2C2USEFPGA */
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0, /* I2C1USEFPGA */
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0, /* SPIM1USEFPGA */
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0, /* USB0USEFPGA */
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0 /* SPIM0USEFPGA */
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};
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@ -0,0 +1,97 @@
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#ifndef _PRELOADER_PLL_CONFIG_H_
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#define _PRELOADER_PLL_CONFIG_H_
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/* PLL configuration data */
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/* Main PLL */
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#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0)
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#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63)
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#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0)
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#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0)
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#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0)
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#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3)
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#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (3)
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#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15)
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#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1)
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#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1)
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#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1)
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#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1)
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#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0)
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#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1)
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#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0)
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/*
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* To tell where is the clock source:
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* 0 = MAINPLL
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* 1 = PERIPHPLL
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*/
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#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1)
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#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1)
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/* Peripheral PLL */
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#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1)
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#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79)
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/*
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* To tell where is the VCOs source:
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* 0 = EOSC1
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* 1 = EOSC2
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* 2 = F2S
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*/
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#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0)
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#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3)
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#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3)
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#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (1)
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#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (19)
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#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4)
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#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (9)
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#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0)
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#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0)
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#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1)
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#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1)
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#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249)
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/*
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* To tell where is the clock source:
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* 0 = F2S_PERIPH_REF_CLK
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* 1 = MAIN_CLK
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* 2 = PERIPH_CLK
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*/
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#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (1)
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#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2)
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#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1)
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/* SDRAM PLL */
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#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2)
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#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (79)
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/*
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* To tell where is the VCOs source:
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* 0 = EOSC1
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* 1 = EOSC2
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* 2 = F2S
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*/
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#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0)
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#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1)
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#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0)
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#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0)
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#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0)
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#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1)
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#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4)
|
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5)
|
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0)
|
||||
|
||||
/* Info for driver */
|
||||
#define CONFIG_HPS_CLK_OSC1_HZ (25000000)
|
||||
#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
|
||||
#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
|
||||
#define CONFIG_HPS_CLK_SDRVCO_HZ (600000000)
|
||||
#define CONFIG_HPS_CLK_EMAC0_HZ (50000000)
|
||||
#define CONFIG_HPS_CLK_EMAC1_HZ (50000000)
|
||||
#define CONFIG_HPS_CLK_USBCLK_HZ (200000000)
|
||||
#define CONFIG_HPS_CLK_NAND_HZ (100000000)
|
||||
#define CONFIG_HPS_CLK_SDMMC_HZ (50000000)
|
||||
#define CONFIG_HPS_CLK_QSPI_HZ (400000000)
|
||||
#define CONFIG_HPS_CLK_SPIM_HZ (200000000)
|
||||
#define CONFIG_HPS_CLK_CAN0_HZ (100000000)
|
||||
#define CONFIG_HPS_CLK_CAN1_HZ (100000000)
|
||||
#define CONFIG_HPS_CLK_GPIODB_HZ (32000)
|
||||
#define CONFIG_HPS_CLK_L4_MP_HZ (100000000)
|
||||
#define CONFIG_HPS_CLK_L4_SP_HZ (100000000)
|
||||
|
||||
#endif /* _PRELOADER_PLL_CONFIG_H_ */
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
#ifndef __SDRAM_CONFIG_H
|
||||
#define __SDRAM_CONFIG_H
|
||||
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE (2)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL (8)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER (0)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN (0)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN (0)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN (1)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT (10)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN (0)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS (0)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL (6)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL (0)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL (6)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD (4)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW (14)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC (117)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI (1300)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD (5)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP (5)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR (5)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR (4)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP (4)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS (12)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC (17)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD (4)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD (4)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT (200)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT (3)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES (0)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS (10)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS (15)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS (3)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS (1)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH (32)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH (8)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN (0)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL (2)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA (0)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH (2)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN (0)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE (0)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC (0)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY (0x3FFD1088)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 (0x21084210)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 (0x1EF84)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 (0x2020)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 (0x0)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 (0xF800)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 (0x200)
|
||||
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH (0x44555)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP (0x2C011000)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP (0xB00088)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP (0x760210)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP (0x980543)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR (0x5A56A)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 (0x20820820)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 (0x8208208)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 (0)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 (0x41041041)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 (0x410410)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 (0x80808080)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 (0x80808080)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 (0x8080)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ (0)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE (1)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED (0)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED (0)
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED (0)
|
||||
|
||||
#endif /*#ifndef__SDRAM_CONFIG_H*/
|
||||
|
|
@ -0,0 +1,174 @@
|
|||
#define __RW_MGR_ac_mrs1 0x04
|
||||
#define __RW_MGR_ac_mrs3 0x06
|
||||
#define __RW_MGR_ac_write_bank_0_col_0_nodata_wl_1 0x1C
|
||||
#define __RW_MGR_ac_act_1 0x11
|
||||
#define __RW_MGR_ac_write_postdata 0x1A
|
||||
#define __RW_MGR_ac_act_0 0x10
|
||||
#define __RW_MGR_ac_des 0x0D
|
||||
#define __RW_MGR_ac_init_reset_1_cke_0 0x01
|
||||
#define __RW_MGR_ac_write_data 0x19
|
||||
#define __RW_MGR_ac_init_reset_0_cke_0 0x00
|
||||
#define __RW_MGR_ac_read_bank_0_1_norden 0x22
|
||||
#define __RW_MGR_ac_pre_all 0x12
|
||||
#define __RW_MGR_ac_mrs0_user 0x02
|
||||
#define __RW_MGR_ac_mrs0_dll_reset 0x03
|
||||
#define __RW_MGR_ac_read_bank_0_0 0x1D
|
||||
#define __RW_MGR_ac_write_bank_0_col_1 0x16
|
||||
#define __RW_MGR_ac_read_bank_0_1 0x1F
|
||||
#define __RW_MGR_ac_write_bank_1_col_0 0x15
|
||||
#define __RW_MGR_ac_write_bank_1_col_1 0x17
|
||||
#define __RW_MGR_ac_write_bank_0_col_0 0x14
|
||||
#define __RW_MGR_ac_read_bank_1_0 0x1E
|
||||
#define __RW_MGR_ac_mrs1_mirr 0x0A
|
||||
#define __RW_MGR_ac_read_bank_1_1 0x20
|
||||
#define __RW_MGR_ac_des_odt_1 0x0E
|
||||
#define __RW_MGR_ac_mrs0_dll_reset_mirr 0x09
|
||||
#define __RW_MGR_ac_zqcl 0x07
|
||||
#define __RW_MGR_ac_write_predata 0x18
|
||||
#define __RW_MGR_ac_mrs0_user_mirr 0x08
|
||||
#define __RW_MGR_ac_ref 0x13
|
||||
#define __RW_MGR_ac_nop 0x0F
|
||||
#define __RW_MGR_ac_rdimm 0x23
|
||||
#define __RW_MGR_ac_mrs2_mirr 0x0B
|
||||
#define __RW_MGR_ac_write_bank_0_col_0_nodata 0x1B
|
||||
#define __RW_MGR_ac_read_en 0x21
|
||||
#define __RW_MGR_ac_mrs3_mirr 0x0C
|
||||
#define __RW_MGR_ac_mrs2 0x05
|
||||
#define __RW_MGR_CONTENT_ac_mrs1 0x10090044
|
||||
#define __RW_MGR_CONTENT_ac_mrs3 0x100B0000
|
||||
#define __RW_MGR_CONTENT_ac_write_bank_0_col_0_nodata_wl_1 0x18980000
|
||||
#define __RW_MGR_CONTENT_ac_act_1 0x106B0000
|
||||
#define __RW_MGR_CONTENT_ac_write_postdata 0x38780000
|
||||
#define __RW_MGR_CONTENT_ac_act_0 0x10680000
|
||||
#define __RW_MGR_CONTENT_ac_des 0x30780000
|
||||
#define __RW_MGR_CONTENT_ac_init_reset_1_cke_0 0x20780000
|
||||
#define __RW_MGR_CONTENT_ac_write_data 0x3CF80000
|
||||
#define __RW_MGR_CONTENT_ac_init_reset_0_cke_0 0x20700000
|
||||
#define __RW_MGR_CONTENT_ac_read_bank_0_1_norden 0x10580008
|
||||
#define __RW_MGR_CONTENT_ac_pre_all 0x10280400
|
||||
#define __RW_MGR_CONTENT_ac_mrs0_user 0x10080221
|
||||
#define __RW_MGR_CONTENT_ac_mrs0_dll_reset 0x10080320
|
||||
#define __RW_MGR_CONTENT_ac_read_bank_0_0 0x13580000
|
||||
#define __RW_MGR_CONTENT_ac_write_bank_0_col_1 0x1C980008
|
||||
#define __RW_MGR_CONTENT_ac_read_bank_0_1 0x13580008
|
||||
#define __RW_MGR_CONTENT_ac_write_bank_1_col_0 0x1C9B0000
|
||||
#define __RW_MGR_CONTENT_ac_write_bank_1_col_1 0x1C9B0008
|
||||
#define __RW_MGR_CONTENT_ac_write_bank_0_col_0 0x1C980000
|
||||
#define __RW_MGR_CONTENT_ac_read_bank_1_0 0x135B0000
|
||||
#define __RW_MGR_CONTENT_ac_mrs1_mirr 0x100A0024
|
||||
#define __RW_MGR_CONTENT_ac_read_bank_1_1 0x135B0008
|
||||
#define __RW_MGR_CONTENT_ac_des_odt_1 0x38780000
|
||||
#define __RW_MGR_CONTENT_ac_mrs0_dll_reset_mirr 0x100802C0
|
||||
#define __RW_MGR_CONTENT_ac_zqcl 0x10380400
|
||||
#define __RW_MGR_CONTENT_ac_write_predata 0x38F80000
|
||||
#define __RW_MGR_CONTENT_ac_mrs0_user_mirr 0x10080241
|
||||
#define __RW_MGR_CONTENT_ac_ref 0x10480000
|
||||
#define __RW_MGR_CONTENT_ac_nop 0x30780000
|
||||
#define __RW_MGR_CONTENT_ac_rdimm 0x10780000
|
||||
#define __RW_MGR_CONTENT_ac_mrs2_mirr 0x10090010
|
||||
#define __RW_MGR_CONTENT_ac_write_bank_0_col_0_nodata 0x18180000
|
||||
#define __RW_MGR_CONTENT_ac_read_en 0x33780000
|
||||
#define __RW_MGR_CONTENT_ac_mrs3_mirr 0x100B0000
|
||||
#define __RW_MGR_CONTENT_ac_mrs2 0x100A0008
|
||||
|
||||
#define __RW_MGR_READ_B2B_WAIT2 0x6A
|
||||
#define __RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31
|
||||
#define __RW_MGR_REFRESH_ALL 0x14
|
||||
#define __RW_MGR_ZQCL 0x06
|
||||
#define __RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x22
|
||||
#define __RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x23
|
||||
#define __RW_MGR_ACTIVATE_0_AND_1 0x0D
|
||||
#define __RW_MGR_MRS2_MIRR 0x0A
|
||||
#define __RW_MGR_INIT_RESET_0_CKE_0 0x6E
|
||||
#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x45
|
||||
#define __RW_MGR_ACTIVATE_1 0x0F
|
||||
#define __RW_MGR_MRS2 0x04
|
||||
#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34
|
||||
#define __RW_MGR_MRS1 0x03
|
||||
#define __RW_MGR_IDLE_LOOP1 0x7C
|
||||
#define __RW_MGR_GUARANTEED_WRITE_WAIT2 0x18
|
||||
#define __RW_MGR_MRS3 0x05
|
||||
#define __RW_MGR_IDLE_LOOP2 0x7B
|
||||
#define __RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E
|
||||
#define __RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24
|
||||
#define __RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C
|
||||
#define __RW_MGR_RDIMM_CMD 0x7A
|
||||
#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36
|
||||
#define __RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A
|
||||
#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38
|
||||
#define __RW_MGR_GUARANTEED_READ_CONT 0x53
|
||||
#define __RW_MGR_MRS3_MIRR 0x0B
|
||||
#define __RW_MGR_IDLE 0x00
|
||||
#define __RW_MGR_READ_B2B 0x58
|
||||
#define __RW_MGR_INIT_RESET_0_CKE_0_inloop 0x6F
|
||||
#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x37
|
||||
#define __RW_MGR_GUARANTEED_WRITE 0x17
|
||||
#define __RW_MGR_PRECHARGE_ALL 0x12
|
||||
#define __RW_MGR_INIT_RESET_1_CKE_0_inloop_1 0x74
|
||||
#define __RW_MGR_SGLE_READ 0x7E
|
||||
#define __RW_MGR_MRS0_USER_MIRR 0x0C
|
||||
#define __RW_MGR_RETURN 0x01
|
||||
#define __RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35
|
||||
#define __RW_MGR_MRS0_USER 0x07
|
||||
#define __RW_MGR_GUARANTEED_READ 0x4B
|
||||
#define __RW_MGR_MRS0_DLL_RESET_MIRR 0x08
|
||||
#define __RW_MGR_INIT_RESET_1_CKE_0 0x73
|
||||
#define __RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
|
||||
#define __RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x20
|
||||
#define __RW_MGR_MRS0_DLL_RESET 0x02
|
||||
#define __RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
|
||||
#define __RW_MGR_LFSR_WR_RD_BANK_0 0x21
|
||||
#define __RW_MGR_CLEAR_DQS_ENABLE 0x48
|
||||
#define __RW_MGR_MRS1_MIRR 0x09
|
||||
#define __RW_MGR_READ_B2B_WAIT1 0x60
|
||||
#define __RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680
|
||||
#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680
|
||||
#define __RW_MGR_CONTENT_REFRESH_ALL 0x000980
|
||||
#define __RW_MGR_CONTENT_ZQCL 0x008380
|
||||
#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_NOP 0x00E700
|
||||
#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DQS 0x000C00
|
||||
#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1 0x000800
|
||||
#define __RW_MGR_CONTENT_MRS2_MIRR 0x008580
|
||||
#define __RW_MGR_CONTENT_INIT_RESET_0_CKE_0 0x000000
|
||||
#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WAIT 0x00A680
|
||||
#define __RW_MGR_CONTENT_ACTIVATE_1 0x000880
|
||||
#define __RW_MGR_CONTENT_MRS2 0x008280
|
||||
#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WL_1 0x00CE00
|
||||
#define __RW_MGR_CONTENT_MRS1 0x008200
|
||||
#define __RW_MGR_CONTENT_IDLE_LOOP1 0x00A680
|
||||
#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT2 0x00CCE8
|
||||
#define __RW_MGR_CONTENT_MRS3 0x008300
|
||||
#define __RW_MGR_CONTENT_IDLE_LOOP2 0x008680
|
||||
#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT1 0x00AC88
|
||||
#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DATA 0x020CE0
|
||||
#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT3 0x00EC88
|
||||
#define __RW_MGR_CONTENT_RDIMM_CMD 0x009180
|
||||
#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_NOP 0x00E700
|
||||
#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8
|
||||
#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0
|
||||
#define __RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168
|
||||
#define __RW_MGR_CONTENT_MRS3_MIRR 0x008600
|
||||
#define __RW_MGR_CONTENT_IDLE 0x080000
|
||||
#define __RW_MGR_CONTENT_READ_B2B 0x040E88
|
||||
#define __RW_MGR_CONTENT_INIT_RESET_0_CKE_0_inloop 0x000000
|
||||
#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00
|
||||
#define __RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68
|
||||
#define __RW_MGR_CONTENT_PRECHARGE_ALL 0x000900
|
||||
#define __RW_MGR_CONTENT_INIT_RESET_1_CKE_0_inloop_1 0x000080
|
||||
#define __RW_MGR_CONTENT_SGLE_READ 0x040F08
|
||||
#define __RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400
|
||||
#define __RW_MGR_CONTENT_RETURN 0x080680
|
||||
#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0 0x00CD80
|
||||
#define __RW_MGR_CONTENT_MRS0_USER 0x008100
|
||||
#define __RW_MGR_CONTENT_GUARANTEED_READ 0x001168
|
||||
#define __RW_MGR_CONTENT_MRS0_DLL_RESET_MIRR 0x008480
|
||||
#define __RW_MGR_CONTENT_INIT_RESET_1_CKE_0 0x000080
|
||||
#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT2 0x00A680
|
||||
#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WL_1 0x00CE00
|
||||
#define __RW_MGR_CONTENT_MRS0_DLL_RESET 0x008180
|
||||
#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT1 0x008680
|
||||
#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0 0x00CD80
|
||||
#define __RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158
|
||||
#define __RW_MGR_CONTENT_MRS1_MIRR 0x008500
|
||||
#define __RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680
|
||||
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
static const uint32_t ac_rom_init_size = 36;
|
||||
static const uint32_t ac_rom_init[36] =
|
||||
{
|
||||
0x20700000,
|
||||
0x20780000,
|
||||
0x10080221,
|
||||
0x10080320,
|
||||
0x10090044,
|
||||
0x100a0008,
|
||||
0x100b0000,
|
||||
0x10380400,
|
||||
0x10080241,
|
||||
0x100802c0,
|
||||
0x100a0024,
|
||||
0x10090010,
|
||||
0x100b0000,
|
||||
0x30780000,
|
||||
0x38780000,
|
||||
0x30780000,
|
||||
0x10680000,
|
||||
0x106b0000,
|
||||
0x10280400,
|
||||
0x10480000,
|
||||
0x1c980000,
|
||||
0x1c9b0000,
|
||||
0x1c980008,
|
||||
0x1c9b0008,
|
||||
0x38f80000,
|
||||
0x3cf80000,
|
||||
0x38780000,
|
||||
0x18180000,
|
||||
0x18980000,
|
||||
0x13580000,
|
||||
0x135b0000,
|
||||
0x13580008,
|
||||
0x135b0008,
|
||||
0x33780000,
|
||||
0x10580008,
|
||||
0x10780000
|
||||
};
|
||||
|
|
@ -0,0 +1,132 @@
|
|||
static const uint32_t inst_rom_init_size = 128;
|
||||
static const uint32_t inst_rom_init[128] =
|
||||
{
|
||||
0x80000,
|
||||
0x80680,
|
||||
0x8180,
|
||||
0x8200,
|
||||
0x8280,
|
||||
0x8300,
|
||||
0x8380,
|
||||
0x8100,
|
||||
0x8480,
|
||||
0x8500,
|
||||
0x8580,
|
||||
0x8600,
|
||||
0x8400,
|
||||
0x800,
|
||||
0x8680,
|
||||
0x880,
|
||||
0xa680,
|
||||
0x80680,
|
||||
0x900,
|
||||
0x80680,
|
||||
0x980,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0xb68,
|
||||
0xcce8,
|
||||
0xae8,
|
||||
0x8ce8,
|
||||
0xb88,
|
||||
0xec88,
|
||||
0xa08,
|
||||
0xac88,
|
||||
0x80680,
|
||||
0xce00,
|
||||
0xcd80,
|
||||
0xe700,
|
||||
0xc00,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0xd00,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x60e80,
|
||||
0x61080,
|
||||
0x61080,
|
||||
0x61080,
|
||||
0xa680,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0xce00,
|
||||
0xcd80,
|
||||
0xe700,
|
||||
0xc00,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0xd00,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x70e80,
|
||||
0x71080,
|
||||
0x71080,
|
||||
0x71080,
|
||||
0xa680,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0x1158,
|
||||
0x6d8,
|
||||
0x80680,
|
||||
0x1168,
|
||||
0x7e8,
|
||||
0x7e8,
|
||||
0x87e8,
|
||||
0x40fe8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x1168,
|
||||
0x7e8,
|
||||
0x7e8,
|
||||
0xa7e8,
|
||||
0x80680,
|
||||
0x40e88,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x40f68,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0xa680,
|
||||
0x40fe8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x41008,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x1100,
|
||||
0xc680,
|
||||
0x8680,
|
||||
0xe680,
|
||||
0x80680,
|
||||
0x0,
|
||||
0x0,
|
||||
0xa000,
|
||||
0x8000,
|
||||
0x80000,
|
||||
0x80,
|
||||
0x80,
|
||||
0x80,
|
||||
0x80,
|
||||
0xa080,
|
||||
0x8080,
|
||||
0x80080,
|
||||
0x9180,
|
||||
0x8680,
|
||||
0xa680,
|
||||
0x80680,
|
||||
0x40f08,
|
||||
0x80680
|
||||
};
|
||||
|
|
@ -0,0 +1,118 @@
|
|||
#ifndef _SEQUENCER_DEFINES_H_
|
||||
#define _SEQUENCER_DEFINES_H_
|
||||
|
||||
#define AC_ROM_MR1_MIRR 0000000100100
|
||||
#define AC_ROM_MR1_OCD_ENABLE
|
||||
#define AC_ROM_MR2_MIRR 0000000010000
|
||||
#define AC_ROM_MR3_MIRR 0000000000000
|
||||
#define AC_ROM_MR0_CALIB
|
||||
#define AC_ROM_MR0_DLL_RESET_MIRR 0001011000000
|
||||
#define AC_ROM_MR0_DLL_RESET 0001100100000
|
||||
#define AC_ROM_MR0_MIRR 0001001000001
|
||||
#define AC_ROM_MR0 0001000100001
|
||||
#define AC_ROM_MR1 0000001000100
|
||||
#define AC_ROM_MR2 0000000001000
|
||||
#define AC_ROM_MR3 0000000000000
|
||||
#define AFI_CLK_FREQ 334
|
||||
#define AFI_RATE_RATIO 1
|
||||
#define ARRIAVGZ 0
|
||||
#define ARRIAV 0
|
||||
#define AVL_CLK_FREQ 67
|
||||
#define BFM_MODE 0
|
||||
#define BURST2 0
|
||||
#define CALIBRATE_BIT_SLIPS 0
|
||||
#define CALIB_LFIFO_OFFSET 6
|
||||
#define CALIB_VFIFO_OFFSET 4
|
||||
#define CYCLONEV 1
|
||||
#define DDR2 0
|
||||
#define DDR3 1
|
||||
#define DDRX 1
|
||||
#define DM_PINS_ENABLED 1
|
||||
#define ENABLE_ASSERT 0
|
||||
#define ENABLE_BRINGUP_DEBUGGING 0
|
||||
#define ENABLE_DQS_IN_CENTERING 1
|
||||
#define ENABLE_DQS_OUT_CENTERING 0
|
||||
#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0
|
||||
#define ENABLE_INST_ROM_WRITE 1
|
||||
#define ENABLE_MARGIN_REPORT_GEN 0
|
||||
#define ENABLE_NON_DESTRUCTIVE_CALIB 0
|
||||
#define ENABLE_SUPER_QUICK_CALIBRATION 0
|
||||
#define ENABLE_TCL_DEBUG 0
|
||||
#define FULL_RATE 1
|
||||
#define GUARANTEED_READ_BRINGUP_TEST 0
|
||||
#define HALF_RATE 0
|
||||
#define HARD_PHY 1
|
||||
#define HARD_VFIFO 1
|
||||
#define HCX_COMPAT_MODE 0
|
||||
#define HHP_HPS_SIMULATION 0
|
||||
#define HHP_HPS_VERIFICATION 0
|
||||
#define HHP_HPS 1
|
||||
#define HPS_HW 1
|
||||
#define HR_DDIO_OUT_HAS_THREE_REGS 0
|
||||
#define IO_DELAY_PER_DCHAIN_TAP 25
|
||||
#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
|
||||
#define IO_DELAY_PER_OPA_TAP 375
|
||||
#define IO_DLL_CHAIN_LENGTH 8
|
||||
#define IO_DM_OUT_RESERVE 0
|
||||
#define IO_DQDQS_OUT_PHASE_MAX 0
|
||||
#define IO_DQS_EN_DELAY_MAX 31
|
||||
#define IO_DQS_EN_DELAY_OFFSET 0
|
||||
#define IO_DQS_EN_PHASE_MAX 7
|
||||
#define IO_DQS_IN_DELAY_MAX 31
|
||||
#define IO_DQS_IN_RESERVE 4
|
||||
#define IO_DQS_OUT_RESERVE 4
|
||||
#define IO_DQ_OUT_RESERVE 0
|
||||
#define IO_IO_IN_DELAY_MAX 31
|
||||
#define IO_IO_OUT1_DELAY_MAX 31
|
||||
#define IO_IO_OUT2_DELAY_MAX 0
|
||||
#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
|
||||
#define LPDDR1 0
|
||||
#define LPDDR2 0
|
||||
#define LRDIMM 0
|
||||
#define MARGIN_VARIATION_TEST 0
|
||||
#define MAX_LATENCY_COUNT_WIDTH 5
|
||||
#define MEM_ADDR_WIDTH 13
|
||||
#define MULTIPLE_AFI_WLAT 0
|
||||
#define NUM_SHADOW_REGS 1
|
||||
#define QDRII 0
|
||||
#define QUARTER_RATE 0
|
||||
#define RDIMM 0
|
||||
#define READ_AFTER_WRITE_CALIBRATION 1
|
||||
#define READ_VALID_FIFO_SIZE 16
|
||||
#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550482
|
||||
#define RLDRAM3 0
|
||||
#define RLDRAMII 0
|
||||
#define RLDRAMX 0
|
||||
#define RUNTIME_CAL_REPORT 0
|
||||
#define RW_MGR_MEM_ADDRESS_MIRRORING 0
|
||||
#define RW_MGR_MEM_ADDRESS_WIDTH 15
|
||||
#define RW_MGR_MEM_BANK_WIDTH 3
|
||||
#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1
|
||||
#define RW_MGR_MEM_CLK_EN_WIDTH 1
|
||||
#define RW_MGR_MEM_CONTROL_WIDTH 1
|
||||
#define RW_MGR_MEM_DATA_MASK_WIDTH 4
|
||||
#define RW_MGR_MEM_DATA_WIDTH 32
|
||||
#define RW_MGR_MEM_DQ_PER_READ_DQS 8
|
||||
#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
|
||||
#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
|
||||
#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
|
||||
#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
|
||||
#define RW_MGR_MEM_NUMBER_OF_RANKS 1
|
||||
#define RW_MGR_MEM_ODT_WIDTH 1
|
||||
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
|
||||
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
|
||||
#define RW_MGR_MR0_BL 1
|
||||
#define RW_MGR_MR0_CAS_LATENCY 2
|
||||
#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
|
||||
#define RW_MGR_WRITE_TO_DEBUG_READ 1.0
|
||||
#define SKEW_CALIBRATION 0
|
||||
#define STATIC_FULL_CALIBRATION 1
|
||||
#define STATIC_SIM_FILESET 0
|
||||
#define STATIC_SKIP_MEM_INIT 0
|
||||
#define STRATIXV 0
|
||||
#define TRACKING_ERROR_TEST 0
|
||||
#define TRACKING_WATCH_TEST 0
|
||||
#define USE_DQS_TRACKING 1
|
||||
#define USE_SHADOW_REGS 0
|
||||
|
||||
#endif /* _SEQUENCER_DEFINES_H_ */
|
||||
|
|
@ -11,7 +11,8 @@ dtb-$(CONFIG_ARCH_IMX6) += imx6q-gk802.dtb \
|
|||
imx6q-mba6x.dtb \
|
||||
imx6q-phytec-pbab01.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += dove-cubox.dtb
|
||||
dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_sockit.dtb
|
||||
dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_sockit.dtb \
|
||||
socfpga_cyclone5_socrates.dtb
|
||||
|
||||
BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME))
|
||||
obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
|
||||
|
|
@ -25,6 +26,7 @@ pbl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-realq7.dtb.o
|
|||
pbl-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox.dtb.o
|
||||
pbl-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o
|
||||
pbl-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o
|
||||
pbl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o
|
||||
pbl-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o
|
||||
|
||||
.SECONDARY: $(obj)/$(BUILTIN_DTB).dtb.S
|
||||
|
|
|
|||
|
|
@ -0,0 +1,64 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/include/ "socfpga_cyclone5.dtsi"
|
||||
|
||||
/ {
|
||||
model = "EBV SoCrates";
|
||||
compatible = "ebv,socrates", "altr,socfpga";
|
||||
|
||||
chosen {
|
||||
};
|
||||
|
||||
memory {
|
||||
name = "memory";
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0>;
|
||||
};
|
||||
|
||||
leds: gpio-leds {
|
||||
};
|
||||
};
|
||||
|
||||
&leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led@0 {
|
||||
label = "0";
|
||||
gpios = <&gpio0 28 1>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
label = "1";
|
||||
gpios = <&gpio1 19 1>;
|
||||
};
|
||||
|
||||
led@2 {
|
||||
label = "2";
|
||||
gpios = <&gpio1 25 1>;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
phy-mode = "rgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -8,6 +8,10 @@ config ARCH_TEXT_BASE
|
|||
hex
|
||||
default 0x00100000 if MACH_SOCFPGA_CYCLONE5
|
||||
|
||||
config MACH_SOCFPGA_EBV_SOCRATES
|
||||
select HAVE_DEFAULT_ENVIRONMENT_NEW
|
||||
bool "EBV Socrates"
|
||||
|
||||
config MACH_SOCFPGA_TERASIC_SOCKIT
|
||||
select HAVE_DEFAULT_ENVIRONMENT_NEW
|
||||
bool "Terasic SoCKit"
|
||||
|
|
|
|||
|
|
@ -19,6 +19,14 @@ pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += start_socfpga_sockit
|
|||
FILE_barebox-socfpga-sockit.img = start_socfpga_sockit.pblx
|
||||
barebox-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += barebox-socfpga-sockit.img
|
||||
|
||||
pblx-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += start_socfpga_socrates_xload
|
||||
FILE_barebox-socfpga-socrates-xload.img = start_socfpga_socrates_xload.pblx.socfpgaimg
|
||||
xload-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += barebox-socfpga-socrates-xload.img
|
||||
|
||||
pblx-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += start_socfpga_socrates
|
||||
FILE_barebox-socfpga-socrates.img = start_socfpga_socrates.pblx
|
||||
barebox-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += barebox-socfpga-socrates.img
|
||||
|
||||
ifdef CONFIG_ARCH_SOCFPGA_XLOAD
|
||||
image-y += $(xload-y)
|
||||
else
|
||||
|
|
|
|||
Loading…
Reference in New Issue