ARM i.MX: rework bootsource setting
This moves the known i.MX bootsource settings to a single file so that the code can be shared. Also we add a enum for the different boot sources so that it can be used in C Code and not only on the shell. The pcm038 board is changed to use it instead of digging in the registers manually. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
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cff3972712
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a029e32d7f
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@ -39,6 +39,7 @@
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#include <mach/devices-imx27.h>
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#include <mach/iim.h>
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#include <mfd/mc13xxx.h>
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#include <mach/generic.h>
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#include "pll.h"
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@ -302,11 +303,8 @@ static int pcm038_devices_init(void)
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*/
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imx27_add_fec(&fec_info);
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switch ((GPCR & GPCR_BOOT_MASK) >> GPCR_BOOT_SHIFT) {
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case GPCR_BOOT_8BIT_NAND_2k:
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case GPCR_BOOT_16BIT_NAND_2k:
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case GPCR_BOOT_16BIT_NAND_512:
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case GPCR_BOOT_8BIT_NAND_512:
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switch (imx_bootsource()) {
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case bootsource_nand:
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devfs_add_partition("nand0", 0x00000, 0x80000,
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DEVFS_PARTITION_FIXED, "self_raw");
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dev_add_bb_dev("self_raw", "self0");
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@ -17,9 +17,64 @@
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#include <magicvar.h>
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#include <io.h>
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#include <mach/imx-regs.h>
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#include <mach/generic.h>
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static const char *bootsource_str[] = {
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[bootsource_unknown] = "unknown",
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[bootsource_nand] = "nand",
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[bootsource_nor] = "nor",
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[bootsource_mmc] = "mmc",
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[bootsource_i2c] = "i2c",
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[bootsource_spi] = "spi",
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[bootsource_serial] = "serial",
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[bootsource_onenand] = "onenand",
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};
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static enum imx_bootsource bootsource;
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void imx_set_bootsource(enum imx_bootsource src)
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{
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if (src >= ARRAY_SIZE(bootsource_str))
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src = bootsource_unknown;
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bootsource = src;
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setenv("barebox_loc", bootsource_str[src]);
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export("barebox_loc");
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}
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enum imx_bootsource imx_bootsource(void)
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{
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return bootsource;
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}
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BAREBOX_MAGICVAR(barebox_loc, "The source barebox has been booted from");
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/* [CTRL][TYPE] */
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static const enum imx_bootsource locations[4][4] = {
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{ /* CTRL = WEIM */
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bootsource_nor,
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bootsource_unknown,
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bootsource_onenand,
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bootsource_unknown,
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}, { /* CTRL == NAND */
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bootsource_nand,
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bootsource_nand,
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bootsource_nand,
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bootsource_nand,
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}, { /* CTRL == ATA, (imx35 only) */
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bootsource_unknown,
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bootsource_unknown, /* might be p-ata */
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bootsource_unknown,
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bootsource_unknown,
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}, { /* CTRL == expansion */
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bootsource_mmc, /* note imx25 could also be: movinand, ce-ata */
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bootsource_unknown,
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bootsource_i2c,
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bootsource_spi,
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}
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};
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#if defined(CONFIG_ARCH_IMX25) || defined(CONFIG_ARCH_IMX35)
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/*
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* Saves the boot source media into the $barebox_loc enviroment variable
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*
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@ -38,43 +93,14 @@
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* Note also that I suspect that the boot source pins are only sampled at
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* power up.
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*/
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static int imx_25_35_boot_save_loc(void)
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int imx_25_35_boot_save_loc(unsigned int ctrl, unsigned int type)
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{
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const char *bareboxloc = NULL;
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uint32_t reg;
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unsigned int ctrl, type;
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enum imx_bootsource src;
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/* [CTRL][TYPE] */
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const char *const locations[4][4] = {
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{ /* CTRL = WEIM */
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"nor",
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NULL,
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"onenand",
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NULL,
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}, { /* CTRL == NAND */
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"nand",
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"nand",
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"nand",
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"nand",
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}, { /* CTRL == ATA, (imx35 only) */
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NULL,
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NULL, /* might be p-ata */
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NULL,
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NULL,
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}, { /* CTRL == expansion */
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"mmc", /* note imx25 could also be: movinand, ce-ata */
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NULL,
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"i2c",
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"spi",
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}
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};
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reg = readl(IMX_CCM_BASE + CCM_RCSR);
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ctrl = (reg >> CCM_RCSR_MEM_CTRL_SHIFT) & 0x3;
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type = (reg >> CCM_RCSR_MEM_TYPE_SHIFT) & 0x3;
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bareboxloc = locations[ctrl][type];
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src = locations[ctrl][type];
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imx_set_bootsource(src);
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if (bareboxloc) {
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setenv("barebox_loc", bareboxloc);
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export("barebox_loc");
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@ -82,32 +108,78 @@ static int imx_25_35_boot_save_loc(void)
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return 0;
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}
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coredevice_initcall(imx_25_35_boot_save_loc);
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#endif
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#if defined(CONFIG_ARCH_IMX27)
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static int imx_27_boot_save_loc(void)
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#define IMX27_SYSCTRL_GPCR 0x18
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#define IMX27_GPCR_BOOT_SHIFT 16
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#define IMX27_GPCR_BOOT_MASK (0xf << IMX27_GPCR_BOOT_SHIFT)
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#define IMX27_GPCR_BOOT_UART_USB 0
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#define IMX27_GPCR_BOOT_8BIT_NAND_2k 2
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#define IMX27_GPCR_BOOT_16BIT_NAND_2k 3
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#define IMX27_GPCR_BOOT_16BIT_NAND_512 4
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#define IMX27_GPCR_BOOT_16BIT_CS0 5
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#define IMX27_GPCR_BOOT_32BIT_CS0 6
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#define IMX27_GPCR_BOOT_8BIT_NAND_512 7
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void imx_27_boot_save_loc(void __iomem *sysctrl_base)
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{
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switch ((GPCR & GPCR_BOOT_MASK) >> GPCR_BOOT_SHIFT) {
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case GPCR_BOOT_UART_USB:
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setenv("barebox_loc", "serial");
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enum imx_bootsource src;
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uint32_t val;
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val = readl(sysctrl_base + IMX27_SYSCTRL_GPCR);
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val &= IMX27_GPCR_BOOT_MASK;
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val >>= IMX27_GPCR_BOOT_SHIFT;
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switch (val) {
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case IMX27_GPCR_BOOT_UART_USB:
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src = bootsource_serial;
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break;
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case GPCR_BOOT_8BIT_NAND_2k:
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case GPCR_BOOT_16BIT_NAND_2k:
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case GPCR_BOOT_16BIT_NAND_512:
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case GPCR_BOOT_8BIT_NAND_512:
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setenv("barebox_loc", "nand");
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case IMX27_GPCR_BOOT_8BIT_NAND_2k:
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case IMX27_GPCR_BOOT_16BIT_NAND_2k:
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case IMX27_GPCR_BOOT_16BIT_NAND_512:
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case IMX27_GPCR_BOOT_8BIT_NAND_512:
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src = bootsource_nand;
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break;
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default:
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setenv("barebox_loc", "nor");
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src = bootsource_nor;
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break;
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}
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export("barebox_loc");
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imx_set_bootsource(src);
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}
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#define IMX51_SRC_SBMR 0x4
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#define IMX51_SBMR_BT_MEM_TYPE_SHIFT 7
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#define IMX51_SBMR_BT_MEM_CTL_SHIFT 0
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#define IMX51_SBMR_BMOD_SHIFT 14
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int imx51_boot_save_loc(void __iomem *src_base)
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{
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enum imx_bootsource src = bootsource_unknown;
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uint32_t reg;
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unsigned int ctrl, type;
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reg = readl(src_base + IMX51_SRC_SBMR);
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switch ((reg >> IMX51_SBMR_BMOD_SHIFT) & 0x3) {
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case 0:
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case 2:
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/* internal boot */
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ctrl = (reg >> IMX51_SBMR_BT_MEM_CTL_SHIFT) & 0x3;
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type = (reg >> IMX51_SBMR_BT_MEM_TYPE_SHIFT) & 0x3;
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src = locations[ctrl][type];
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break;
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case 1:
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/* reserved */
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src = bootsource_unknown;
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break;
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case 3:
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src = bootsource_serial;
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break;
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}
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imx_set_bootsource(src);
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return 0;
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}
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coredevice_initcall(imx_27_boot_save_loc);
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#endif
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BAREBOX_MAGICVAR(barebox_loc, "The source barebox has been booted from");
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@ -17,6 +17,7 @@
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#include <mach/iim.h>
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#include <io.h>
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#include <mach/weim.h>
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#include <mach/generic.h>
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#include <sizes.h>
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void imx25_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
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static int imx25_init(void)
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{
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uint32_t val;
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val = readl(MX25_CCM_BASE_ADDR + CCM_RCSR);
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imx_25_35_boot_save_loc((val >> CCM_RCSR_MEM_CTRL_SHIFT) & 0x3,
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(val >> CCM_RCSR_MEM_TYPE_SHIFT) & 0x3);
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add_generic_device("imx_iim", 0, NULL, MX25_IIM_BASE_ADDR, SZ_4K,
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IORESOURCE_MEM, &imx25_iim_pdata);
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@ -17,6 +17,7 @@
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#include <mach/iomux-v1.h>
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#include <sizes.h>
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#include <mach/revision.h>
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#include <mach/generic.h>
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#include <init.h>
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#include <io.h>
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static int imx27_init(void)
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{
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imx27_silicon_revision();
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imx_27_boot_save_loc((void *)MX27_SYSCTRL_BASE_ADDR);
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imx_iomuxv1_init((void *)MX27_GPIO1_BASE_ADDR);
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@ -59,8 +59,14 @@ core_initcall(imx35_l2_fix);
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static int imx35_init(void)
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{
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uint32_t val;
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imx35_silicon_revision();
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val = readl(MX35_CCM_BASE_ADDR + CCM_RCSR);
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imx_25_35_boot_save_loc((val >> CCM_RCSR_MEM_CTRL_SHIFT) & 0x3,
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(val >> CCM_RCSR_MEM_TYPE_SHIFT) & 0x3);
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add_generic_device("imx_iim", 0, NULL, MX35_IIM_BASE_ADDR, SZ_4K,
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IORESOURCE_MEM, NULL);
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#include <mach/imx-regs.h>
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#include <mach/revision.h>
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#include <mach/clock-imx51_53.h>
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#include <mach/generic.h>
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#define SI_REV 0x48
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@ -69,6 +70,7 @@ device_initcall(imx51_print_silicon_rev);
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static int imx51_init(void)
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{
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imx51_silicon_revision();
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imx51_boot_save_loc((void *)MX51_SRC_BASE_ADDR);
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add_generic_device("imx_iim", 0, NULL, MX51_IIM_BASE_ADDR, SZ_4K,
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IORESOURCE_MEM, NULL);
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* power up.
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*/
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#define SRC_SBMR 0x4
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#define SBMR_BT_MEM_TYPE_SHIFT 7
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#define SBMR_BT_MEM_CTL_SHIFT 0
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#define SBMR_BMOD_SHIFT 14
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static int imx51_boot_save_loc(void)
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{
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const char *bareboxloc = NULL;
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uint32_t reg;
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unsigned int ctrl, type;
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/* [CTRL][TYPE] */
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const char *const locations[4][4] = {
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{ /* CTRL = WEIM */
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"nor",
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NULL,
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"onenand",
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NULL,
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}, { /* CTRL == NAND */
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"nand",
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"nand",
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"nand",
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"nand",
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}, { /* CTRL == reserved */
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NULL,
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NULL,
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NULL,
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NULL,
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}, { /* CTRL == expansion */
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"mmc",
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NULL,
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"i2c",
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"spi",
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}
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};
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reg = readl(MX51_SRC_BASE_ADDR + SRC_SBMR);
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switch ((reg >> SBMR_BMOD_SHIFT) & 0x3) {
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case 0:
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case 2:
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/* internal boot */
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ctrl = (reg >> SBMR_BT_MEM_CTL_SHIFT) & 0x3;
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type = (reg >> SBMR_BT_MEM_TYPE_SHIFT) & 0x3;
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bareboxloc = locations[ctrl][type];
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break;
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case 1:
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/* reserved */
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bareboxloc = "unknown";
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break;
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case 3:
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bareboxloc = "serial";
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break;
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}
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if (bareboxloc) {
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setenv("barebox_loc", bareboxloc);
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export("barebox_loc");
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}
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return 0;
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}
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coredevice_initcall(imx51_boot_save_loc);
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#define setup_pll_800(base) imx5_setup_pll((base), 800, (( 8 << 4) + ((1 - 1) << 0)), ( 3 - 1), 1)
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#define setup_pll_665(base) imx5_setup_pll((base), 665, (( 6 << 4) + ((1 - 1) << 0)), (96 - 1), 89)
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#define setup_pll_600(base) imx5_setup_pll((base), 600, (( 6 << 4) + ((1 - 1) << 0)), ( 4 - 1), 1)
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@ -1,6 +1,23 @@
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u64 imx_uid(void);
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enum imx_bootsource {
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bootsource_unknown,
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bootsource_nand,
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bootsource_nor,
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bootsource_mmc,
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bootsource_i2c,
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bootsource_spi,
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bootsource_serial,
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bootsource_onenand,
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};
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enum imx_bootsource imx_bootsource(void);
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void imx_set_bootsource(enum imx_bootsource src);
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int imx_25_35_boot_save_loc(unsigned int ctrl, unsigned int type);
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void imx_27_boot_save_loc(void __iomem *sysctrl_base);
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int imx51_boot_save_loc(void __iomem *src_base);
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#ifdef CONFIG_ARCH_IMX1
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#define cpu_is_mx1() (1)
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#define WBCR __REG(MX27_SYSCTRL_BASE_ADDR + 0x1C) /* Well Bias Control Register */
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#define DSCR(x) __REG(MX27_SYSCTRL_BASE_ADDR + 0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */
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#define GPCR_BOOT_SHIFT 16
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#define GPCR_BOOT_MASK (0xf << GPCR_BOOT_SHIFT)
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#define GPCR_BOOT_UART_USB 0
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#define GPCR_BOOT_8BIT_NAND_2k 2
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#define GPCR_BOOT_16BIT_NAND_2k 3
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#define GPCR_BOOT_16BIT_NAND_512 4
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#define GPCR_BOOT_16BIT_CS0 5
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#define GPCR_BOOT_32BIT_CS0 6
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#define GPCR_BOOT_8BIT_NAND_512 7
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#include "esdctl.h"
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/* PLL registers */
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