Merge branch 'for-next/dts'
This commit is contained in:
commit
a06513273f
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@ -62,6 +62,9 @@ wants to support one of the below features, it should adapt the bindings below.
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"irq" and "wakeup" names are recognized by I2C core, other names are
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left to individual drivers.
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- host-notify
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device uses SMBus host notify protocol instead of interrupt line.
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- multi-master
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states that there is another master active on this bus. The OS can use
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this information to adapt power management to keep the arbitration awake
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@ -81,6 +84,11 @@ Binding may contain optional "interrupts" property, describing interrupts
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used by the device. I2C core will assign "irq" interrupt (or the very first
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interrupt if not using interrupt names) as primary interrupt for the slave.
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Alternatively, devices supporting SMbus Host Notify, and connected to
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adapters that support this feature, may use "host-notify" property. I2C
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core will create a virtual interrupt for Host Notify and assign it as
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primary interrupt for the slave.
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Also, if device is marked as a wakeup source, I2C core will set up "wakeup"
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interrupt for the device. If "wakeup" interrupt name is not present in the
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binding, then primary interrupt will be used as wakeup interrupt.
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@ -15,6 +15,9 @@ Properties:
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Second cell specifies the irq distribution mode to cores
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0=Round Robin; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
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The second cell in interrupts property is deprecated and may be ignored by
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the kernel.
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intc accessed via the special ARC AUX register interface, hence "reg" property
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is not specified.
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@ -5,7 +5,7 @@ Required properties:
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- compatible: "sigma,smp8758-nand"
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- reg: address/size of nfc_reg, nfc_mem, and pbus_reg
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- dmas: reference to the DMA channel used by the controller
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- dma-names: "nfc_sbox"
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- dma-names: "rxtx"
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- clocks: reference to the system clock
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- #address-cells: <1>
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- #size-cells: <0>
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@ -17,9 +17,9 @@ Example:
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nandc: nand-controller@2c000 {
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compatible = "sigma,smp8758-nand";
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reg = <0x2c000 0x30 0x2d000 0x800 0x20000 0x1000>;
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reg = <0x2c000 0x30>, <0x2d000 0x800>, <0x20000 0x1000>;
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dmas = <&dma0 3>;
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dma-names = "nfc_sbox";
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dma-names = "rxtx";
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clocks = <&clkgen SYS_CLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -7,7 +7,7 @@ have dual GMAC each represented by a child node..
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* Ethernet controller node
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Required properties:
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- compatible: Should be "mediatek,mt7623-eth"
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- compatible: Should be "mediatek,mt2701-eth"
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- reg: Address and length of the register set for the device
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- interrupts: Should contain the three frame engines interrupts in numeric
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order. These are fe_int0, fe_int1 and fe_int2.
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@ -19,8 +19,9 @@ Optional Properties:
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specifications. If neither of these are specified, the default is to
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assume clause 22.
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If the phy's identifier is known then the list may contain an entry
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of the form: "ethernet-phy-idAAAA.BBBB" where
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If the PHY reports an incorrect ID (or none at all) then the
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"compatible" list may contain an entry with the correct PHY ID in the
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form: "ethernet-phy-idAAAA.BBBB" where
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AAAA - The value of the 16 bit Phy Identifier 1 register as
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4 hex digits. This is the chip vendor OUI bits 3:18
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BBBB - The value of the 16 bit Phy Identifier 2 register as
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@ -3,9 +3,11 @@
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Required properties:
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- reg - The ID number for the phy, usually a small integer
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- ti,rx-internal-delay - RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
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for applicable values
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for applicable values. Required only if interface type is
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PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID
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- ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
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for applicable values
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for applicable values. Required only if interface type is
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PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID
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- ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
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for applicable values
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@ -1,17 +1,23 @@
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Renesas MSIOF spi controller
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Required properties:
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- compatible : "renesas,msiof-<soctype>" for SoCs,
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"renesas,sh-msiof" for SuperH, or
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"renesas,sh-mobile-msiof" for SH Mobile series.
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Examples with soctypes are:
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"renesas,msiof-r8a7790" (R-Car H2)
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- compatible : "renesas,msiof-r8a7790" (R-Car H2)
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"renesas,msiof-r8a7791" (R-Car M2-W)
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"renesas,msiof-r8a7792" (R-Car V2H)
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"renesas,msiof-r8a7793" (R-Car M2-N)
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"renesas,msiof-r8a7794" (R-Car E2)
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"renesas,msiof-r8a7796" (R-Car M3-W)
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"renesas,msiof-sh73a0" (SH-Mobile AG5)
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"renesas,sh-mobile-msiof" (generic SH-Mobile compatibile device)
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"renesas,rcar-gen2-msiof" (generic R-Car Gen2 compatible device)
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"renesas,rcar-gen3-msiof" (generic R-Car Gen3 compatible device)
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"renesas,sh-msiof" (deprecated)
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When compatible with the generic version, nodes
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must list the SoC-specific version corresponding
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to the platform first followed by the generic
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version.
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- reg : A list of offsets and lengths of the register sets for
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the device.
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If only one register set is present, it is to be used
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@ -61,7 +67,8 @@ Documentation/devicetree/bindings/pinctrl/renesas,*.
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Example:
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msiof0: spi@e6e20000 {
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compatible = "renesas,msiof-r8a7791";
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compatible = "renesas,msiof-r8a7791",
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"renesas,rcar-gen2-msiof";
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reg = <0 0xe6e20000 0 0x0064>;
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interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
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@ -170,7 +170,6 @@
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AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */
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AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */
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AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */
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AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE5) /* (C15) spi0_cs1.mmc0_sdcd */
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>;
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};
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@ -160,7 +160,7 @@
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axi {
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compatible = "simple-bus";
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ranges = <0x00000000 0x18000000 0x0011c40a>;
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ranges = <0x00000000 0x18000000 0x0011c40c>;
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#address-cells = <1>;
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#size-cells = <1>;
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@ -99,6 +99,7 @@
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#size-cells = <1>;
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compatible = "m25p64";
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spi-max-frequency = <30000000>;
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m25p,fast-read;
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reg = <0>;
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partition@0 {
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label = "U-Boot-SPL";
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@ -1378,6 +1378,7 @@
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phy-names = "sata-phy";
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clocks = <&sata_ref_clk>;
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ti,hwmods = "sata";
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ports-implemented = <0x1>;
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};
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rtc: rtc@48838000 {
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@ -75,6 +75,6 @@
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
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ti,min-output-imepdance;
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ti,min-output-impedance;
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};
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};
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@ -319,8 +319,6 @@
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compatible = "fsl,imx6q-nitrogen6_max-sgtl5000",
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"fsl,imx-audio-sgtl5000";
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model = "imx6q-nitrogen6_max-sgtl5000";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sgtl5000>;
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ssi-controller = <&ssi1>;
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audio-codec = <&codec>;
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audio-routing =
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@ -402,6 +400,8 @@
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codec: sgtl5000@0a {
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compatible = "fsl,sgtl5000";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sgtl5000>;
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reg = <0x0a>;
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clocks = <&clks IMX6QDL_CLK_CKO>;
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VDDA-supply = <®_2p5v>;
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@ -250,8 +250,6 @@
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compatible = "fsl,imx6q-nitrogen6_som2-sgtl5000",
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"fsl,imx-audio-sgtl5000";
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model = "imx6q-nitrogen6_som2-sgtl5000";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sgtl5000>;
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ssi-controller = <&ssi1>;
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audio-codec = <&codec>;
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audio-routing =
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@ -320,6 +318,8 @@
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codec: sgtl5000@0a {
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compatible = "fsl,sgtl5000";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sgtl5000>;
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reg = <0x0a>;
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clocks = <&clks IMX6QDL_CLK_CKO>;
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VDDA-supply = <®_2p5v>;
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@ -158,7 +158,7 @@
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&mmc1 {
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interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins &mmc1_cd>;
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pinctrl-0 = <&mmc1_pins>;
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wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */
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cd-gpios = <&gpio4 14 IRQ_TYPE_LEVEL_LOW>; /* gpio_110 */
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vmmc-supply = <&vmmc1>;
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@ -193,7 +193,8 @@
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OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
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OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
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OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
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OMAP3_CORE1_IOPAD(0x2132, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_strobe.gpio_126 sdmmc1_wp*/
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OMAP3_CORE1_IOPAD(0x2132, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_strobe.gpio_126 */
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OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d11.gpio_110 */
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>;
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};
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@ -242,12 +243,6 @@
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OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* sys_boot6.gpio_8 */
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>;
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};
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mmc1_cd: pinmux_mmc1_cd {
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pinctrl-single,pins = <
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OMAP3_WKUP_IOPAD(0x212c, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d11.gpio_110 */
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>;
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};
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};
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@ -988,6 +988,7 @@
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phy-names = "sata-phy";
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clocks = <&sata_ref_clk>;
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ti,hwmods = "sata";
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ports-implemented = <0x1>;
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};
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dss: dss@58000000 {
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@ -357,7 +357,7 @@
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};
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amba {
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compatible = "arm,amba-bus";
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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@ -140,6 +140,10 @@
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cpu-supply = <®_dcdc3>;
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};
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&de {
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status = "okay";
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};
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&ehci0 {
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status = "okay";
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};
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@ -234,6 +234,7 @@
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de: display-engine {
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compatible = "allwinner,sun6i-a31-display-engine";
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allwinner,pipelines = <&fe0>;
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status = "disabled";
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};
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soc@01c00000 {
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@ -56,7 +56,7 @@
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};
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&pio {
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mmc2_pins_nrst: mmc2@0 {
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mmc2_pins_nrst: mmc2-rst-pin {
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allwinner,pins = "PC16";
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allwinner,function = "gpio_out";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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@ -137,6 +137,10 @@
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};
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};
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&scpi_clocks {
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status = "disabled";
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};
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&uart_AO {
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status = "okay";
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pinctrl-0 = <&uart_ao_a_pins>;
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@ -55,7 +55,7 @@
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mboxes = <&mailbox 1 &mailbox 2>;
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shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
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clocks {
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scpi_clocks: clocks {
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compatible = "arm,scpi-clocks";
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scpi_dvfs: scpi_clocks@0 {
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@ -1367,7 +1367,7 @@
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};
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amba {
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compatible = "arm,amba-bus";
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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@ -27,7 +27,7 @@
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stdout-path = "serial0:115200n8";
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};
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memory {
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x40000000>;
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};
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@ -72,7 +72,7 @@
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<1 10 0xf08>;
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};
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amba_apu {
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amba_apu: amba_apu@0 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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|
@ -175,7 +175,7 @@
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};
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i2c0: i2c@ff020000 {
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compatible = "cdns,i2c-r1p10";
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compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 17 4>;
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|
@ -185,7 +185,7 @@
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|||
};
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i2c1: i2c@ff030000 {
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compatible = "cdns,i2c-r1p10";
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compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
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status = "disabled";
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interrupt-parent = <&gic>;
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||||
interrupts = <0 18 4>;
|
||||
|
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