ARM: imx6: update base DTs
Upgrade to linux-next version. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
parent
6267173673
commit
a2d6081c56
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@ -8,6 +8,7 @@
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*
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "imx6dl-pinfunc.h"
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#include "imx6qdl-pingrp.h"
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#include "imx6qdl.dtsi"
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@ -22,6 +23,26 @@
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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operating-points = <
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/* kHz uV */
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996000 1275000
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792000 1175000
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396000 1075000
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>;
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fsl,soc-operating-points = <
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/* ARM kHz SOC-PU uV */
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996000 1175000
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792000 1175000
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396000 1175000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clks 104>, <&clks 6>, <&clks 16>,
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<&clks 17>, <&clks 170>;
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clock-names = "arm", "pll2_pfd2_396m", "step",
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"pll1_sw", "pll1_sys";
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arm-supply = <®_arm>;
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pu-supply = <®_pu>;
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soc-supply = <®_soc>;
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};
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cpu@1 {
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@ -33,6 +54,12 @@
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};
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soc {
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ocram: sram@00900000 {
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compatible = "mmio-sram";
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reg = <0x00900000 0x20000>;
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clocks = <&clks 142>;
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};
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aips1: aips-bus@02000000 {
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iomuxc: iomuxc@020e0000 {
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compatible = "fsl,imx6dl-iomuxc";
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@ -40,17 +67,17 @@
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pxp: pxp@020f0000 {
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reg = <0x020f0000 0x4000>;
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interrupts = <0 98 0x04>;
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interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
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};
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epdc: epdc@020f4000 {
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reg = <0x020f4000 0x4000>;
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interrupts = <0 97 0x04>;
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interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
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};
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lcdif: lcdif@020f8000 {
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reg = <0x020f8000 0x4000>;
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interrupts = <0 39 0x04>;
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interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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@ -60,7 +87,7 @@
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#size-cells = <0>;
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compatible = "fsl,imx1-i2c";
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reg = <0x021f8000 0x4000>;
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interrupts = <0 35 0x04>;
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interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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};
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@ -216,7 +216,7 @@
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};
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};
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&ocotp1 {
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&ocotp {
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barebox,provide-mac-address = <&fec 0x620>;
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};
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@ -212,7 +212,7 @@
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};
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};
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&ocotp1 {
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&ocotp {
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barebox,provide-mac-address = <&fec 0x620>;
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};
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@ -8,6 +8,7 @@
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*
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "imx6q-pinfunc.h"
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#include "imx6qdl-pingrp.h"
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#include "imx6qdl.dtsi"
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@ -31,7 +32,14 @@
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1200000 1275000
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996000 1250000
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792000 1150000
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396000 950000
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396000 975000
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>;
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fsl,soc-operating-points = <
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/* ARM kHz SOC-PU uV */
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1200000 1275000
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996000 1250000
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792000 1175000
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396000 1175000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clks 104>, <&clks 6>, <&clks 16>,
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};
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soc {
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ocram: sram@00900000 {
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compatible = "mmio-sram";
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reg = <0x00900000 0x40000>;
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clocks = <&clks 142>;
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};
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aips-bus@02000000 { /* AIPS1 */
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spba-bus@02000000 {
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ecspi5: ecspi@02018000 {
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@ -73,7 +87,7 @@
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#size-cells = <0>;
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compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
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reg = <0x02018000 0x4000>;
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interrupts = <0 35 0x04>;
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interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks 116>, <&clks 116>;
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clock-names = "ipg", "per";
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status = "disabled";
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@ -82,14 +96,60 @@
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iomuxc: iomuxc@020e0000 {
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compatible = "fsl,imx6q-iomuxc";
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ipu2 {
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pinctrl_ipu2_1: ipu2grp-1 {
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fsl,pins = <
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MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
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MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10
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MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10
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MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10
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MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000
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MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10
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MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10
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MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10
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MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10
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MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10
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MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10
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MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10
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MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10
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MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10
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MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10
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MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10
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MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10
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MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10
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MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10
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MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10
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MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10
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MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10
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MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10
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MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10
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MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10
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MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10
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MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10
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MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10
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MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10
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>;
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};
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};
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};
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};
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sata: sata@02200000 {
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compatible = "fsl,imx6q-ahci";
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reg = <0x02200000 0x4000>;
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interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks 154>, <&clks 187>, <&clks 105>;
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clock-names = "sata", "sata_ref", "ahb";
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status = "disabled";
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};
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ipu2: ipu@02800000 {
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#crtc-cells = <1>;
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compatible = "fsl,imx6q-ipu";
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reg = <0x02800000 0x400000>;
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interrupts = <0 8 0x4 0 7 0x4>;
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interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
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<0 7 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks 133>, <&clks 134>, <&clks 137>;
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clock-names = "bus", "di0", "di1";
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resets = <&src 4>;
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};
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};
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&ocotp1 {
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&ocotp {
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barebox,provide-mac-address = <&fec 0x620>;
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};
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};
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};
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&ocotp1 {
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&ocotp {
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barebox,provide-mac-address = <&fec 0x620>;
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};
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};
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};
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&ocotp1 {
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&ocotp {
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barebox,provide-mac-address = <&fec 0x620>;
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};
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@ -14,11 +14,8 @@
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/ {
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aliases {
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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can0 = &can1;
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can1 = &can2;
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio4 = &gpio5;
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gpio5 = &gpio6;
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gpio6 = &gpio7;
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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mmc2 = &usdhc3;
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mmc3 = &usdhc4;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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spi0 = &ecspi1;
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spi1 = &ecspi2;
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spi2 = &ecspi3;
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spi3 = &ecspi4;
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usbphy0 = &usbphy1;
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usbphy1 = &usbphy2;
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};
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intc: interrupt-controller@00a01000 {
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dma_apbh: dma-apbh@00110000 {
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compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
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reg = <0x00110000 0x2000>;
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interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
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interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 13 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
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#dma-cells = <1>;
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dma-channels = <4>;
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#size-cells = <1>;
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reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
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reg-names = "gpmi-nand", "bch";
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interrupts = <0 13 0x04>, <0 15 0x04>;
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interrupt-names = "gpmi-dma", "bch";
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interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "bch";
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clocks = <&clks 152>, <&clks 153>, <&clks 151>,
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<&clks 150>, <&clks 149>;
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clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
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"gpmi_bch_apb", "per1_bch";
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dmas = <&dma_apbh 0>;
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dma-names = "rx-tx";
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fsl,gpmi-dma-channel = <0>;
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status = "disabled";
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};
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L2: l2-cache@00a02000 {
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compatible = "arm,pl310-cache";
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reg = <0x00a02000 0x1000>;
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interrupts = <0 92 0x04>;
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interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
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cache-unified;
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cache-level = <2>;
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arm,tag-latency = <4 2 3>;
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arm,data-latency = <4 2 3>;
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};
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pcie: pcie@0x01000000 {
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compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
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reg = <0x01ffc000 0x4000>; /* DBI */
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
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0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
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num-lanes = <1>;
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interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
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clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
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status = "disabled";
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <0 94 0x04>;
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interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
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};
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aips-bus@02000000 { /* AIPS1 */
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ranges;
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spdif: spdif@02004000 {
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compatible = "fsl,imx35-spdif";
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reg = <0x02004000 0x4000>;
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interrupts = <0 52 0x04>;
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interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&sdma 14 18 0>,
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<&sdma 15 18 0>;
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dma-names = "rx", "tx";
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clocks = <&clks 197>, <&clks 3>,
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<&clks 197>, <&clks 107>,
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<&clks 0>, <&clks 118>,
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<&clks 0>, <&clks 139>,
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<&clks 0>;
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clock-names = "core", "rxtx0",
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"rxtx1", "rxtx2",
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"rxtx3", "rxtx4",
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"rxtx5", "rxtx6",
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"rxtx7";
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status = "disabled";
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};
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ecspi1: ecspi@02008000 {
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#size-cells = <0>;
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compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
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reg = <0x02008000 0x4000>;
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interrupts = <0 31 0x04>;
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interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks 112>, <&clks 112>;
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clock-names = "ipg", "per";
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status = "disabled";
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#size-cells = <0>;
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compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
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reg = <0x0200c000 0x4000>;
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interrupts = <0 32 0x04>;
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interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks 113>, <&clks 113>;
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clock-names = "ipg", "per";
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status = "disabled";
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#size-cells = <0>;
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compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
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reg = <0x02010000 0x4000>;
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interrupts = <0 33 0x04>;
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interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks 114>, <&clks 114>;
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clock-names = "ipg", "per";
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status = "disabled";
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#size-cells = <0>;
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compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
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reg = <0x02014000 0x4000>;
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interrupts = <0 34 0x04>;
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interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks 115>, <&clks 115>;
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clock-names = "ipg", "per";
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status = "disabled";
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uart1: serial@02020000 {
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compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
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reg = <0x02020000 0x4000>;
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interrupts = <0 26 0x04>;
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interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks 160>, <&clks 161>;
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clock-names = "ipg", "per";
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dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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esai: esai@02024000 {
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reg = <0x02024000 0x4000>;
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interrupts = <0 51 0x04>;
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interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
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};
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ssi1: ssi@02028000 {
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compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
|
||||
reg = <0x02028000 0x4000>;
|
||||
interrupts = <0 46 0x04>;
|
||||
interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 178>;
|
||||
dmas = <&sdma 37 1 0>,
|
||||
<&sdma 38 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <38 37>;
|
||||
status = "disabled";
|
||||
|
@ -211,8 +258,11 @@
|
|||
ssi2: ssi@0202c000 {
|
||||
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
|
||||
reg = <0x0202c000 0x4000>;
|
||||
interrupts = <0 47 0x04>;
|
||||
interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 179>;
|
||||
dmas = <&sdma 41 1 0>,
|
||||
<&sdma 42 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <42 41>;
|
||||
status = "disabled";
|
||||
|
@ -221,8 +271,11 @@
|
|||
ssi3: ssi@02030000 {
|
||||
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
|
||||
reg = <0x02030000 0x4000>;
|
||||
interrupts = <0 48 0x04>;
|
||||
interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 180>;
|
||||
dmas = <&sdma 45 1 0>,
|
||||
<&sdma 46 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <46 45>;
|
||||
status = "disabled";
|
||||
|
@ -230,7 +283,7 @@
|
|||
|
||||
asrc: asrc@02034000 {
|
||||
reg = <0x02034000 0x4000>;
|
||||
interrupts = <0 50 0x04>;
|
||||
interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spba@0203c000 {
|
||||
|
@ -240,7 +293,8 @@
|
|||
|
||||
vpu: vpu@02040000 {
|
||||
reg = <0x02040000 0x3c000>;
|
||||
interrupts = <0 3 0x04 0 12 0x04>;
|
||||
interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
aipstz@0207c000 { /* AIPSTZ1 */
|
||||
|
@ -251,7 +305,7 @@
|
|||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x02080000 0x4000>;
|
||||
interrupts = <0 83 0x04>;
|
||||
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 62>, <&clks 145>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
@ -260,7 +314,7 @@
|
|||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x02084000 0x4000>;
|
||||
interrupts = <0 84 0x04>;
|
||||
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 62>, <&clks 146>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
@ -269,7 +323,7 @@
|
|||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x02088000 0x4000>;
|
||||
interrupts = <0 85 0x04>;
|
||||
interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 62>, <&clks 147>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
@ -278,25 +332,33 @@
|
|||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x0208c000 0x4000>;
|
||||
interrupts = <0 86 0x04>;
|
||||
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 62>, <&clks 148>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
can1: flexcan@02090000 {
|
||||
compatible = "fsl,imx6q-flexcan";
|
||||
reg = <0x02090000 0x4000>;
|
||||
interrupts = <0 110 0x04>;
|
||||
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 108>, <&clks 109>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can2: flexcan@02094000 {
|
||||
compatible = "fsl,imx6q-flexcan";
|
||||
reg = <0x02094000 0x4000>;
|
||||
interrupts = <0 111 0x04>;
|
||||
interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 110>, <&clks 111>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpt: gpt@02098000 {
|
||||
compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
|
||||
reg = <0x02098000 0x4000>;
|
||||
interrupts = <0 55 0x04>;
|
||||
interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 119>, <&clks 120>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
@ -304,7 +366,8 @@
|
|||
gpio1: gpio@0209c000 {
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x0209c000 0x4000>;
|
||||
interrupts = <0 66 0x04 0 67 0x04>;
|
||||
interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
|
@ -314,7 +377,8 @@
|
|||
gpio2: gpio@020a0000 {
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x020a0000 0x4000>;
|
||||
interrupts = <0 68 0x04 0 69 0x04>;
|
||||
interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
|
@ -324,7 +388,8 @@
|
|||
gpio3: gpio@020a4000 {
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x020a4000 0x4000>;
|
||||
interrupts = <0 70 0x04 0 71 0x04>;
|
||||
interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
|
@ -334,7 +399,8 @@
|
|||
gpio4: gpio@020a8000 {
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x020a8000 0x4000>;
|
||||
interrupts = <0 72 0x04 0 73 0x04>;
|
||||
interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
|
@ -344,7 +410,8 @@
|
|||
gpio5: gpio@020ac000 {
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x020ac000 0x4000>;
|
||||
interrupts = <0 74 0x04 0 75 0x04>;
|
||||
interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
|
@ -354,7 +421,8 @@
|
|||
gpio6: gpio@020b0000 {
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x020b0000 0x4000>;
|
||||
interrupts = <0 76 0x04 0 77 0x04>;
|
||||
interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
|
@ -364,7 +432,8 @@
|
|||
gpio7: gpio@020b4000 {
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x020b4000 0x4000>;
|
||||
interrupts = <0 78 0x04 0 79 0x04>;
|
||||
interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
|
@ -373,20 +442,20 @@
|
|||
|
||||
kpp: kpp@020b8000 {
|
||||
reg = <0x020b8000 0x4000>;
|
||||
interrupts = <0 82 0x04>;
|
||||
interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
wdog1: wdog@020bc000 {
|
||||
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x020bc000 0x4000>;
|
||||
interrupts = <0 80 0x04>;
|
||||
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 0>;
|
||||
};
|
||||
|
||||
wdog2: wdog@020c0000 {
|
||||
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x020c0000 0x4000>;
|
||||
interrupts = <0 81 0x04>;
|
||||
interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -394,14 +463,17 @@
|
|||
clks: ccm@020c4000 {
|
||||
compatible = "fsl,imx6q-ccm";
|
||||
reg = <0x020c4000 0x4000>;
|
||||
interrupts = <0 87 0x04 0 88 0x04>;
|
||||
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 88 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
anatop: anatop@020c8000 {
|
||||
compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
|
||||
reg = <0x020c8000 0x1000>;
|
||||
interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
|
||||
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
regulator-1p1@110 {
|
||||
compatible = "fsl,anatop-regulator";
|
||||
|
@ -447,7 +519,7 @@
|
|||
|
||||
reg_arm: regulator-vddcore@140 {
|
||||
compatible = "fsl,anatop-regulator";
|
||||
regulator-name = "cpu";
|
||||
regulator-name = "vddarm";
|
||||
regulator-min-microvolt = <725000>;
|
||||
regulator-max-microvolt = <1450000>;
|
||||
regulator-always-on;
|
||||
|
@ -497,18 +569,28 @@
|
|||
};
|
||||
};
|
||||
|
||||
tempmon: tempmon {
|
||||
compatible = "fsl,imx6q-tempmon";
|
||||
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
fsl,tempmon = <&anatop>;
|
||||
fsl,tempmon-data = <&ocotp>;
|
||||
clocks = <&clks 172>;
|
||||
};
|
||||
|
||||
usbphy1: usbphy@020c9000 {
|
||||
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
|
||||
reg = <0x020c9000 0x1000>;
|
||||
interrupts = <0 44 0x04>;
|
||||
interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 182>;
|
||||
fsl,anatop = <&anatop>;
|
||||
};
|
||||
|
||||
usbphy2: usbphy@020ca000 {
|
||||
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
|
||||
reg = <0x020ca000 0x1000>;
|
||||
interrupts = <0 45 0x04>;
|
||||
interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 183>;
|
||||
fsl,anatop = <&anatop>;
|
||||
};
|
||||
|
||||
snvs@020cc000 {
|
||||
|
@ -520,31 +602,34 @@
|
|||
snvs-rtc-lp@34 {
|
||||
compatible = "fsl,sec-v4.0-mon-rtc-lp";
|
||||
reg = <0x34 0x58>;
|
||||
interrupts = <0 19 0x04 0 20 0x04>;
|
||||
interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
epit1: epit@020d0000 { /* EPIT1 */
|
||||
reg = <0x020d0000 0x4000>;
|
||||
interrupts = <0 56 0x04>;
|
||||
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
epit2: epit@020d4000 { /* EPIT2 */
|
||||
reg = <0x020d4000 0x4000>;
|
||||
interrupts = <0 57 0x04>;
|
||||
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
src: src@020d8000 {
|
||||
compatible = "fsl,imx6q-src", "fsl,imx51-src";
|
||||
reg = <0x020d8000 0x4000>;
|
||||
interrupts = <0 91 0x04 0 96 0x04>;
|
||||
interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
gpc: gpc@020dc000 {
|
||||
compatible = "fsl,imx6q-gpc";
|
||||
reg = <0x020dc000 0x4000>;
|
||||
interrupts = <0 89 0x04 0 90 0x04>;
|
||||
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 90 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpr: iomuxc-gpr@020e0000 {
|
||||
|
@ -566,33 +651,32 @@
|
|||
|
||||
lvds-channel@0 {
|
||||
reg = <0>;
|
||||
crtcs = <&ipu1 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lvds-channel@1 {
|
||||
reg = <1>;
|
||||
crtcs = <&ipu1 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
dcic1: dcic@020e4000 {
|
||||
reg = <0x020e4000 0x4000>;
|
||||
interrupts = <0 124 0x04>;
|
||||
interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
dcic2: dcic@020e8000 {
|
||||
reg = <0x020e8000 0x4000>;
|
||||
interrupts = <0 125 0x04>;
|
||||
interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sdma: sdma@020ec000 {
|
||||
compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
|
||||
reg = <0x020ec000 0x4000>;
|
||||
interrupts = <0 2 0x04>;
|
||||
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 155>, <&clks 155>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
|
||||
};
|
||||
};
|
||||
|
@ -606,7 +690,8 @@
|
|||
|
||||
caam@02100000 {
|
||||
reg = <0x02100000 0x40000>;
|
||||
interrupts = <0 105 0x04 0 106 0x04>;
|
||||
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
aipstz@0217c000 { /* AIPSTZ2 */
|
||||
|
@ -616,7 +701,7 @@
|
|||
usbotg: usb@02184000 {
|
||||
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
||||
reg = <0x02184000 0x200>;
|
||||
interrupts = <0 43 0x04>;
|
||||
interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 162>;
|
||||
fsl,usbphy = <&usbphy1>;
|
||||
fsl,usbmisc = <&usbmisc 0>;
|
||||
|
@ -626,7 +711,7 @@
|
|||
usbh1: usb@02184200 {
|
||||
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
||||
reg = <0x02184200 0x200>;
|
||||
interrupts = <0 40 0x04>;
|
||||
interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 162>;
|
||||
fsl,usbphy = <&usbphy2>;
|
||||
fsl,usbmisc = <&usbmisc 1>;
|
||||
|
@ -636,7 +721,7 @@
|
|||
usbh2: usb@02184400 {
|
||||
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
||||
reg = <0x02184400 0x200>;
|
||||
interrupts = <0 41 0x04>;
|
||||
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 162>;
|
||||
fsl,usbmisc = <&usbmisc 2>;
|
||||
status = "disabled";
|
||||
|
@ -645,7 +730,7 @@
|
|||
usbh3: usb@02184600 {
|
||||
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
||||
reg = <0x02184600 0x200>;
|
||||
interrupts = <0 42 0x04>;
|
||||
interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 162>;
|
||||
fsl,usbmisc = <&usbmisc 3>;
|
||||
status = "disabled";
|
||||
|
@ -661,7 +746,9 @@
|
|||
fec: ethernet@02188000 {
|
||||
compatible = "fsl,imx6q-fec";
|
||||
reg = <0x02188000 0x4000>;
|
||||
interrupts = <0 118 0x04 0 119 0x04>;
|
||||
interrupts-extended =
|
||||
<&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 117>, <&clks 117>, <&clks 190>;
|
||||
clock-names = "ipg", "ahb", "ptp";
|
||||
status = "disabled";
|
||||
|
@ -669,13 +756,15 @@
|
|||
|
||||
mlb@0218c000 {
|
||||
reg = <0x0218c000 0x4000>;
|
||||
interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
|
||||
interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 117 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 126 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
usdhc1: usdhc@02190000 {
|
||||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x02190000 0x4000>;
|
||||
interrupts = <0 22 0x04>;
|
||||
interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 163>, <&clks 163>, <&clks 163>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
|
@ -685,7 +774,7 @@
|
|||
usdhc2: usdhc@02194000 {
|
||||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x02194000 0x4000>;
|
||||
interrupts = <0 23 0x04>;
|
||||
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 164>, <&clks 164>, <&clks 164>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
|
@ -695,7 +784,7 @@
|
|||
usdhc3: usdhc@02198000 {
|
||||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x02198000 0x4000>;
|
||||
interrupts = <0 24 0x04>;
|
||||
interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 165>, <&clks 165>, <&clks 165>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
|
@ -705,7 +794,7 @@
|
|||
usdhc4: usdhc@0219c000 {
|
||||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x0219c000 0x4000>;
|
||||
interrupts = <0 25 0x04>;
|
||||
interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 166>, <&clks 166>, <&clks 166>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
|
@ -717,7 +806,7 @@
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x021a0000 0x4000>;
|
||||
interrupts = <0 36 0x04>;
|
||||
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 125>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -727,7 +816,7 @@
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x021a4000 0x4000>;
|
||||
interrupts = <0 37 0x04>;
|
||||
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 126>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -737,7 +826,7 @@
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x021a8000 0x4000>;
|
||||
interrupts = <0 38 0x04>;
|
||||
interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 127>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -755,29 +844,26 @@
|
|||
reg = <0x021b4000 0x4000>;
|
||||
};
|
||||
|
||||
weim@021b8000 {
|
||||
weim: weim@021b8000 {
|
||||
compatible = "fsl,imx6q-weim";
|
||||
reg = <0x021b8000 0x4000>;
|
||||
interrupts = <0 14 0x04>;
|
||||
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 196>;
|
||||
};
|
||||
|
||||
ocotp1: ocotp@021bc000 {
|
||||
compatible = "fsl,imx6q-ocotp";
|
||||
ocotp: ocotp@021bc000 {
|
||||
compatible = "fsl,imx6q-ocotp", "syscon";
|
||||
reg = <0x021bc000 0x4000>;
|
||||
};
|
||||
|
||||
ocotp2: ocotp@021c0000 {
|
||||
reg = <0x021c0000 0x4000>;
|
||||
interrupts = <0 21 0x04>;
|
||||
};
|
||||
|
||||
tzasc@021d0000 { /* TZASC1 */
|
||||
reg = <0x021d0000 0x4000>;
|
||||
interrupts = <0 108 0x04>;
|
||||
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
tzasc@021d4000 { /* TZASC2 */
|
||||
reg = <0x021d4000 0x4000>;
|
||||
interrupts = <0 109 0x04>;
|
||||
interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
audmux: audmux@021d8000 {
|
||||
|
@ -786,7 +872,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
mipi@021dc000 { /* MIPI-CSI */
|
||||
mipi_csi: mipi@021dc000 {
|
||||
reg = <0x021dc000 0x4000>;
|
||||
};
|
||||
|
||||
|
@ -796,61 +882,60 @@
|
|||
|
||||
vdoa@021e4000 {
|
||||
reg = <0x021e4000 0x4000>;
|
||||
interrupts = <0 18 0x04>;
|
||||
interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart2: serial@021e8000 {
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021e8000 0x4000>;
|
||||
interrupts = <0 27 0x04>;
|
||||
interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@021ec000 {
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021ec000 0x4000>;
|
||||
interrupts = <0 28 0x04>;
|
||||
interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@021f0000 {
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021f0000 0x4000>;
|
||||
interrupts = <0 29 0x04>;
|
||||
interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@021f4000 {
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021f4000 0x4000>;
|
||||
interrupts = <0 30 0x04>;
|
||||
interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
sata: sata@02200000 {
|
||||
compatible = "fsl,imx6q-ahci";
|
||||
reg = <0x02200000 0x4000>;
|
||||
interrupts = <0 39 0x04>;
|
||||
clocks = <&clks 154 &clks 105 &clks 187>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
gprreg = <&gpr>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipu1: ipu@02400000 {
|
||||
#crtc-cells = <1>;
|
||||
compatible = "fsl,imx6q-ipu";
|
||||
reg = <0x02400000 0x400000>;
|
||||
interrupts = <0 6 0x4 0 5 0x4>;
|
||||
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 130>, <&clks 131>, <&clks 132>;
|
||||
clock-names = "bus", "di0", "di1";
|
||||
resets = <&src 2>;
|
||||
|
|
Loading…
Reference in New Issue