scb9328: Move all not critical register initializations
like chipselect setups from assembler to C.
This commit is contained in:
sascha
parent
7f72d26be9
commit
a3408cfe75
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@ -21,47 +21,21 @@
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#include <config.h>
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#include <asm/arch/imx-regs.h>
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#define CFG_GPR_A_VAL 0x00800000
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#define CFG_GIUS_A_VAL 0x0043fffe
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#define writel(val, reg) \
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ldr r0, =reg; \
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ldr r1, =val; \
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str r1, [r0];
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#define CFG_CS0U_VAL 0x000F2000
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#define CFG_CS0L_VAL 0x11110d01
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#define CFG_CS1U_VAL 0x000F0a00
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#define CFG_CS1L_VAL 0x11110601
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#define CFG_CS2U_VAL 0x0
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#define CFG_CS2L_VAL 0x0
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#define CFG_CS3U_VAL 0x000FFFFF
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#define CFG_CS3L_VAL 0x00000303
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#define CFG_CS4U_VAL 0x000F0a00
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#define CFG_CS4L_VAL 0x11110301
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#define CFG_CS5U_VAL 0x00008400
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#define CFG_CS5L_VAL 0x00000D03
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/* SDRAM Setup Values
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* 0x910a8300 Precharge Command CAS 3
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* 0x910a8200 Precharge Command CAS 2
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*
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* 0xa10a8300 AutoRefresh Command CAS 3
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* 0xa10a8200 Set AutoRefresh Command CAS 2
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*/
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#define PRECHARGE_CMD 0x910a8200
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#define AUTOREFRESH_CMD 0xa10a8200
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.globl lowlevel_init
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lowlevel_init:
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.globl board_init_lowlevel
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board_init_lowlevel:
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mov r10, lr
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/* Change PERCLK1DIV to 14 ie 14+1 */
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ldr r0, =PCDR
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ldr r1, =CFG_PCDR_VAL
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str r1, [r0]
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writel(CFG_PCDR_VAL, PCDR)
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/* set MCU PLL Control Register 0 */
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ldr r0, =MPCTL0
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ldr r1, =CFG_MPCTL0_VAL
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str r1, [r0]
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writel(CFG_MPCTL0_VAL, MPCTL0)
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/* set mpll restart bit */
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ldr r0, =CSCR
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@ -80,10 +54,7 @@ lowlevel_init:
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bne 1b
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/* set System PLL Control Register 0 */
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ldr r0, =SPCTL0
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ldr r1, =CFG_SPCTL0_VAL
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str r1, [r0]
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writel(CFG_SPCTL0_VAL, SPCTL0)
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/* set spll restart bit */
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ldr r0, =CSCR
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@ -101,9 +72,7 @@ lowlevel_init:
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subs r2,r2,#1
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bne 1b
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ldr r0, =CSCR
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ldr r1, =CFG_CSCR_VAL
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str r1, [r0]
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writel(CFG_CSCR_VAL, CSCR)
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/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
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*this.....
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@ -126,81 +95,21 @@ lowlevel_init:
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ORR r0,r0,#0xC0000000
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MCR p15,0,r0,c1,c0,0
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ldr r0, =GPR(0)
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ldr r1, =CFG_GPR_A_VAL
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str r1, [r0]
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/* Skip SDRAM initialization if we run from RAM */
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cmp pc, #0x08000000
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bls 1f
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cmp pc, #0x09000000
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bhi 1f
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ldr r0, =GIUS(0)
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ldr r1, =CFG_GIUS_A_VAL
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str r1, [r0]
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mov pc,r10
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/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
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ldr r0, =FMCR
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ldr r1, =CFG_FMCR_VAL
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str r1, [r0]
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ldr r0, =CS0U
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ldr r1, =CFG_CS0U_VAL
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str r1, [r0]
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ldr r0, =CS0L
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ldr r1, =CFG_CS0L_VAL
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str r1, [r0]
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ldr r0, =CS1U
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ldr r1, =CFG_CS1U_VAL
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str r1, [r0]
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ldr r0, =CS1L
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ldr r1, =CFG_CS1L_VAL
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str r1, [r0]
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ldr r0, =CS2U
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ldr r1, =CFG_CS2U_VAL
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str r1, [r0]
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ldr r0, =CS2L
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ldr r1, =CFG_CS2L_VAL
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str r1, [r0]
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ldr r0, =CS3U
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ldr r1, =CFG_CS3U_VAL
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str r1, [r0]
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ldr r0, =CS3L
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ldr r1, =CFG_CS3L_VAL
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str r1, [r0]
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ldr r0, =CS4U
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ldr r1, =CFG_CS4U_VAL
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str r1, [r0]
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ldr r0, =CS4L
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ldr r1, =CFG_CS4L_VAL
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str r1, [r0]
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ldr r0, =CS5U
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ldr r1, =CFG_CS5U_VAL
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str r1, [r0]
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ldr r0, =CS5L
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ldr r1, =CFG_CS5L_VAL
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str r1, [r0]
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1:
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/* SDRAM Setup */
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ldr r0, =SDCTL0
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ldr r1, =PRECHARGE_CMD
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str r1, [r0]
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ldr r0, =0x08200000
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ldr r1, =0x0 /* Issue Precharge all Command */
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str r1, [r0]
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ldr r0, =SDCTL0
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ldr r1, =AUTOREFRESH_CMD
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str r1, [r0]
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writel(0x910a8200, SDCTL0) /* Precharge cmd, CAS = 2 */
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writel(0x0, 0x08200000) /* Issue Precharge all Command */
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writel(0xa10a8200, SDCTL0) /* Autorefresh cmd, CAS = 2 */
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ldr r0, =0x08000000
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ldr r1, =0x0 /* Issue AutoRefresh Command */
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@ -213,16 +122,8 @@ lowlevel_init:
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str r1, [r0]
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str r1, [r0]
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ldr r0, =SDCTL0
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ldr r1, =0xb10a8300
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str r1, [r0]
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ldr r0, =0x08223000 /* CAS Latency 2 */
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ldr r1, =0x0 /* Issue Mode Register Command, Burst Length = 8 */
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str r1, [r0]
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ldr r0, =SDCTL0
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ldr r1, =0x810a8200 /* Set to Normal Mode CAS 2 */
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str r1, [r0]
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writel(0xb10a8300, SDCTL0)
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writel(0x0, 0x08223000) /* CAS Latency 2, issue Mode Register Command, Burst Length = 8 */
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writel(0x810a8200, SDCTL0) /* Set to Normal Mode CAS 2 */
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mov pc,r10
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@ -25,6 +25,7 @@
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#include <environment.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/gpio.h>
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#include <asm/io.h>
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#include <partition.h>
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#include <fs.h>
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#include <fcntl.h>
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@ -55,6 +56,28 @@ static struct device_d dm9000_dev = {
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};
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static int scb9328_devices_init(void) {
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/* adjust chipselects */
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GPR(0) = 0x00800000;
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GIUS(0) = 0x0043fffe;
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/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
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FMCR = 0x1;
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CS0U = 0x000F2000;
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CS0L = 0x11110d01;
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CS1U = 0x000F0a00;
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CS1L = 0x11110601;
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CS2U = 0x0;
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CS2L = 0x0;
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CS3U = 0x000FFFFF;
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CS3L = 0x00000303;
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CS4U = 0x000F0a00;
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CS4L = 0x11110301;
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CS5U = 0x00008400;
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CS5L = 0x00000D03;
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register_device(&cfi_dev);
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register_device(&sdram_dev);
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register_device(&dm9000_dev);
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