From 458f5083d6e79c7dfc091da4078552f39867e40d Mon Sep 17 00:00:00 2001 From: Jan Luebbe Date: Wed, 5 Sep 2012 17:52:09 +0200 Subject: [PATCH 1/4] drivers/nor/m25p80: add JEDEC ID for Micron/Numonyx SPI NOR flash Signed-off-by: Jan Luebbe Signed-off-by: Sascha Hauer --- drivers/nor/m25p80.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/nor/m25p80.c b/drivers/nor/m25p80.c index 5713ad58f..61f219505 100644 --- a/drivers/nor/m25p80.c +++ b/drivers/nor/m25p80.c @@ -648,6 +648,9 @@ static const struct spi_device_id m25p_ids[] = { { "cat25c09", CAT25_INFO( 128, 8, 32, 2) }, { "cat25c17", CAT25_INFO( 256, 8, 32, 2) }, { "cat25128", CAT25_INFO(2048, 8, 64, 2) }, + + /* Micron */ + { "n25q128", INFO(0x20ba18, 0, 64 * 1024, 256, 0) }, { }, }; From 68bc34d416ceffaa11be0ac096e87ffdfb482081 Mon Sep 17 00:00:00 2001 From: Jan Luebbe Date: Mon, 10 Sep 2012 10:55:46 +0200 Subject: [PATCH 2/4] drivers/nor/m25p80: add MTD support This has been tested by using UBI with a N25Q128 connected to a TI McSPI controller. Signed-off-by: Jan Luebbe Signed-off-by: Sascha Hauer --- drivers/nor/m25p80.c | 71 ++++++++++++++++++++++++++++++++++++++++++++ drivers/nor/m25p80.h | 2 +- 2 files changed, 72 insertions(+), 1 deletion(-) diff --git a/drivers/nor/m25p80.c b/drivers/nor/m25p80.c index 61f219505..8775fa9a4 100644 --- a/drivers/nor/m25p80.c +++ b/drivers/nor/m25p80.c @@ -697,6 +697,74 @@ static struct file_operations m25p80_ops = { .lseek = dev_lseek_default, }; +static int m25p_mtd_read(struct mtd_info *mtd, loff_t from, size_t len, + size_t *retlen, u_char *buf) +{ + struct m25p *flash = container_of(mtd, struct m25p, mtd); + ssize_t ret; + + ret = flash->cdev.ops->read(&flash->cdev, buf, len, from, 0); + if (ret < 0) { + *retlen = 0; + return ret; + } + + *retlen = ret; + return 0; +} + +static int m25p_mtd_write(struct mtd_info *mtd, loff_t to, size_t len, + size_t *retlen, const u_char *buf) +{ + struct m25p *flash = container_of(mtd, struct m25p, mtd); + ssize_t ret; + + ret = flash->cdev.ops->write(&flash->cdev, buf, len, to, 0); + if (ret < 0) { + *retlen = 0; + return ret; + } + + *retlen = ret; + return 0; +} + +static int m25p_mtd_erase(struct mtd_info *mtd, struct erase_info *instr) +{ + struct m25p *flash = container_of(mtd, struct m25p, mtd); + ssize_t ret; + + ret = flash->cdev.ops->erase(&flash->cdev, instr->len, instr->addr); + + if (ret) { + instr->state = MTD_ERASE_FAILED; + return -EIO; + } + + instr->state = MTD_ERASE_DONE; + mtd_erase_callback(instr); + + return 0; +} + +static void m25p_init_mtd(struct m25p *flash) +{ + struct mtd_info *mtd = &flash->mtd; + + mtd->read = m25p_mtd_read; + mtd->write = m25p_mtd_write; + mtd->erase = m25p_mtd_erase; + mtd->size = flash->size; + mtd->name = flash->cdev.name; + mtd->erasesize = flash->erasesize; + mtd->writesize = 1; + mtd->subpage_sft = 0; + mtd->eraseregions = NULL; + mtd->numeraseregions = 0; + mtd->flags = MTD_CAP_NORFLASH; + flash->cdev.mtd = mtd; +} + /* * board specific setup should have ensured the SPI clock used here * matches what the READ command supports, at least until this driver @@ -828,6 +896,9 @@ static int m25p_probe(struct device_d *dev) dev_info(dev, "%s (%lld Kbytes)\n", id->name, (long long)flash->size >> 10); + if (IS_ENABLED(CONFIG_PARTITION_NEED_MTD)) + m25p_init_mtd(flash); + devfs_create(&flash->cdev); return 0; diff --git a/drivers/nor/m25p80.h b/drivers/nor/m25p80.h index 34bf2e259..957900e3a 100644 --- a/drivers/nor/m25p80.h +++ b/drivers/nor/m25p80.h @@ -46,7 +46,7 @@ struct spi_device_id { struct m25p { struct spi_device *spi; struct flash_info *info; - struct mtd_info mtd; + struct mtd_info mtd; struct cdev cdev; char *name; u32 erasesize; From aa577bfc6d3ac3a07d489fadc733036edef70c0c Mon Sep 17 00:00:00 2001 From: Jan Luebbe Date: Mon, 10 Sep 2012 10:55:47 +0200 Subject: [PATCH 3/4] drivers/nor/cfi_flash: use IS_ENABLED instead of an ifdef Signed-off-by: Jan Luebbe Signed-off-by: Sascha Hauer --- drivers/nor/cfi_flash.c | 8 +++----- drivers/nor/cfi_flash.h | 2 -- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/nor/cfi_flash.c b/drivers/nor/cfi_flash.c index 16885c0af..d9347b237 100644 --- a/drivers/nor/cfi_flash.c +++ b/drivers/nor/cfi_flash.c @@ -917,7 +917,6 @@ struct file_operations cfi_ops = { .memmap = generic_memmap_ro, }; -#ifdef CONFIG_PARTITION_NEED_MTD static int cfi_mtd_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) { @@ -977,7 +976,6 @@ static void cfi_init_mtd(struct flash_info *info) mtd->flags = MTD_CAP_NORFLASH; info->cdev.mtd = mtd; } -#endif static int cfi_probe (struct device_d *dev) { @@ -1006,9 +1004,9 @@ static int cfi_probe (struct device_d *dev) info->cdev.ops = &cfi_ops; info->cdev.priv = info; -#ifdef CONFIG_PARTITION_NEED_MTD - cfi_init_mtd(info); -#endif + if (IS_ENABLED(CONFIG_PARTITION_NEED_MTD)) + cfi_init_mtd(info); + devfs_create(&info->cdev); return 0; diff --git a/drivers/nor/cfi_flash.h b/drivers/nor/cfi_flash.h index fec08940a..1bfe81c38 100644 --- a/drivers/nor/cfi_flash.h +++ b/drivers/nor/cfi_flash.h @@ -75,9 +75,7 @@ struct flash_info { ulong addr_unlock2; /* unlock address 2 for AMD flash roms */ struct cfi_cmd_set *cfi_cmd_set; struct cdev cdev; -#ifdef CONFIG_PARTITION_NEED_MTD struct mtd_info mtd; -#endif int numeraseregions; struct mtd_erase_region_info *eraseregions; void *base; From 7d4d295d4ef5b6cddbe14003ae78098687904356 Mon Sep 17 00:00:00 2001 From: Marcus Folkesson Date: Sat, 15 Sep 2012 13:45:06 +0200 Subject: [PATCH 4/4] mtd: nand: extend NAND flash detection to new MLC chips Some of the newer MLC devices have a 6-byte ID sequence in which several field definitions differ from older chips in a manner that is not backward compatible. This method is already used in the Linux Kernel. Signed-off-by: Marcus Folkesson Signed-off-by: Sascha Hauer --- drivers/mtd/nand/nand_base.c | 97 +++++++++++++++++++++++++++++------- drivers/mtd/nand/nand_ids.c | 30 +++++++++++ 2 files changed, 108 insertions(+), 19 deletions(-) diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 37e57b32c..fe9a6e7ab 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -1137,7 +1137,7 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, { struct nand_flash_dev *type = NULL; int i, dev_id, maf_idx; - int tmp_id, tmp_manf; + int id_data[8]; int ret; /* Select the device */ @@ -1166,13 +1166,13 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, /* Read manufacturer and device IDs */ - tmp_manf = chip->read_byte(mtd); - tmp_id = chip->read_byte(mtd); + id_data[0] = chip->read_byte(mtd); + id_data[1] = chip->read_byte(mtd); - if (tmp_manf != *maf_id || tmp_id != dev_id) { + if (id_data[0] != *maf_id || id_data[1] != dev_id) { printk(KERN_ERR "%s: second ID read did not match " "%02x,%02x against %02x,%02x\n", __func__, - *maf_id, dev_id, tmp_manf, tmp_id); + *maf_id, dev_id, id_data[0], id_data[1]); return ERR_PTR(-ENODEV); } @@ -1196,29 +1196,75 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, } } + chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); + + /* Read entire ID string */ + + for (i = 0; i < 8; i++) + id_data[i] = chip->read_byte(mtd); + if (!mtd->name) mtd->name = type->name; chip->chipsize = type->chipsize << 20; - /* Newer devices have all the information in additional id bytes */ if (!type->pagesize) { int extid; /* The 3rd id byte holds MLC / multichip data */ - chip->cellinfo = chip->read_byte(mtd); + chip->cellinfo = id_data[2]; /* The 4th id byte is the important one */ - extid = chip->read_byte(mtd); - /* Calc pagesize */ - mtd->writesize = 1024 << (extid & 0x3); - extid >>= 2; - /* Calc oobsize */ - mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9); - extid >>= 2; - /* Calc blocksize. Blocksize is multiples of 64KiB */ - mtd->erasesize = (64 * 1024) << (extid & 0x03); - extid >>= 2; - /* Get buswidth information */ - busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; + extid = id_data[3]; + + /* + * Field definitions are in the following datasheets: + * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) + * New style (6 byte ID): Samsung K9GBG08U0M (p.40) + * + * Check for wraparound + Samsung ID + nonzero 6th byte + * to decide what to do. + */ + if (id_data[0] == id_data[6] && id_data[1] == id_data[7] && + id_data[0] == NAND_MFR_SAMSUNG && + (chip->cellinfo & NAND_CI_CELLTYPE_MSK) && + id_data[5] != 0x00) { + /* Calc pagesize */ + mtd->writesize = 2048 << (extid & 0x03); + extid >>= 2; + /* Calc oobsize */ + switch (extid & 0x03) { + case 1: + mtd->oobsize = 128; + break; + case 2: + mtd->oobsize = 218; + break; + case 3: + mtd->oobsize = 400; + break; + default: + mtd->oobsize = 436; + break; + } + extid >>= 2; + /* Calc blocksize */ + mtd->erasesize = (128 * 1024) << + (((extid >> 1) & 0x04) | (extid & 0x03)); + busw = 0; + } else { + /* Calc pagesize */ + mtd->writesize = 1024 << (extid & 0x03); + extid >>= 2; + /* Calc oobsize */ + mtd->oobsize = (8 << (extid & 0x01)) * + (mtd->writesize >> 9); + extid >>= 2; + /* Calc blocksize. Blocksize is multiples of 64KiB */ + mtd->erasesize = (64 * 1024) << (extid & 0x03); + extid >>= 2; + /* Get buswidth information */ + busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; + } + } else { /* @@ -1228,6 +1274,19 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, mtd->writesize = type->pagesize; mtd->oobsize = mtd->writesize / 32; busw = type->options & NAND_BUSWIDTH_16; + + /* + * Check for Spansion/AMD ID + repeating 5th, 6th byte since + * some Spansion chips have erasesize that conflicts with size + * listed in nand_ids table + * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) + */ + if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && + id_data[5] == 0x00 && id_data[6] == 0x00 && + id_data[7] == 0x00 && mtd->writesize == 512) { + mtd->erasesize = 128 * 1024; + mtd->erasesize <<= ((id_data[3] & 0x03) << 1); + } } /* Try to identify manufacturer */ diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index cb53fc61c..72593d44a 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c @@ -118,6 +118,36 @@ struct nand_flash_dev nand_flash_ids[] = { {__NANDSTR("NAND 2GiB 1,8V 16-bit"), 0xB5, 0, 2048, 0, LP_OPTIONS16}, {__NANDSTR("NAND 2GiB 3,3V 16-bit"), 0xC5, 0, 2048, 0, LP_OPTIONS16}, + /* 32 Gigabit */ + {__NANDSTR("NAND 4GiB 1,8V 8-bit"), 0xA7, 0, 4096, 0, LP_OPTIONS}, + {__NANDSTR("NAND 4GiB 3,3V 8-bit"), 0xD7, 0, 4096, 0, LP_OPTIONS}, + {__NANDSTR("NAND 4GiB 1,8V 16-bit"), 0xB7, 0, 4096, 0, LP_OPTIONS16}, + {__NANDSTR("NAND 4GiB 3,3V 16-bit"), 0xC7, 0, 4096, 0, LP_OPTIONS16}, + + /* 64 Gigabit */ + {__NANDSTR("NAND 8GiB 1,8V 8-bit"), 0xAE, 0, 8192, 0, LP_OPTIONS}, + {__NANDSTR("NAND 8GiB 3,3V 8-bit"), 0xDE, 0, 8192, 0, LP_OPTIONS}, + {__NANDSTR("NAND 8GiB 1,8V 16-bit"), 0xBE, 0, 8192, 0, LP_OPTIONS16}, + {__NANDSTR("NAND 8GiB 3,3V 16-bit"), 0xCE, 0, 8192, 0, LP_OPTIONS16}, + + /* 128 Gigabit */ + {__NANDSTR("NAND 16GiB 1,8V 8-bit"), 0x1A, 0, 16384, 0, LP_OPTIONS}, + {__NANDSTR("NAND 16GiB 3,3V 8-bit"), 0x3A, 0, 16384, 0, LP_OPTIONS}, + {__NANDSTR("NAND 16GiB 1,8V 16-bit"), 0x2A, 0, 16384, 0, LP_OPTIONS16}, + {__NANDSTR("NAND 16GiB 3,3V 16-bit"), 0x4A, 0, 16384, 0, LP_OPTIONS16}, + + /* 256 Gigabit */ + {__NANDSTR("NAND 32GiB 1,8V 8-bit"), 0x1C, 0, 32768, 0, LP_OPTIONS}, + {__NANDSTR("NAND 32GiB 3,3V 8-bit"), 0x3C, 0, 32768, 0, LP_OPTIONS}, + {__NANDSTR("NAND 32GiB 1,8V 16-bit"), 0x2C, 0, 32768, 0, LP_OPTIONS16}, + {__NANDSTR("NAND 32GiB 3,3V 16-bit"), 0x4C, 0, 32768, 0, LP_OPTIONS16}, + + /* 512 Gigabit */ + {__NANDSTR("NAND 64GiB 1,8V 8-bit"), 0x1E, 0, 65536, 0, LP_OPTIONS}, + {__NANDSTR("NAND 64GiB 3,3V 8-bit"), 0x3E, 0, 65536, 0, LP_OPTIONS}, + {__NANDSTR("NAND 64GiB 1,8V 16-bit"), 0x2E, 0, 65536, 0, LP_OPTIONS16}, + {__NANDSTR("NAND 64GiB 3,3V 16-bit"), 0x4E, 0, 65536, 0, LP_OPTIONS16}, + /* * Renesas AND 1 Gigabit. Those chips do not support extended id and * have a strange page/block layout ! The chosen minimum erasesize is