USB i.MX: Add chipidea driver support
For proper USB function the usbmisc registers have to be initialized. This patch adds a driver which matches for the usbmisc registers. This driver is called from a new driver which binds to the USB ports to configure the misc registers. After that the driver registers the EHCI driver and an ULPI transceiver if necessary. Currently only host mode is supported, but device support can be added later. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
15fd89d0a4
commit
a4076ddf65
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@ -3,6 +3,8 @@ menuconfig USB
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if USB
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source drivers/usb/imx/Kconfig
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source drivers/usb/host/Kconfig
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source drivers/usb/otg/Kconfig
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@ -1,4 +1,5 @@
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obj-$(CONFIG_USB) += core/
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obj-$(CONFIG_USB_IMX_CHIPIDEA) += imx/
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obj-$(CONFIG_USB_GADGET) += gadget/
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obj-$(CONFIG_USB_STORAGE) += storage/
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obj-y += host/
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@ -0,0 +1,15 @@
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config USB_IMX_CHIPIDEA
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bool "i.MX USB support (read help)"
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depends on ARCH_IMX
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help
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The Freescale i.MX SoCs have a variant of the chipidea ci13xxx for
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USB support. Traditionally in barebox this is supported through the
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EHCI driver for USB host and the ARC USB gadget driver for device.
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This option instead enables support for i.MX chipidea support which
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acts as a toplevel driver for the i.MX USB support. The chipidea
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support also configures the usbmisc registers which traditionally
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are configured in the board file.
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This driver is recommended for new designs, but it needs board
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support to work.
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It's safe to say yes here. Also select EHCI support for USB host.
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@ -0,0 +1 @@
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obj-$(CONFIG_USB_IMX_CHIPIDEA) += imx-usb-misc.o chipidea-imx.o
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@ -0,0 +1,91 @@
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/*
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* Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <driver.h>
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#include <usb/ehci.h>
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#include <usb/chipidea-imx.h>
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#include <usb/ulpi.h>
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#define MXC_EHCI_PORTSC_MASK (0xf << 28)
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static int imx_chipidea_probe(struct device_d *dev)
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{
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struct imxusb_platformdata *pdata = dev->platform_data;
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int ret;
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void __iomem *base;
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struct ehci_data data;
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uint32_t portsc;
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if (!pdata) {
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dev_err(dev, "no pdata!\n");
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return -EINVAL;
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}
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base = dev_request_mem_region(dev, 0);
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if (!base)
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return -ENODEV;
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portsc = readl(base + 0x184);
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portsc &= ~MXC_EHCI_PORTSC_MASK;
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portsc |= pdata->flags & MXC_EHCI_PORTSC_MASK;
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writel(portsc, base + 0x184);
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ret = imx_usbmisc_port_init(dev->id, pdata->flags);
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if (ret) {
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dev_err(dev, "failed to init misc regs: %s\n", strerror(-ret));
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return ret;
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}
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if ((pdata->flags & MXC_EHCI_PORTSC_MASK) == MXC_EHCI_MODE_ULPI) {
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dev_dbg(dev, "using ULPI phy\n");
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if (IS_ENABLED(CONFIG_USB_ULPI)) {
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ret = ulpi_setup(base + 0x170, 1);
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} else {
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dev_err(dev, "no ULPI support available\n");
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ret = -ENODEV;
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}
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if (ret)
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return ret;
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}
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data.hccr = base + 0x100;
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data.hcor = base + 0x140;
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data.flags = EHCI_HAS_TT;
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if (pdata->mode == IMX_USB_MODE_HOST) {
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ret = ehci_register(dev, &data);
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} else {
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/*
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* Not yet implemented. Register USB gadget driver here.
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*/
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ret = -ENOSYS;
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}
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return ret;
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};
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static struct driver_d imx_chipidea_driver = {
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.name = "imx-usb",
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.probe = imx_chipidea_probe,
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};
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static int imx_chipidea_init(void)
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{
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return platform_driver_register(&imx_chipidea_driver);
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}
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device_initcall(imx_chipidea_init);
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@ -0,0 +1,410 @@
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/*
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* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
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* Copyright (C) 2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <usb/chipidea-imx.h>
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#define MX25_OTG_SIC_SHIFT 29
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#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT)
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#define MX25_OTG_PM_BIT (1 << 24)
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#define MX25_OTG_PP_BIT (1 << 11)
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#define MX25_OTG_OCPOL_BIT (1 << 3)
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#define MX25_H1_SIC_SHIFT 21
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#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT)
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#define MX25_H1_PP_BIT (1 << 18)
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#define MX25_H1_PM_BIT (1 << 8)
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#define MX25_H1_IPPUE_UP_BIT (1 << 7)
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#define MX25_H1_IPPUE_DOWN_BIT (1 << 6)
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#define MX25_H1_TLL_BIT (1 << 5)
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#define MX25_H1_USBTE_BIT (1 << 4)
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#define MX25_H1_OCPOL_BIT (1 << 2)
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static __maybe_unused int mx25_initialize_usb_hw(void __iomem *base, int port, unsigned int flags)
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{
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unsigned int v;
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v = readl(base);
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switch (port) {
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case 0: /* OTG port */
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v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
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MX25_OTG_OCPOL_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX25_OTG_PM_BIT;
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if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
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v |= MX25_OTG_PP_BIT;
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if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
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v |= MX25_OTG_OCPOL_BIT;
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break;
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case 1: /* H1 port */
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v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
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MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT |
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MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX25_H1_PM_BIT;
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if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
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v |= MX25_H1_PP_BIT;
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if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
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v |= MX25_H1_OCPOL_BIT;
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if (!(flags & MXC_EHCI_TLL_ENABLED))
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v |= MX25_H1_TLL_BIT;
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if (flags & MXC_EHCI_INTERNAL_PHY)
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v |= MX25_H1_USBTE_BIT;
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if (flags & MXC_EHCI_IPPUE_DOWN)
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v |= MX25_H1_IPPUE_DOWN_BIT;
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if (flags & MXC_EHCI_IPPUE_UP)
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v |= MX25_H1_IPPUE_UP_BIT;
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break;
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default:
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return -EINVAL;
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}
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writel(v, base);
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return 0;
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}
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#define MX27_OTG_SIC_SHIFT 29
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#define MX27_OTG_SIC_MASK (0x3 << MX27_OTG_SIC_SHIFT)
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#define MX27_OTG_PM_BIT (1 << 24)
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#define MX27_H2_SIC_SHIFT 21
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#define MX27_H2_SIC_MASK (0x3 << MX27_H2_SIC_SHIFT)
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#define MX27_H2_PM_BIT (1 << 16)
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#define MX27_H2_DT_BIT (1 << 5)
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#define MX27_H1_SIC_SHIFT 13
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#define MX27_H1_SIC_MASK (0x3 << MX27_H1_SIC_SHIFT)
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#define MX27_H1_PM_BIT (1 << 8)
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#define MX27_H1_DT_BIT (1 << 4)
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static __maybe_unused int mx27_mx31_initialize_usb_hw(void __iomem *base, int port, unsigned int flags)
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{
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unsigned int v;
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v = readl(base);
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switch (port) {
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case 0: /* OTG port */
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v &= ~(MX27_OTG_SIC_MASK | MX27_OTG_PM_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_OTG_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX27_OTG_PM_BIT;
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break;
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case 1: /* H1 port */
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v &= ~(MX27_H1_SIC_MASK | MX27_H1_PM_BIT | MX27_H1_DT_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_H1_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX27_H1_PM_BIT;
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if (!(flags & MXC_EHCI_TLL_ENABLED))
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v |= MX27_H1_DT_BIT;
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break;
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case 2: /* H2 port */
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v &= ~(MX27_H2_SIC_MASK | MX27_H2_PM_BIT | MX27_H2_DT_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_H2_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX27_H2_PM_BIT;
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if (!(flags & MXC_EHCI_TLL_ENABLED))
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v |= MX27_H2_DT_BIT;
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break;
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default:
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return -EINVAL;
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}
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writel(v, base);
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return 0;
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}
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#define USBCTRL_OTGBASE_OFFSET 0x600
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#define MX35_OTG_SIC_SHIFT 29
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#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
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#define MX35_OTG_PM_BIT (1 << 24)
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#define MX35_OTG_PP_BIT (1 << 11)
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#define MX35_OTG_OCPOL_BIT (1 << 3)
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#define MX35_H1_SIC_SHIFT 21
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#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
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#define MX35_H1_PP_BIT (1 << 18)
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#define MX35_H1_PM_BIT (1 << 8)
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#define MX35_H1_IPPUE_UP_BIT (1 << 7)
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#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
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#define MX35_H1_TLL_BIT (1 << 5)
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#define MX35_H1_USBTE_BIT (1 << 4)
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#define MX35_H1_OCPOL_BIT (1 << 2)
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static __maybe_unused int mx35_initialize_usb_hw(void __iomem *base, int port, unsigned int flags)
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{
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unsigned int v;
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v = readl(base);
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switch (port) {
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case 0: /* OTG port */
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v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
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MX35_OTG_OCPOL_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX35_OTG_PM_BIT;
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if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
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v |= MX35_OTG_PP_BIT;
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if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
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v |= MX35_OTG_OCPOL_BIT;
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break;
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case 1: /* H1 port */
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v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT |
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MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT |
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MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX35_H1_PM_BIT;
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if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
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v |= MX35_H1_PP_BIT;
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if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
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v |= MX35_H1_OCPOL_BIT;
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if (!(flags & MXC_EHCI_TLL_ENABLED))
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v |= MX35_H1_TLL_BIT;
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if (flags & MXC_EHCI_INTERNAL_PHY)
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v |= MX35_H1_USBTE_BIT;
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if (flags & MXC_EHCI_IPPUE_DOWN)
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v |= MX35_H1_IPPUE_DOWN_BIT;
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if (flags & MXC_EHCI_IPPUE_UP)
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v |= MX35_H1_IPPUE_UP_BIT;
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break;
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default:
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return -EINVAL;
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}
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writel(v, base);
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return 0;
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}
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/* USB_CTRL */
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#define MX5_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
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#define MX5_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
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#define MX5_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
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#define MX5_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
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#define MX5_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
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/* USB_PHY_CTRL_FUNC */
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#define MX5_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of Overcurrent */
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#define MX5_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
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#define MX5_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent */
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#define MX5_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
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#define MX5_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* OTG Power Pin Polarity */
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/* USBH2CTRL */
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#define MX5_H2_UCTRL_H2UIE_BIT (1 << 8)
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#define MX5_H2_UCTRL_H2WIE_BIT (1 << 7)
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#define MX5_H2_UCTRL_H2PM_BIT (1 << 4)
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#define MX5_USBCTRL_OFFSET 0x0
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#define MX5_UTMI_PHY_CTRL_0 0x8
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#define MX5_UTMI_PHY_CTRL_1 0xc
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#define MX5_USBH2CTRL_OFFSET 0x14
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static __maybe_unused int mx5_initialize_usb_hw(void __iomem *base, int port,
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unsigned int flags)
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{
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unsigned int v;
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switch (port) {
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case 0: /* OTG port */
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if (!(flags & MXC_EHCI_INTERNAL_PHY))
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return 0;
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/* Adjust UTMI PHY frequency to 24MHz */
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v = readl(base + MX5_UTMI_PHY_CTRL_1);
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v = (v & ~0x3) | 0x01;
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writel(v, base + MX5_UTMI_PHY_CTRL_1);
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v = readl(base + MX5_UTMI_PHY_CTRL_0);
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v &= ~MX5_OTG_PHYCTRL_OC_POL_BIT;
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v &= ~MX5_OTG_PHYCTRL_OC_DIS_BIT;
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v &= ~MX5_OTG_PHYCTRL_PWR_POL_BIT;
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if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
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v |= MX5_OTG_PHYCTRL_OC_POL_BIT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX5_OTG_PHYCTRL_OC_DIS_BIT;
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if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
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v |= MX5_OTG_PHYCTRL_PWR_POL_BIT;
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writel(v, base + MX5_UTMI_PHY_CTRL_0);
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v = readl(base + MX5_USBCTRL_OFFSET);
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v &= ~MX5_OTG_UCTRL_OWIE_BIT;
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v &= ~MX5_OTG_UCTRL_OPM_BIT;
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|
||||
if (flags & MXC_EHCI_WAKEUP_ENABLED)
|
||||
v |= MX5_OTG_UCTRL_OWIE_BIT;
|
||||
|
||||
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
|
||||
v |= MX5_OTG_UCTRL_OPM_BIT;
|
||||
|
||||
writel(v, base + MX5_USBCTRL_OFFSET);
|
||||
|
||||
break;
|
||||
case 1: /* H1 port */
|
||||
v = readl(base + MX5_USBCTRL_OFFSET);
|
||||
v &= ~MX5_H1_UCTRL_H1PM_BIT;
|
||||
|
||||
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
|
||||
v |= MX5_H1_UCTRL_H1PM_BIT;
|
||||
|
||||
writel(v, base + MX5_USBCTRL_OFFSET);
|
||||
|
||||
break;
|
||||
case 2: /* H2 port */
|
||||
v = readl(base + MX5_USBH2CTRL_OFFSET);
|
||||
v &= ~MX5_H2_UCTRL_H2PM_BIT;
|
||||
|
||||
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
|
||||
v |= MX5_H2_UCTRL_H2PM_BIT;
|
||||
|
||||
writel(v, base + MX5_USBH2CTRL_OFFSET);
|
||||
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_device_id imx_usbmisc_ids[] = {
|
||||
#ifdef CONFIG_ARCH_IMX25
|
||||
{
|
||||
.name = "imx25-usb-misc",
|
||||
.driver_data = (unsigned long)&mx25_initialize_usb_hw,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_IMX27
|
||||
{
|
||||
.name = "imx27-usb-misc",
|
||||
.driver_data = (unsigned long)&mx27_mx31_initialize_usb_hw,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_IMX31
|
||||
{
|
||||
.name = "imx31-usb-misc",
|
||||
.driver_data = (unsigned long)&mx27_mx31_initialize_usb_hw,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_IMX35
|
||||
{
|
||||
.name = "imx35-usb-misc",
|
||||
.driver_data = (unsigned long)&mx35_initialize_usb_hw,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_IMX51
|
||||
{
|
||||
.name = "imx51-usb-misc",
|
||||
.driver_data = (unsigned long)&mx5_initialize_usb_hw,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_IMX53
|
||||
{
|
||||
.name = "imx53-usb-misc",
|
||||
.driver_data = (unsigned long)&mx5_initialize_usb_hw,
|
||||
},
|
||||
#endif
|
||||
{
|
||||
/* sentinel */
|
||||
},
|
||||
};
|
||||
|
||||
static int (*__imx_usbmisc_port_init)(void __iomem *base, int port, unsigned flags);
|
||||
static void __iomem *usbmisc_base;
|
||||
|
||||
int imx_usbmisc_port_init(int port, unsigned flags)
|
||||
{
|
||||
if (!__imx_usbmisc_port_init)
|
||||
return -ENODEV;
|
||||
|
||||
return __imx_usbmisc_port_init(usbmisc_base, port, flags);
|
||||
}
|
||||
|
||||
static int imx_usbmisc_probe(struct device_d *dev)
|
||||
{
|
||||
struct imx_serial_devtype_data *devtype;
|
||||
int ret;
|
||||
|
||||
ret = dev_get_drvdata(dev, (unsigned long *)&devtype);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
usbmisc_base = dev_request_mem_region(dev, 0);
|
||||
if (!usbmisc_base)
|
||||
return -ENOMEM;
|
||||
|
||||
__imx_usbmisc_port_init = (void *)devtype;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct driver_d imx_usbmisc_driver = {
|
||||
.name = "imx-usbmisc",
|
||||
.probe = imx_usbmisc_probe,
|
||||
.id_table = imx_usbmisc_ids,
|
||||
};
|
||||
|
||||
static int imx_usbmisc_init(void)
|
||||
{
|
||||
platform_driver_register(&imx_usbmisc_driver);
|
||||
return 0;
|
||||
}
|
||||
|
||||
coredevice_initcall(imx_usbmisc_init);
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
#ifndef __USB_CHIPIDEA_IMX_H
|
||||
#define __USB_CHIPIDEA_IMX_H
|
||||
|
||||
/*
|
||||
* POTSC flags
|
||||
*/
|
||||
#define MXC_EHCI_SERIAL (1 << 29)
|
||||
#define MXC_EHCI_MODE_UTMI_8BIT (0 << 30)
|
||||
#define MXC_EHCI_MODE_UTMI_16_BIT ((0 << 30) | (1 << 28))
|
||||
#define MXC_EHCI_MODE_PHILIPS (1 << 30)
|
||||
#define MXC_EHCI_MODE_ULPI (2 << 30)
|
||||
#define MXC_EHCI_MODE_SERIAL (3 << 30)
|
||||
|
||||
/*
|
||||
* USB misc flags
|
||||
*/
|
||||
#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
|
||||
#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
|
||||
#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
|
||||
#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
|
||||
#define MXC_EHCI_INTERFACE_MASK (0xf)
|
||||
|
||||
#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
|
||||
#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6)
|
||||
#define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7)
|
||||
#define MXC_EHCI_TLL_ENABLED (1 << 8)
|
||||
|
||||
#define MXC_EHCI_INTERNAL_PHY (1 << 9)
|
||||
#define MXC_EHCI_IPPUE_DOWN (1 << 10)
|
||||
#define MXC_EHCI_IPPUE_UP (1 << 11)
|
||||
#define MXC_EHCI_WAKEUP_ENABLED (1 << 12)
|
||||
#define MXC_EHCI_ITC_NO_THRESHOLD (1 << 13)
|
||||
|
||||
enum imx_usb_mode {
|
||||
IMX_USB_MODE_HOST,
|
||||
IMX_USB_MODE_DEVICE,
|
||||
};
|
||||
|
||||
struct imxusb_platformdata {
|
||||
unsigned long flags;
|
||||
enum imx_usb_mode mode;
|
||||
};
|
||||
|
||||
int imx_usbmisc_port_init(int port, unsigned flags);
|
||||
|
||||
#endif /* __USB_CHIPIDEA_IMX_H */
|
||||
Loading…
Reference in New Issue