ARM: mxs: Add lowlevel setup from U-Boot
U-Boot has code to replace the infamous Freescale bootlet code. This patch adds this for barebox with some changes: - Separate it more into mx23/mx28 functions instead of mxs functions with #ifdefs for the actual SoC - Add mx2x_power_init_battery_input() power entry point for boards which have a regulated input on the battery pin to supply the board. - Export more functions to be more flexible when boards need non standard setup. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
7f00863010
commit
a47c7d1ecb
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@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_IMX23) += clocksource-imx23.o usb-imx23.o soc-imx23.o
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obj-$(CONFIG_ARCH_IMX28) += clocksource-imx28.o usb-imx28.o soc-imx28.o
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obj-$(CONFIG_MXS_OCOTP) += ocotp.o
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obj-$(CONFIG_MXS_CMD_BCB) += bcb.o
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pbl-y += power-init.o mem-init.o lradc-init.o
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@ -0,0 +1,33 @@
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/*
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* Freescale i.MX28 SPL functions
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __M28_INIT_H__
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#define __M28_INIT_H__
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void mxs_early_delay(int delay);
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void mx23_power_init(void);
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void mx23_power_init_battery_input(void);
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void mx28_power_init(void);
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void mx28_power_init_battery_input(void);
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void mxs_power_wait_pswitch(void);
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extern uint32_t mx28_dram_vals[];
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extern uint32_t mx23_dram_vals[];
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void mx23_mem_init(void);
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void mx28_mem_init(void);
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void mxs_mem_setup_cpu_and_hbus(void);
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void mxs_mem_setup_vdda(void);
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void mxs_mem_init_clock(unsigned char divider);
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void mxs_lradc_init(void);
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void mxs_lradc_enable_batt_measurement(void);
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#endif /* __M28_INIT_H__ */
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@ -0,0 +1,208 @@
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/*
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* Freescale i.MX23 CLKCTRL Register Definitions
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*
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* Copyright (C) 2012 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* Based on code from LTIB:
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* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __MX23_REGS_CLKCTRL_H__
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#define __MX23_REGS_CLKCTRL_H__
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#include <mach/regs-common.h>
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#ifndef __ASSEMBLY__
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struct mxs_clkctrl_regs {
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mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */
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uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */
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uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */
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mxs_reg_32(hw_clkctrl_cpu) /* 0x20 */
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mxs_reg_32(hw_clkctrl_hbus) /* 0x30 */
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mxs_reg_32(hw_clkctrl_xbus) /* 0x40 */
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mxs_reg_32(hw_clkctrl_xtal) /* 0x50 */
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mxs_reg_32(hw_clkctrl_pix) /* 0x60 */
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mxs_reg_32(hw_clkctrl_ssp0) /* 0x70 */
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mxs_reg_32(hw_clkctrl_gpmi) /* 0x80 */
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mxs_reg_32(hw_clkctrl_spdif) /* 0x90 */
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mxs_reg_32(hw_clkctrl_emi) /* 0xa0 */
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uint32_t reserved1[4];
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mxs_reg_32(hw_clkctrl_saif0) /* 0xc0 */
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mxs_reg_32(hw_clkctrl_tv) /* 0xd0 */
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mxs_reg_32(hw_clkctrl_etm) /* 0xe0 */
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mxs_reg_8(hw_clkctrl_frac0) /* 0xf0 */
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mxs_reg_8(hw_clkctrl_frac1) /* 0x100 */
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mxs_reg_32(hw_clkctrl_clkseq) /* 0x110 */
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mxs_reg_32(hw_clkctrl_reset) /* 0x120 */
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mxs_reg_32(hw_clkctrl_status) /* 0x130 */
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mxs_reg_32(hw_clkctrl_version) /* 0x140 */
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};
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#endif
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#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28)
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#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28
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#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28)
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#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28)
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#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28)
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#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28)
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#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24)
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#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24
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#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24)
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#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24)
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#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24)
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#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24)
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#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20)
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#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20
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#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20)
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#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20)
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#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20)
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#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20)
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#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18)
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#define CLKCTRL_PLL0CTRL0_POWER (1 << 16)
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#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31)
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#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30)
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#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff
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#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0
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#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29)
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#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28)
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#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26)
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#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16)
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#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16
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#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12)
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#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10)
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#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f
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#define CLKCTRL_CPU_DIV_CPU_OFFSET 0
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#define CLKCTRL_HBUS_BUSY (1 << 29)
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#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 28)
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#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 27)
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#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26)
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#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25)
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#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24)
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#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23)
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#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22)
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#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21)
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#define CLKCTRL_HBUS_AUTO_SLOW_MODE (1 << 20)
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#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16)
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#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16
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#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16)
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#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16)
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#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16)
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#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16)
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#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16)
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#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16)
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#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5)
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#define CLKCTRL_HBUS_DIV_MASK 0x1f
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#define CLKCTRL_HBUS_DIV_OFFSET 0
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#define CLKCTRL_XBUS_BUSY (1 << 31)
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#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10)
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#define CLKCTRL_XBUS_DIV_MASK 0x3ff
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#define CLKCTRL_XBUS_DIV_OFFSET 0
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#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31)
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#define CLKCTRL_XTAL_FILT_CLK24M_GATE (1 << 30)
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#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29)
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#define CLKCTRL_XTAL_DRI_CLK24M_GATE (1 << 28)
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#define CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE (1 << 27)
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#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26)
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#define CLKCTRL_XTAL_DIV_UART_MASK 0x3
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#define CLKCTRL_XTAL_DIV_UART_OFFSET 0
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#define CLKCTRL_PIX_CLKGATE (1 << 31)
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#define CLKCTRL_PIX_BUSY (1 << 29)
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#define CLKCTRL_PIX_DIV_FRAC_EN (1 << 12)
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#define CLKCTRL_PIX_DIV_MASK 0xfff
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#define CLKCTRL_PIX_DIV_OFFSET 0
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#define CLKCTRL_SSP_CLKGATE (1 << 31)
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#define CLKCTRL_SSP_BUSY (1 << 29)
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#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9)
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#define CLKCTRL_SSP_DIV_MASK 0x1ff
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#define CLKCTRL_SSP_DIV_OFFSET 0
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#define CLKCTRL_GPMI_CLKGATE (1 << 31)
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#define CLKCTRL_GPMI_BUSY (1 << 29)
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#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10)
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#define CLKCTRL_GPMI_DIV_MASK 0x3ff
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#define CLKCTRL_GPMI_DIV_OFFSET 0
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#define CLKCTRL_SPDIF_CLKGATE (1 << 31)
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#define CLKCTRL_EMI_CLKGATE (1 << 31)
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#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30)
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#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29)
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#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28)
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#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27)
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#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26)
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#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17)
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#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16)
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#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8)
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#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8
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#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f
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#define CLKCTRL_EMI_DIV_EMI_OFFSET 0
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#define CLKCTRL_IR_CLKGATE (1 << 31)
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#define CLKCTRL_IR_AUTO_DIV (1 << 29)
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#define CLKCTRL_IR_IR_BUSY (1 << 28)
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#define CLKCTRL_IR_IROV_BUSY (1 << 27)
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#define CLKCTRL_IR_IROV_DIV_MASK (0x1ff << 16)
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#define CLKCTRL_IR_IROV_DIV_OFFSET 16
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#define CLKCTRL_IR_IR_DIV_MASK 0x3ff
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#define CLKCTRL_IR_IR_DIV_OFFSET 0
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#define CLKCTRL_SAIF0_CLKGATE (1 << 31)
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#define CLKCTRL_SAIF0_BUSY (1 << 29)
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#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16)
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#define CLKCTRL_SAIF0_DIV_MASK 0xffff
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#define CLKCTRL_SAIF0_DIV_OFFSET 0
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#define CLKCTRL_TV_CLK_TV108M_GATE (1 << 31)
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#define CLKCTRL_TV_CLK_TV_GATE (1 << 30)
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#define CLKCTRL_ETM_CLKGATE (1 << 31)
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#define CLKCTRL_ETM_BUSY (1 << 29)
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#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 6)
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#define CLKCTRL_ETM_DIV_MASK 0x3f
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#define CLKCTRL_ETM_DIV_OFFSET 0
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#define CLKCTRL_FRAC_CLKGATE (1 << 7)
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#define CLKCTRL_FRAC_STABLE (1 << 6)
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#define CLKCTRL_FRAC_FRAC_MASK 0x3f
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#define CLKCTRL_FRAC_FRAC_OFFSET 0
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#define CLKCTRL_FRAC0_CPU 0
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#define CLKCTRL_FRAC0_EMI 1
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#define CLKCTRL_FRAC0_PIX 2
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#define CLKCTRL_FRAC0_IO0 3
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#define CLKCTRL_FRAC1_VID 3
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#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8)
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#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 7)
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#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 6)
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#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 5)
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#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 4)
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#define CLKCTRL_CLKSEQ_BYPASS_IR (1 << 3)
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#define CLKCTRL_CLKSEQ_BYPASS_PIX (1 << 1)
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#define CLKCTRL_CLKSEQ_BYPASS_SAIF (1 << 0)
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#define CLKCTRL_RESET_CHIP (1 << 1)
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#define CLKCTRL_RESET_DIG (1 << 0)
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#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30)
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#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30
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#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24)
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#define CLKCTRL_VERSION_MAJOR_OFFSET 24
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#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16)
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#define CLKCTRL_VERSION_MINOR_OFFSET 16
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#define CLKCTRL_VERSION_STEP_MASK 0xffff
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#define CLKCTRL_VERSION_STEP_OFFSET 0
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#endif /* __MX23_REGS_CLKCTRL_H__ */
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@ -0,0 +1,283 @@
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/*
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* Freescale i.MX28 CLKCTRL Register Definitions
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* Based on code from LTIB:
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* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __MX28_REGS_CLKCTRL_H__
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#define __MX28_REGS_CLKCTRL_H__
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#include <mach/regs-common.h>
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#ifndef __ASSEMBLY__
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struct mxs_clkctrl_regs {
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mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */
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uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */
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uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */
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mxs_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */
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uint32_t hw_clkctrl_pll1ctrl1; /* 0x30 */
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uint32_t reserved_pll1ctrl1[3]; /* 0x34-0x3c */
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mxs_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */
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mxs_reg_32(hw_clkctrl_cpu) /* 0x50 */
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mxs_reg_32(hw_clkctrl_hbus) /* 0x60 */
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mxs_reg_32(hw_clkctrl_xbus) /* 0x70 */
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mxs_reg_32(hw_clkctrl_xtal) /* 0x80 */
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mxs_reg_32(hw_clkctrl_ssp0) /* 0x90 */
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mxs_reg_32(hw_clkctrl_ssp1) /* 0xa0 */
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mxs_reg_32(hw_clkctrl_ssp2) /* 0xb0 */
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mxs_reg_32(hw_clkctrl_ssp3) /* 0xc0 */
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mxs_reg_32(hw_clkctrl_gpmi) /* 0xd0 */
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mxs_reg_32(hw_clkctrl_spdif) /* 0xe0 */
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mxs_reg_32(hw_clkctrl_emi) /* 0xf0 */
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mxs_reg_32(hw_clkctrl_saif0) /* 0x100 */
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mxs_reg_32(hw_clkctrl_saif1) /* 0x110 */
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mxs_reg_32(hw_clkctrl_lcdif) /* 0x120 */
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mxs_reg_32(hw_clkctrl_etm) /* 0x130 */
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mxs_reg_32(hw_clkctrl_enet) /* 0x140 */
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mxs_reg_32(hw_clkctrl_hsadc) /* 0x150 */
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mxs_reg_32(hw_clkctrl_flexcan) /* 0x160 */
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uint32_t reserved[16];
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mxs_reg_8(hw_clkctrl_frac0) /* 0x1b0 */
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mxs_reg_8(hw_clkctrl_frac1) /* 0x1c0 */
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mxs_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */
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mxs_reg_32(hw_clkctrl_reset) /* 0x1e0 */
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mxs_reg_32(hw_clkctrl_status) /* 0x1f0 */
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mxs_reg_32(hw_clkctrl_version) /* 0x200 */
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};
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#endif
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#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28)
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#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28
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#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28)
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#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28)
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#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28)
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#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28)
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#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24)
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#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24
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#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24)
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#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24)
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#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24)
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#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24)
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#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20)
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#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20
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#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20)
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#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20)
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#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20)
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#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20)
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#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18)
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#define CLKCTRL_PLL0CTRL0_POWER (1 << 17)
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#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31)
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#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30)
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#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff
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#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0
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#define CLKCTRL_PLL1CTRL0_CLKGATEEMI (1 << 31)
|
||||
#define CLKCTRL_PLL1CTRL0_LFR_SEL_MASK (0x3 << 28)
|
||||
#define CLKCTRL_PLL1CTRL0_LFR_SEL_OFFSET 28
|
||||
#define CLKCTRL_PLL1CTRL0_LFR_SEL_DEFAULT (0x0 << 28)
|
||||
#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_2 (0x1 << 28)
|
||||
#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_05 (0x2 << 28)
|
||||
#define CLKCTRL_PLL1CTRL0_LFR_SEL_UNDEFINED (0x3 << 28)
|
||||
#define CLKCTRL_PLL1CTRL0_CP_SEL_MASK (0x3 << 24)
|
||||
#define CLKCTRL_PLL1CTRL0_CP_SEL_OFFSET 24
|
||||
#define CLKCTRL_PLL1CTRL0_CP_SEL_DEFAULT (0x0 << 24)
|
||||
#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_2 (0x1 << 24)
|
||||
#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_05 (0x2 << 24)
|
||||
#define CLKCTRL_PLL1CTRL0_CP_SEL_UNDEFINED (0x3 << 24)
|
||||
#define CLKCTRL_PLL1CTRL0_DIV_SEL_MASK (0x3 << 20)
|
||||
#define CLKCTRL_PLL1CTRL0_DIV_SEL_OFFSET 20
|
||||
#define CLKCTRL_PLL1CTRL0_DIV_SEL_DEFAULT (0x0 << 20)
|
||||
#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWER (0x1 << 20)
|
||||
#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWEST (0x2 << 20)
|
||||
#define CLKCTRL_PLL1CTRL0_DIV_SEL_UNDEFINED (0x3 << 20)
|
||||
#define CLKCTRL_PLL1CTRL0_EN_USB_CLKS (1 << 18)
|
||||
#define CLKCTRL_PLL1CTRL0_POWER (1 << 17)
|
||||
|
||||
#define CLKCTRL_PLL1CTRL1_LOCK (1 << 31)
|
||||
#define CLKCTRL_PLL1CTRL1_FORCE_LOCK (1 << 30)
|
||||
#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_MASK 0xffff
|
||||
#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_OFFSET 0
|
||||
|
||||
#define CLKCTRL_PLL2CTRL0_CLKGATE (1 << 31)
|
||||
#define CLKCTRL_PLL2CTRL0_LFR_SEL_MASK (0x3 << 28)
|
||||
#define CLKCTRL_PLL2CTRL0_LFR_SEL_OFFSET 28
|
||||
#define CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B (1 << 26)
|
||||
#define CLKCTRL_PLL2CTRL0_CP_SEL_MASK (0x3 << 24)
|
||||
#define CLKCTRL_PLL2CTRL0_CP_SEL_OFFSET 24
|
||||
#define CLKCTRL_PLL2CTRL0_POWER (1 << 23)
|
||||
|
||||
#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29)
|
||||
#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28)
|
||||
#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26)
|
||||
#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16)
|
||||
#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16
|
||||
#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12)
|
||||
#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10)
|
||||
#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f
|
||||
#define CLKCTRL_CPU_DIV_CPU_OFFSET 0
|
||||
|
||||
#define CLKCTRL_HBUS_ASM_BUSY (1 << 31)
|
||||
#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 30)
|
||||
#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 29)
|
||||
#define CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE (1 << 27)
|
||||
#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26)
|
||||
#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25)
|
||||
#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24)
|
||||
#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23)
|
||||
#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22)
|
||||
#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21)
|
||||
#define CLKCTRL_HBUS_ASM_ENABLE (1 << 20)
|
||||
#define CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE (1 << 19)
|
||||
#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16)
|
||||
#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16
|
||||
#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16)
|
||||
#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16)
|
||||
#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16)
|
||||
#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16)
|
||||
#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16)
|
||||
#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16)
|
||||
#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5)
|
||||
#define CLKCTRL_HBUS_DIV_MASK 0x1f
|
||||
#define CLKCTRL_HBUS_DIV_OFFSET 0
|
||||
|
||||
#define CLKCTRL_XBUS_BUSY (1 << 31)
|
||||
#define CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE (1 << 11)
|
||||
#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10)
|
||||
#define CLKCTRL_XBUS_DIV_MASK 0x3ff
|
||||
#define CLKCTRL_XBUS_DIV_OFFSET 0
|
||||
|
||||
#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31)
|
||||
#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29)
|
||||
#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26)
|
||||
#define CLKCTRL_XTAL_DIV_UART_MASK 0x3
|
||||
#define CLKCTRL_XTAL_DIV_UART_OFFSET 0
|
||||
|
||||
#define CLKCTRL_SSP_CLKGATE (1 << 31)
|
||||
#define CLKCTRL_SSP_BUSY (1 << 29)
|
||||
#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9)
|
||||
#define CLKCTRL_SSP_DIV_MASK 0x1ff
|
||||
#define CLKCTRL_SSP_DIV_OFFSET 0
|
||||
|
||||
#define CLKCTRL_GPMI_CLKGATE (1 << 31)
|
||||
#define CLKCTRL_GPMI_BUSY (1 << 29)
|
||||
#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10)
|
||||
#define CLKCTRL_GPMI_DIV_MASK 0x3ff
|
||||
#define CLKCTRL_GPMI_DIV_OFFSET 0
|
||||
|
||||
#define CLKCTRL_SPDIF_CLKGATE (1 << 31)
|
||||
|
||||
#define CLKCTRL_EMI_CLKGATE (1 << 31)
|
||||
#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30)
|
||||
#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29)
|
||||
#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28)
|
||||
#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27)
|
||||
#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26)
|
||||
#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17)
|
||||
#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16)
|
||||
#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8)
|
||||
#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8
|
||||
#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f
|
||||
#define CLKCTRL_EMI_DIV_EMI_OFFSET 0
|
||||
|
||||
#define CLKCTRL_SAIF0_CLKGATE (1 << 31)
|
||||
#define CLKCTRL_SAIF0_BUSY (1 << 29)
|
||||
#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16)
|
||||
#define CLKCTRL_SAIF0_DIV_MASK 0xffff
|
||||
#define CLKCTRL_SAIF0_DIV_OFFSET 0
|
||||
|
||||
#define CLKCTRL_SAIF1_CLKGATE (1 << 31)
|
||||
#define CLKCTRL_SAIF1_BUSY (1 << 29)
|
||||
#define CLKCTRL_SAIF1_DIV_FRAC_EN (1 << 16)
|
||||
#define CLKCTRL_SAIF1_DIV_MASK 0xffff
|
||||
#define CLKCTRL_SAIF1_DIV_OFFSET 0
|
||||
|
||||
#define CLKCTRL_DIS_LCDIF_CLKGATE (1 << 31)
|
||||
#define CLKCTRL_DIS_LCDIF_BUSY (1 << 29)
|
||||
#define CLKCTRL_DIS_LCDIF_DIV_FRAC_EN (1 << 13)
|
||||
#define CLKCTRL_DIS_LCDIF_DIV_MASK 0x1fff
|
||||
#define CLKCTRL_DIS_LCDIF_DIV_OFFSET 0
|
||||
|
||||
#define CLKCTRL_ETM_CLKGATE (1 << 31)
|
||||
#define CLKCTRL_ETM_BUSY (1 << 29)
|
||||
#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 7)
|
||||
#define CLKCTRL_ETM_DIV_MASK 0x7f
|
||||
#define CLKCTRL_ETM_DIV_OFFSET 0
|
||||
|
||||
#define CLKCTRL_ENET_SLEEP (1 << 31)
|
||||
#define CLKCTRL_ENET_DISABLE (1 << 30)
|
||||
#define CLKCTRL_ENET_STATUS (1 << 29)
|
||||
#define CLKCTRL_ENET_BUSY_TIME (1 << 27)
|
||||
#define CLKCTRL_ENET_DIV_TIME_MASK (0x3f << 21)
|
||||
#define CLKCTRL_ENET_DIV_TIME_OFFSET 21
|
||||
#define CLKCTRL_ENET_TIME_SEL_MASK (0x3 << 19)
|
||||
#define CLKCTRL_ENET_TIME_SEL_OFFSET 19
|
||||
#define CLKCTRL_ENET_TIME_SEL_XTAL (0x0 << 19)
|
||||
#define CLKCTRL_ENET_TIME_SEL_PLL (0x1 << 19)
|
||||
#define CLKCTRL_ENET_TIME_SEL_RMII_CLK (0x2 << 19)
|
||||
#define CLKCTRL_ENET_TIME_SEL_UNDEFINED (0x3 << 19)
|
||||
#define CLKCTRL_ENET_CLK_OUT_EN (1 << 18)
|
||||
#define CLKCTRL_ENET_RESET_BY_SW_CHIP (1 << 17)
|
||||
#define CLKCTRL_ENET_RESET_BY_SW (1 << 16)
|
||||
|
||||
#define CLKCTRL_HSADC_RESETB (1 << 30)
|
||||
#define CLKCTRL_HSADC_FREQDIV_MASK (0x3 << 28)
|
||||
#define CLKCTRL_HSADC_FREQDIV_OFFSET 28
|
||||
|
||||
#define CLKCTRL_FLEXCAN_STOP_CAN0 (1 << 30)
|
||||
#define CLKCTRL_FLEXCAN_CAN0_STATUS (1 << 29)
|
||||
#define CLKCTRL_FLEXCAN_STOP_CAN1 (1 << 28)
|
||||
#define CLKCTRL_FLEXCAN_CAN1_STATUS (1 << 27)
|
||||
|
||||
#define CLKCTRL_FRAC_CLKGATE (1 << 7)
|
||||
#define CLKCTRL_FRAC_STABLE (1 << 6)
|
||||
#define CLKCTRL_FRAC_FRAC_MASK 0x3f
|
||||
#define CLKCTRL_FRAC_FRAC_OFFSET 0
|
||||
#define CLKCTRL_FRAC0_CPU 0
|
||||
#define CLKCTRL_FRAC0_EMI 1
|
||||
#define CLKCTRL_FRAC0_IO1 2
|
||||
#define CLKCTRL_FRAC0_IO0 3
|
||||
#define CLKCTRL_FRAC1_PIX 0
|
||||
#define CLKCTRL_FRAC1_HSADC 1
|
||||
#define CLKCTRL_FRAC1_GPMI 2
|
||||
|
||||
#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 18)
|
||||
#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14)
|
||||
#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_BYPASS (0x1 << 14)
|
||||
#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_PFD (0x0 << 14)
|
||||
#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8)
|
||||
#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 7)
|
||||
#define CLKCTRL_CLKSEQ_BYPASS_SSP3 (1 << 6)
|
||||
#define CLKCTRL_CLKSEQ_BYPASS_SSP2 (1 << 5)
|
||||
#define CLKCTRL_CLKSEQ_BYPASS_SSP1 (1 << 4)
|
||||
#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 3)
|
||||
#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 2)
|
||||
#define CLKCTRL_CLKSEQ_BYPASS_SAIF1 (1 << 1)
|
||||
#define CLKCTRL_CLKSEQ_BYPASS_SAIF0 (1 << 0)
|
||||
|
||||
#define CLKCTRL_RESET_WDOG_POR_DISABLE (1 << 5)
|
||||
#define CLKCTRL_RESET_EXTERNAL_RESET_ENABLE (1 << 4)
|
||||
#define CLKCTRL_RESET_THERMAL_RESET_ENABLE (1 << 3)
|
||||
#define CLKCTRL_RESET_THERMAL_RESET_DEFAULT (1 << 2)
|
||||
#define CLKCTRL_RESET_CHIP (1 << 1)
|
||||
#define CLKCTRL_RESET_DIG (1 << 0)
|
||||
|
||||
#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30)
|
||||
#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30
|
||||
|
||||
#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24)
|
||||
#define CLKCTRL_VERSION_MAJOR_OFFSET 24
|
||||
#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16)
|
||||
#define CLKCTRL_VERSION_MINOR_OFFSET 16
|
||||
#define CLKCTRL_VERSION_STEP_MASK 0xffff
|
||||
#define CLKCTRL_VERSION_STEP_OFFSET 0
|
||||
|
||||
#endif /* __MX28_REGS_CLKCTRL_H__ */
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
/*
|
||||
* Freescale i.MXS Register Accessors
|
||||
*
|
||||
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
|
||||
* on behalf of DENX Software Engineering GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __MXS_REGS_COMMON_H__
|
||||
#define __MXS_REGS_COMMON_H__
|
||||
|
||||
/*
|
||||
* The i.MXS has interesting feature when it comes to register access. There
|
||||
* are four kinds of access to one particular register. Those are:
|
||||
*
|
||||
* 1) Common read/write access. To use this mode, just write to the address of
|
||||
* the register.
|
||||
* 2) Set bits only access. To set bits, write which bits you want to set to the
|
||||
* address of the register + 0x4.
|
||||
* 3) Clear bits only access. To clear bits, write which bits you want to clear
|
||||
* to the address of the register + 0x8.
|
||||
* 4) Toggle bits only access. To toggle bits, write which bits you want to
|
||||
* toggle to the address of the register + 0xc.
|
||||
*
|
||||
* IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits
|
||||
* can be set/cleared by pure write as in access type 1, some need to be
|
||||
* explicitly set/cleared by using access type 2-3.
|
||||
*
|
||||
* The following macros and structures allow the user to either access the
|
||||
* register in all aforementioned modes (by accessing reg_name, reg_name_set,
|
||||
* reg_name_clr, reg_name_tog) or pass the register structure further into
|
||||
* various functions with correct type information (by accessing reg_name_reg).
|
||||
*
|
||||
*/
|
||||
|
||||
#define __mxs_reg_8(name) \
|
||||
uint8_t name[4]; \
|
||||
uint8_t name##_set[4]; \
|
||||
uint8_t name##_clr[4]; \
|
||||
uint8_t name##_tog[4]; \
|
||||
|
||||
#define __mxs_reg_32(name) \
|
||||
uint32_t name; \
|
||||
uint32_t name##_set; \
|
||||
uint32_t name##_clr; \
|
||||
uint32_t name##_tog;
|
||||
|
||||
struct mxs_register_8 {
|
||||
__mxs_reg_8(reg)
|
||||
};
|
||||
|
||||
struct mxs_register_32 {
|
||||
__mxs_reg_32(reg)
|
||||
};
|
||||
|
||||
#define mxs_reg_8(name) \
|
||||
union { \
|
||||
struct { __mxs_reg_8(name) }; \
|
||||
struct mxs_register_8 name##_reg; \
|
||||
};
|
||||
|
||||
#define mxs_reg_32(name) \
|
||||
union { \
|
||||
struct { __mxs_reg_32(name) }; \
|
||||
struct mxs_register_32 name##_reg; \
|
||||
};
|
||||
|
||||
#endif /* __MXS_REGS_COMMON_H__ */
|
||||
|
|
@ -0,0 +1,387 @@
|
|||
/*
|
||||
* Freescale i.MX28 LRADC Register Definitions
|
||||
*
|
||||
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
|
||||
* on behalf of DENX Software Engineering GmbH
|
||||
*
|
||||
* Based on code from LTIB:
|
||||
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __MX28_REGS_LRADC_H__
|
||||
#define __MX28_REGS_LRADC_H__
|
||||
|
||||
#include <mach/regs-common.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct mxs_lradc_regs {
|
||||
mxs_reg_32(hw_lradc_ctrl0);
|
||||
mxs_reg_32(hw_lradc_ctrl1);
|
||||
mxs_reg_32(hw_lradc_ctrl2);
|
||||
mxs_reg_32(hw_lradc_ctrl3);
|
||||
mxs_reg_32(hw_lradc_status);
|
||||
mxs_reg_32(hw_lradc_ch0);
|
||||
mxs_reg_32(hw_lradc_ch1);
|
||||
mxs_reg_32(hw_lradc_ch2);
|
||||
mxs_reg_32(hw_lradc_ch3);
|
||||
mxs_reg_32(hw_lradc_ch4);
|
||||
mxs_reg_32(hw_lradc_ch5);
|
||||
mxs_reg_32(hw_lradc_ch6);
|
||||
mxs_reg_32(hw_lradc_ch7);
|
||||
mxs_reg_32(hw_lradc_delay0);
|
||||
mxs_reg_32(hw_lradc_delay1);
|
||||
mxs_reg_32(hw_lradc_delay2);
|
||||
mxs_reg_32(hw_lradc_delay3);
|
||||
mxs_reg_32(hw_lradc_debug0);
|
||||
mxs_reg_32(hw_lradc_debug1);
|
||||
mxs_reg_32(hw_lradc_conversion);
|
||||
mxs_reg_32(hw_lradc_ctrl4);
|
||||
mxs_reg_32(hw_lradc_treshold0);
|
||||
mxs_reg_32(hw_lradc_treshold1);
|
||||
mxs_reg_32(hw_lradc_version);
|
||||
};
|
||||
#endif
|
||||
|
||||
#define LRADC_CTRL0_SFTRST (1 << 31)
|
||||
#define LRADC_CTRL0_CLKGATE (1 << 30)
|
||||
#define LRADC_CTRL0_ONCHIP_GROUNDREF (1 << 26)
|
||||
#define LRADC_CTRL0_BUTTON1_DETECT_ENABLE (1 << 25)
|
||||
#define LRADC_CTRL0_BUTTON0_DETECT_ENABLE (1 << 24)
|
||||
#define LRADC_CTRL0_TOUCH_DETECT_ENABLE (1 << 23)
|
||||
#define LRADC_CTRL0_TOUCH_SCREEN_TYPE (1 << 22)
|
||||
#define LRADC_CTRL0_YNLRSW (1 << 21)
|
||||
#define LRADC_CTRL0_YPLLSW_MASK (0x3 << 19)
|
||||
#define LRADC_CTRL0_YPLLSW_OFFSET 19
|
||||
#define LRADC_CTRL0_XNURSW_MASK (0x3 << 17)
|
||||
#define LRADC_CTRL0_XNURSW_OFFSET 17
|
||||
#define LRADC_CTRL0_XPULSW (1 << 16)
|
||||
#define LRADC_CTRL0_SCHEDULE_MASK 0xff
|
||||
#define LRADC_CTRL0_SCHEDULE_OFFSET 0
|
||||
|
||||
#define LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN (1 << 28)
|
||||
#define LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN (1 << 27)
|
||||
#define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN (1 << 26)
|
||||
#define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN (1 << 25)
|
||||
#define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN (1 << 24)
|
||||
#define LRADC_CTRL1_LRADC7_IRQ_EN (1 << 23)
|
||||
#define LRADC_CTRL1_LRADC6_IRQ_EN (1 << 22)
|
||||
#define LRADC_CTRL1_LRADC5_IRQ_EN (1 << 21)
|
||||
#define LRADC_CTRL1_LRADC4_IRQ_EN (1 << 20)
|
||||
#define LRADC_CTRL1_LRADC3_IRQ_EN (1 << 19)
|
||||
#define LRADC_CTRL1_LRADC2_IRQ_EN (1 << 18)
|
||||
#define LRADC_CTRL1_LRADC1_IRQ_EN (1 << 17)
|
||||
#define LRADC_CTRL1_LRADC0_IRQ_EN (1 << 16)
|
||||
#define LRADC_CTRL1_BUTTON1_DETECT_IRQ (1 << 12)
|
||||
#define LRADC_CTRL1_BUTTON0_DETECT_IRQ (1 << 11)
|
||||
#define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ (1 << 10)
|
||||
#define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ (1 << 9)
|
||||
#define LRADC_CTRL1_TOUCH_DETECT_IRQ (1 << 8)
|
||||
#define LRADC_CTRL1_LRADC7_IRQ (1 << 7)
|
||||
#define LRADC_CTRL1_LRADC6_IRQ (1 << 6)
|
||||
#define LRADC_CTRL1_LRADC5_IRQ (1 << 5)
|
||||
#define LRADC_CTRL1_LRADC4_IRQ (1 << 4)
|
||||
#define LRADC_CTRL1_LRADC3_IRQ (1 << 3)
|
||||
#define LRADC_CTRL1_LRADC2_IRQ (1 << 2)
|
||||
#define LRADC_CTRL1_LRADC1_IRQ (1 << 1)
|
||||
#define LRADC_CTRL1_LRADC0_IRQ (1 << 0)
|
||||
|
||||
#define LRADC_CTRL2_DIVIDE_BY_TWO_MASK (0xff << 24)
|
||||
#define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET 24
|
||||
#define LRADC_CTRL2_TEMPSENSE_PWD (1 << 15)
|
||||
#define LRADC_CTRL2_VTHSENSE_MASK (0x3 << 13)
|
||||
#define LRADC_CTRL2_VTHSENSE_OFFSET 13
|
||||
#define LRADC_CTRL2_DISABLE_MUXAMP_BYPASS (1 << 12)
|
||||
#define LRADC_CTRL2_TEMP_SENSOR_IENABLE1 (1 << 9)
|
||||
#define LRADC_CTRL2_TEMP_SENSOR_IENABLE0 (1 << 8)
|
||||
#define LRADC_CTRL2_TEMP_ISRC1_MASK (0xf << 4)
|
||||
#define LRADC_CTRL2_TEMP_ISRC1_OFFSET 4
|
||||
#define LRADC_CTRL2_TEMP_ISRC1_300 (0xf << 4)
|
||||
#define LRADC_CTRL2_TEMP_ISRC1_280 (0xe << 4)
|
||||
#define LRADC_CTRL2_TEMP_ISRC1_260 (0xd << 4)
|
||||
#define LRADC_CTRL2_TEMP_ISRC1_240 (0xc << 4)
|
||||
#define LRADC_CTRL2_TEMP_ISRC1_220 (0xb << 4)
|
||||
#define LRADC_CTRL2_TEMP_ISRC1_200 (0xa << 4)
|
||||
#define LRADC_CTRL2_TEMP_ISRC1_180 (0x9 << 4)
|
||||
#define LRADC_CTRL2_TEMP_ISRC1_160 (0x8 << 4)
|
||||
#define LRADC_CTRL2_TEMP_ISRC1_140 (0x7 << 4)
|
||||
#define LRADC_CTRL2_TEMP_ISRC1_120 (0x6 << 4)
|
||||
#define LRADC_CTRL2_TEMP_ISRC1_100 (0x5 << 4)
|
||||
#define LRADC_CTRL2_TEMP_ISRC1_80 (0x4 << 4)
|
||||
#define LRADC_CTRL2_TEMP_ISRC1_60 (0x3 << 4)
|
||||
#define LRADC_CTRL2_TEMP_ISRC1_40 (0x2 << 4)
|
||||
#define LRADC_CTRL2_TEMP_ISRC1_20 (0x1 << 4)
|
||||
#define LRADC_CTRL2_TEMP_ISRC1_ZERO (0x0 << 4)
|
||||
#define LRADC_CTRL2_TEMP_ISRC0_MASK (0xf << 0)
|
||||
#define LRADC_CTRL2_TEMP_ISRC0_OFFSET 0
|
||||
#define LRADC_CTRL2_TEMP_ISRC0_300 (0xf << 0)
|
||||
#define LRADC_CTRL2_TEMP_ISRC0_280 (0xe << 0)
|
||||
#define LRADC_CTRL2_TEMP_ISRC0_260 (0xd << 0)
|
||||
#define LRADC_CTRL2_TEMP_ISRC0_240 (0xc << 0)
|
||||
#define LRADC_CTRL2_TEMP_ISRC0_220 (0xb << 0)
|
||||
#define LRADC_CTRL2_TEMP_ISRC0_200 (0xa << 0)
|
||||
#define LRADC_CTRL2_TEMP_ISRC0_180 (0x9 << 0)
|
||||
#define LRADC_CTRL2_TEMP_ISRC0_160 (0x8 << 0)
|
||||
#define LRADC_CTRL2_TEMP_ISRC0_140 (0x7 << 0)
|
||||
#define LRADC_CTRL2_TEMP_ISRC0_120 (0x6 << 0)
|
||||
#define LRADC_CTRL2_TEMP_ISRC0_100 (0x5 << 0)
|
||||
#define LRADC_CTRL2_TEMP_ISRC0_80 (0x4 << 0)
|
||||
#define LRADC_CTRL2_TEMP_ISRC0_60 (0x3 << 0)
|
||||
#define LRADC_CTRL2_TEMP_ISRC0_40 (0x2 << 0)
|
||||
#define LRADC_CTRL2_TEMP_ISRC0_20 (0x1 << 0)
|
||||
#define LRADC_CTRL2_TEMP_ISRC0_ZERO (0x0 << 0)
|
||||
|
||||
#define LRADC_CTRL3_DISCARD_MASK (0x3 << 24)
|
||||
#define LRADC_CTRL3_DISCARD_OFFSET 24
|
||||
#define LRADC_CTRL3_DISCARD_1_SAMPLE (0x1 << 24)
|
||||
#define LRADC_CTRL3_DISCARD_2_SAMPLES (0x2 << 24)
|
||||
#define LRADC_CTRL3_DISCARD_3_SAMPLES (0x3 << 24)
|
||||
#define LRADC_CTRL3_FORCE_ANALOG_PWUP (1 << 23)
|
||||
#define LRADC_CTRL3_FORCE_ANALOG_PWDN (1 << 22)
|
||||
#define LRADC_CTRL3_CYCLE_TIME_MASK (0x3 << 8)
|
||||
#define LRADC_CTRL3_CYCLE_TIME_OFFSET 8
|
||||
#define LRADC_CTRL3_CYCLE_TIME_6MHZ (0x0 << 8)
|
||||
#define LRADC_CTRL3_CYCLE_TIME_4MHZ (0x1 << 8)
|
||||
#define LRADC_CTRL3_CYCLE_TIME_3MHZ (0x2 << 8)
|
||||
#define LRADC_CTRL3_CYCLE_TIME_2MHZ (0x3 << 8)
|
||||
#define LRADC_CTRL3_HIGH_TIME_MASK (0x3 << 4)
|
||||
#define LRADC_CTRL3_HIGH_TIME_OFFSET 4
|
||||
#define LRADC_CTRL3_HIGH_TIME_42NS (0x0 << 4)
|
||||
#define LRADC_CTRL3_HIGH_TIME_83NS (0x1 << 4)
|
||||
#define LRADC_CTRL3_HIGH_TIME_125NS (0x2 << 4)
|
||||
#define LRADC_CTRL3_HIGH_TIME_250NS (0x3 << 4)
|
||||
#define LRADC_CTRL3_DELAY_CLOCK (1 << 1)
|
||||
#define LRADC_CTRL3_INVERT_CLOCK (1 << 0)
|
||||
|
||||
#define LRADC_STATUS_BUTTON1_PRESENT (1 << 28)
|
||||
#define LRADC_STATUS_BUTTON0_PRESENT (1 << 27)
|
||||
#define LRADC_STATUS_TEMP1_PRESENT (1 << 26)
|
||||
#define LRADC_STATUS_TEMP0_PRESENT (1 << 25)
|
||||
#define LRADC_STATUS_TOUCH_PANEL_PRESENT (1 << 24)
|
||||
#define LRADC_STATUS_CHANNEL7_PRESENT (1 << 23)
|
||||
#define LRADC_STATUS_CHANNEL6_PRESENT (1 << 22)
|
||||
#define LRADC_STATUS_CHANNEL5_PRESENT (1 << 21)
|
||||
#define LRADC_STATUS_CHANNEL4_PRESENT (1 << 20)
|
||||
#define LRADC_STATUS_CHANNEL3_PRESENT (1 << 19)
|
||||
#define LRADC_STATUS_CHANNEL2_PRESENT (1 << 18)
|
||||
#define LRADC_STATUS_CHANNEL1_PRESENT (1 << 17)
|
||||
#define LRADC_STATUS_CHANNEL0_PRESENT (1 << 16)
|
||||
#define LRADC_STATUS_BUTTON1_DETECT_RAW (1 << 2)
|
||||
#define LRADC_STATUS_BUTTON0_DETECT_RAW (1 << 1)
|
||||
#define LRADC_STATUS_TOUCH_DETECT_RAW (1 << 0)
|
||||
|
||||
#define LRADC_CH_TOGGLE (1 << 31)
|
||||
#define LRADC_CH7_TESTMODE_TOGGLE (1 << 30)
|
||||
#define LRADC_CH_ACCUMULATE (1 << 29)
|
||||
#define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24)
|
||||
#define LRADC_CH_NUM_SAMPLES_OFFSET 24
|
||||
#define LRADC_CH_VALUE_MASK 0x3ffff
|
||||
#define LRADC_CH_VALUE_OFFSET 0
|
||||
|
||||
#define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xff << 24)
|
||||
#define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24
|
||||
#define LRADC_DELAY_KICK (1 << 20)
|
||||
#define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16)
|
||||
#define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16
|
||||
#define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11)
|
||||
#define LRADC_DELAY_LOOP_COUNT_OFFSET 11
|
||||
#define LRADC_DELAY_DELAY_MASK 0x7ff
|
||||
#define LRADC_DELAY_DELAY_OFFSET 0
|
||||
|
||||
#define LRADC_DEBUG0_READONLY_MASK (0xffff << 16)
|
||||
#define LRADC_DEBUG0_READONLY_OFFSET 16
|
||||
#define LRADC_DEBUG0_STATE_MASK (0xfff << 0)
|
||||
#define LRADC_DEBUG0_STATE_OFFSET 0
|
||||
|
||||
#define LRADC_DEBUG1_REQUEST_MASK (0xff << 16)
|
||||
#define LRADC_DEBUG1_REQUEST_OFFSET 16
|
||||
#define LRADC_DEBUG1_TESTMODE_COUNT_MASK (0x1f << 8)
|
||||
#define LRADC_DEBUG1_TESTMODE_COUNT_OFFSET 8
|
||||
#define LRADC_DEBUG1_TESTMODE6 (1 << 2)
|
||||
#define LRADC_DEBUG1_TESTMODE5 (1 << 1)
|
||||
#define LRADC_DEBUG1_TESTMODE (1 << 0)
|
||||
|
||||
#define LRADC_CONVERSION_AUTOMATIC (1 << 20)
|
||||
#define LRADC_CONVERSION_SCALE_FACTOR_MASK (0x3 << 16)
|
||||
#define LRADC_CONVERSION_SCALE_FACTOR_OFFSET 16
|
||||
#define LRADC_CONVERSION_SCALE_FACTOR_NIMH (0x0 << 16)
|
||||
#define LRADC_CONVERSION_SCALE_FACTOR_DUAL_NIMH (0x1 << 16)
|
||||
#define LRADC_CONVERSION_SCALE_FACTOR_LI_ION (0x2 << 16)
|
||||
#define LRADC_CONVERSION_SCALE_FACTOR_ALT_LI_ION (0x3 << 16)
|
||||
#define LRADC_CONVERSION_SCALED_BATT_VOLTAGE_MASK 0x3ff
|
||||
#define LRADC_CONVERSION_SCALED_BATT_VOLTAGE_OFFSET 0
|
||||
|
||||
#define LRADC_CTRL4_LRADC7SELECT_MASK (0xf << 28)
|
||||
#define LRADC_CTRL4_LRADC7SELECT_OFFSET 28
|
||||
#define LRADC_CTRL4_LRADC7SELECT_CHANNEL0 (0x0 << 28)
|
||||
#define LRADC_CTRL4_LRADC7SELECT_CHANNEL1 (0x1 << 28)
|
||||
#define LRADC_CTRL4_LRADC7SELECT_CHANNEL2 (0x2 << 28)
|
||||
#define LRADC_CTRL4_LRADC7SELECT_CHANNEL3 (0x3 << 28)
|
||||
#define LRADC_CTRL4_LRADC7SELECT_CHANNEL4 (0x4 << 28)
|
||||
#define LRADC_CTRL4_LRADC7SELECT_CHANNEL5 (0x5 << 28)
|
||||
#define LRADC_CTRL4_LRADC7SELECT_CHANNEL6 (0x6 << 28)
|
||||
#define LRADC_CTRL4_LRADC7SELECT_CHANNEL7 (0x7 << 28)
|
||||
#define LRADC_CTRL4_LRADC7SELECT_CHANNEL8 (0x8 << 28)
|
||||
#define LRADC_CTRL4_LRADC7SELECT_CHANNEL9 (0x9 << 28)
|
||||
#define LRADC_CTRL4_LRADC7SELECT_CHANNEL10 (0xa << 28)
|
||||
#define LRADC_CTRL4_LRADC7SELECT_CHANNEL11 (0xb << 28)
|
||||
#define LRADC_CTRL4_LRADC7SELECT_CHANNEL12 (0xc << 28)
|
||||
#define LRADC_CTRL4_LRADC7SELECT_CHANNEL13 (0xd << 28)
|
||||
#define LRADC_CTRL4_LRADC7SELECT_CHANNEL14 (0xe << 28)
|
||||
#define LRADC_CTRL4_LRADC7SELECT_CHANNEL15 (0xf << 28)
|
||||
#define LRADC_CTRL4_LRADC6SELECT_MASK (0xf << 24)
|
||||
#define LRADC_CTRL4_LRADC6SELECT_OFFSET 24
|
||||
#define LRADC_CTRL4_LRADC6SELECT_CHANNEL0 (0x0 << 24)
|
||||
#define LRADC_CTRL4_LRADC6SELECT_CHANNEL1 (0x1 << 24)
|
||||
#define LRADC_CTRL4_LRADC6SELECT_CHANNEL2 (0x2 << 24)
|
||||
#define LRADC_CTRL4_LRADC6SELECT_CHANNEL3 (0x3 << 24)
|
||||
#define LRADC_CTRL4_LRADC6SELECT_CHANNEL4 (0x4 << 24)
|
||||
#define LRADC_CTRL4_LRADC6SELECT_CHANNEL5 (0x5 << 24)
|
||||
#define LRADC_CTRL4_LRADC6SELECT_CHANNEL6 (0x6 << 24)
|
||||
#define LRADC_CTRL4_LRADC6SELECT_CHANNEL7 (0x7 << 24)
|
||||
#define LRADC_CTRL4_LRADC6SELECT_CHANNEL8 (0x8 << 24)
|
||||
#define LRADC_CTRL4_LRADC6SELECT_CHANNEL9 (0x9 << 24)
|
||||
#define LRADC_CTRL4_LRADC6SELECT_CHANNEL10 (0xa << 24)
|
||||
#define LRADC_CTRL4_LRADC6SELECT_CHANNEL11 (0xb << 24)
|
||||
#define LRADC_CTRL4_LRADC6SELECT_CHANNEL12 (0xc << 24)
|
||||
#define LRADC_CTRL4_LRADC6SELECT_CHANNEL13 (0xd << 24)
|
||||
#define LRADC_CTRL4_LRADC6SELECT_CHANNEL14 (0xe << 24)
|
||||
#define LRADC_CTRL4_LRADC6SELECT_CHANNEL15 (0xf << 24)
|
||||
#define LRADC_CTRL4_LRADC5SELECT_MASK (0xf << 20)
|
||||
#define LRADC_CTRL4_LRADC5SELECT_OFFSET 20
|
||||
#define LRADC_CTRL4_LRADC5SELECT_CHANNEL0 (0x0 << 20)
|
||||
#define LRADC_CTRL4_LRADC5SELECT_CHANNEL1 (0x1 << 20)
|
||||
#define LRADC_CTRL4_LRADC5SELECT_CHANNEL2 (0x2 << 20)
|
||||
#define LRADC_CTRL4_LRADC5SELECT_CHANNEL3 (0x3 << 20)
|
||||
#define LRADC_CTRL4_LRADC5SELECT_CHANNEL4 (0x4 << 20)
|
||||
#define LRADC_CTRL4_LRADC5SELECT_CHANNEL5 (0x5 << 20)
|
||||
#define LRADC_CTRL4_LRADC5SELECT_CHANNEL6 (0x6 << 20)
|
||||
#define LRADC_CTRL4_LRADC5SELECT_CHANNEL7 (0x7 << 20)
|
||||
#define LRADC_CTRL4_LRADC5SELECT_CHANNEL8 (0x8 << 20)
|
||||
#define LRADC_CTRL4_LRADC5SELECT_CHANNEL9 (0x9 << 20)
|
||||
#define LRADC_CTRL4_LRADC5SELECT_CHANNEL10 (0xa << 20)
|
||||
#define LRADC_CTRL4_LRADC5SELECT_CHANNEL11 (0xb << 20)
|
||||
#define LRADC_CTRL4_LRADC5SELECT_CHANNEL12 (0xc << 20)
|
||||
#define LRADC_CTRL4_LRADC5SELECT_CHANNEL13 (0xd << 20)
|
||||
#define LRADC_CTRL4_LRADC5SELECT_CHANNEL14 (0xe << 20)
|
||||
#define LRADC_CTRL4_LRADC5SELECT_CHANNEL15 (0xf << 20)
|
||||
#define LRADC_CTRL4_LRADC4SELECT_MASK (0xf << 16)
|
||||
#define LRADC_CTRL4_LRADC4SELECT_OFFSET 16
|
||||
#define LRADC_CTRL4_LRADC4SELECT_CHANNEL0 (0x0 << 16)
|
||||
#define LRADC_CTRL4_LRADC4SELECT_CHANNEL1 (0x1 << 16)
|
||||
#define LRADC_CTRL4_LRADC4SELECT_CHANNEL2 (0x2 << 16)
|
||||
#define LRADC_CTRL4_LRADC4SELECT_CHANNEL3 (0x3 << 16)
|
||||
#define LRADC_CTRL4_LRADC4SELECT_CHANNEL4 (0x4 << 16)
|
||||
#define LRADC_CTRL4_LRADC4SELECT_CHANNEL5 (0x5 << 16)
|
||||
#define LRADC_CTRL4_LRADC4SELECT_CHANNEL6 (0x6 << 16)
|
||||
#define LRADC_CTRL4_LRADC4SELECT_CHANNEL7 (0x7 << 16)
|
||||
#define LRADC_CTRL4_LRADC4SELECT_CHANNEL8 (0x8 << 16)
|
||||
#define LRADC_CTRL4_LRADC4SELECT_CHANNEL9 (0x9 << 16)
|
||||
#define LRADC_CTRL4_LRADC4SELECT_CHANNEL10 (0xa << 16)
|
||||
#define LRADC_CTRL4_LRADC4SELECT_CHANNEL11 (0xb << 16)
|
||||
#define LRADC_CTRL4_LRADC4SELECT_CHANNEL12 (0xc << 16)
|
||||
#define LRADC_CTRL4_LRADC4SELECT_CHANNEL13 (0xd << 16)
|
||||
#define LRADC_CTRL4_LRADC4SELECT_CHANNEL14 (0xe << 16)
|
||||
#define LRADC_CTRL4_LRADC4SELECT_CHANNEL15 (0xf << 16)
|
||||
#define LRADC_CTRL4_LRADC3SELECT_MASK (0xf << 12)
|
||||
#define LRADC_CTRL4_LRADC3SELECT_OFFSET 12
|
||||
#define LRADC_CTRL4_LRADC3SELECT_CHANNEL0 (0x0 << 12)
|
||||
#define LRADC_CTRL4_LRADC3SELECT_CHANNEL1 (0x1 << 12)
|
||||
#define LRADC_CTRL4_LRADC3SELECT_CHANNEL2 (0x2 << 12)
|
||||
#define LRADC_CTRL4_LRADC3SELECT_CHANNEL3 (0x3 << 12)
|
||||
#define LRADC_CTRL4_LRADC3SELECT_CHANNEL4 (0x4 << 12)
|
||||
#define LRADC_CTRL4_LRADC3SELECT_CHANNEL5 (0x5 << 12)
|
||||
#define LRADC_CTRL4_LRADC3SELECT_CHANNEL6 (0x6 << 12)
|
||||
#define LRADC_CTRL4_LRADC3SELECT_CHANNEL7 (0x7 << 12)
|
||||
#define LRADC_CTRL4_LRADC3SELECT_CHANNEL8 (0x8 << 12)
|
||||
#define LRADC_CTRL4_LRADC3SELECT_CHANNEL9 (0x9 << 12)
|
||||
#define LRADC_CTRL4_LRADC3SELECT_CHANNEL10 (0xa << 12)
|
||||
#define LRADC_CTRL4_LRADC3SELECT_CHANNEL11 (0xb << 12)
|
||||
#define LRADC_CTRL4_LRADC3SELECT_CHANNEL12 (0xc << 12)
|
||||
#define LRADC_CTRL4_LRADC3SELECT_CHANNEL13 (0xd << 12)
|
||||
#define LRADC_CTRL4_LRADC3SELECT_CHANNEL14 (0xe << 12)
|
||||
#define LRADC_CTRL4_LRADC3SELECT_CHANNEL15 (0xf << 12)
|
||||
#define LRADC_CTRL4_LRADC2SELECT_MASK (0xf << 8)
|
||||
#define LRADC_CTRL4_LRADC2SELECT_OFFSET 8
|
||||
#define LRADC_CTRL4_LRADC2SELECT_CHANNEL0 (0x0 << 8)
|
||||
#define LRADC_CTRL4_LRADC2SELECT_CHANNEL1 (0x1 << 8)
|
||||
#define LRADC_CTRL4_LRADC2SELECT_CHANNEL2 (0x2 << 8)
|
||||
#define LRADC_CTRL4_LRADC2SELECT_CHANNEL3 (0x3 << 8)
|
||||
#define LRADC_CTRL4_LRADC2SELECT_CHANNEL4 (0x4 << 8)
|
||||
#define LRADC_CTRL4_LRADC2SELECT_CHANNEL5 (0x5 << 8)
|
||||
#define LRADC_CTRL4_LRADC2SELECT_CHANNEL6 (0x6 << 8)
|
||||
#define LRADC_CTRL4_LRADC2SELECT_CHANNEL7 (0x7 << 8)
|
||||
#define LRADC_CTRL4_LRADC2SELECT_CHANNEL8 (0x8 << 8)
|
||||
#define LRADC_CTRL4_LRADC2SELECT_CHANNEL9 (0x9 << 8)
|
||||
#define LRADC_CTRL4_LRADC2SELECT_CHANNEL10 (0xa << 8)
|
||||
#define LRADC_CTRL4_LRADC2SELECT_CHANNEL11 (0xb << 8)
|
||||
#define LRADC_CTRL4_LRADC2SELECT_CHANNEL12 (0xc << 8)
|
||||
#define LRADC_CTRL4_LRADC2SELECT_CHANNEL13 (0xd << 8)
|
||||
#define LRADC_CTRL4_LRADC2SELECT_CHANNEL14 (0xe << 8)
|
||||
#define LRADC_CTRL4_LRADC2SELECT_CHANNEL15 (0xf << 8)
|
||||
#define LRADC_CTRL4_LRADC1SELECT_MASK (0xf << 4)
|
||||
#define LRADC_CTRL4_LRADC1SELECT_OFFSET 4
|
||||
#define LRADC_CTRL4_LRADC1SELECT_CHANNEL0 (0x0 << 4)
|
||||
#define LRADC_CTRL4_LRADC1SELECT_CHANNEL1 (0x1 << 4)
|
||||
#define LRADC_CTRL4_LRADC1SELECT_CHANNEL2 (0x2 << 4)
|
||||
#define LRADC_CTRL4_LRADC1SELECT_CHANNEL3 (0x3 << 4)
|
||||
#define LRADC_CTRL4_LRADC1SELECT_CHANNEL4 (0x4 << 4)
|
||||
#define LRADC_CTRL4_LRADC1SELECT_CHANNEL5 (0x5 << 4)
|
||||
#define LRADC_CTRL4_LRADC1SELECT_CHANNEL6 (0x6 << 4)
|
||||
#define LRADC_CTRL4_LRADC1SELECT_CHANNEL7 (0x7 << 4)
|
||||
#define LRADC_CTRL4_LRADC1SELECT_CHANNEL8 (0x8 << 4)
|
||||
#define LRADC_CTRL4_LRADC1SELECT_CHANNEL9 (0x9 << 4)
|
||||
#define LRADC_CTRL4_LRADC1SELECT_CHANNEL10 (0xa << 4)
|
||||
#define LRADC_CTRL4_LRADC1SELECT_CHANNEL11 (0xb << 4)
|
||||
#define LRADC_CTRL4_LRADC1SELECT_CHANNEL12 (0xc << 4)
|
||||
#define LRADC_CTRL4_LRADC1SELECT_CHANNEL13 (0xd << 4)
|
||||
#define LRADC_CTRL4_LRADC1SELECT_CHANNEL14 (0xe << 4)
|
||||
#define LRADC_CTRL4_LRADC1SELECT_CHANNEL15 (0xf << 4)
|
||||
#define LRADC_CTRL4_LRADC0SELECT_MASK 0xf
|
||||
#define LRADC_CTRL4_LRADC0SELECT_CHANNEL0 (0x0 << 0)
|
||||
#define LRADC_CTRL4_LRADC0SELECT_CHANNEL1 (0x1 << 0)
|
||||
#define LRADC_CTRL4_LRADC0SELECT_CHANNEL2 (0x2 << 0)
|
||||
#define LRADC_CTRL4_LRADC0SELECT_CHANNEL3 (0x3 << 0)
|
||||
#define LRADC_CTRL4_LRADC0SELECT_CHANNEL4 (0x4 << 0)
|
||||
#define LRADC_CTRL4_LRADC0SELECT_CHANNEL5 (0x5 << 0)
|
||||
#define LRADC_CTRL4_LRADC0SELECT_CHANNEL6 (0x6 << 0)
|
||||
#define LRADC_CTRL4_LRADC0SELECT_CHANNEL7 (0x7 << 0)
|
||||
#define LRADC_CTRL4_LRADC0SELECT_CHANNEL8 (0x8 << 0)
|
||||
#define LRADC_CTRL4_LRADC0SELECT_CHANNEL9 (0x9 << 0)
|
||||
#define LRADC_CTRL4_LRADC0SELECT_CHANNEL10 (0xa << 0)
|
||||
#define LRADC_CTRL4_LRADC0SELECT_CHANNEL11 (0xb << 0)
|
||||
#define LRADC_CTRL4_LRADC0SELECT_CHANNEL12 (0xc << 0)
|
||||
#define LRADC_CTRL4_LRADC0SELECT_CHANNEL13 (0xd << 0)
|
||||
#define LRADC_CTRL4_LRADC0SELECT_CHANNEL14 (0xe << 0)
|
||||
#define LRADC_CTRL4_LRADC0SELECT_CHANNEL15 (0xf << 0)
|
||||
|
||||
#define LRADC_THRESHOLD_ENABLE (1 << 24)
|
||||
#define LRADC_THRESHOLD_BATTCHRG_DISABLE (1 << 23)
|
||||
#define LRADC_THRESHOLD_CHANNEL_SEL_MASK (0x7 << 20)
|
||||
#define LRADC_THRESHOLD_CHANNEL_SEL_OFFSET 20
|
||||
#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL0 (0x0 << 20)
|
||||
#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL1 (0x1 << 20)
|
||||
#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL2 (0x2 << 20)
|
||||
#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL3 (0x3 << 20)
|
||||
#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL4 (0x4 << 20)
|
||||
#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL5 (0x5 << 20)
|
||||
#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL6 (0x6 << 20)
|
||||
#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL7 (0x7 << 20)
|
||||
#define LRADC_THRESHOLD_SETTING_MASK (0x3 << 18)
|
||||
#define LRADC_THRESHOLD_SETTING_OFFSET 18
|
||||
#define LRADC_THRESHOLD_SETTING_NO_COMPARE (0x0 << 18)
|
||||
#define LRADC_THRESHOLD_SETTING_DETECT_LOW (0x1 << 18)
|
||||
#define LRADC_THRESHOLD_SETTING_DETECT_HIGH (0x2 << 18)
|
||||
#define LRADC_THRESHOLD_SETTING_RESERVED (0x3 << 18)
|
||||
#define LRADC_THRESHOLD_VALUE_MASK 0x3ffff
|
||||
#define LRADC_THRESHOLD_VALUE_OFFSET 0
|
||||
|
||||
#define LRADC_VERSION_MAJOR_MASK (0xff << 24)
|
||||
#define LRADC_VERSION_MAJOR_OFFSET 24
|
||||
#define LRADC_VERSION_MINOR_MASK (0xff << 16)
|
||||
#define LRADC_VERSION_MINOR_OFFSET 16
|
||||
#define LRADC_VERSION_STEP_MASK 0xffff
|
||||
#define LRADC_VERSION_STEP_OFFSET 0
|
||||
|
||||
#endif /* __MX28_REGS_LRADC_H__ */
|
||||
|
|
@ -0,0 +1,408 @@
|
|||
/*
|
||||
* Freescale i.MX28 Power Controller Register Definitions
|
||||
*
|
||||
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __MX28_REGS_POWER_H__
|
||||
#define __MX28_REGS_POWER_H__
|
||||
|
||||
#include <mach/regs-common.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct mxs_power_regs {
|
||||
mxs_reg_32(hw_power_ctrl)
|
||||
mxs_reg_32(hw_power_5vctrl)
|
||||
mxs_reg_32(hw_power_minpwr)
|
||||
mxs_reg_32(hw_power_charge)
|
||||
uint32_t hw_power_vdddctrl;
|
||||
uint32_t reserved_vddd[3];
|
||||
uint32_t hw_power_vddactrl;
|
||||
uint32_t reserved_vdda[3];
|
||||
uint32_t hw_power_vddioctrl;
|
||||
uint32_t reserved_vddio[3];
|
||||
uint32_t hw_power_vddmemctrl;
|
||||
uint32_t reserved_vddmem[3];
|
||||
uint32_t hw_power_dcdc4p2;
|
||||
uint32_t reserved_dcdc4p2[3];
|
||||
uint32_t hw_power_misc;
|
||||
uint32_t reserved_misc[3];
|
||||
uint32_t hw_power_dclimits;
|
||||
uint32_t reserved_dclimits[3];
|
||||
mxs_reg_32(hw_power_loopctrl)
|
||||
uint32_t hw_power_sts;
|
||||
uint32_t reserved_sts[3];
|
||||
mxs_reg_32(hw_power_speed)
|
||||
uint32_t hw_power_battmonitor;
|
||||
uint32_t reserved_battmonitor[3];
|
||||
|
||||
uint32_t reserved[4];
|
||||
|
||||
mxs_reg_32(hw_power_reset)
|
||||
};
|
||||
#endif
|
||||
|
||||
#define MX23_POWER_CTRL_CLKGATE (1 << 30)
|
||||
#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27)
|
||||
#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24)
|
||||
#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23)
|
||||
#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22)
|
||||
#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21)
|
||||
#define POWER_CTRL_PSWITCH_IRQ (1 << 20)
|
||||
#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19)
|
||||
#define POWER_CTRL_POLARITY_PSWITCH (1 << 18)
|
||||
#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17)
|
||||
#define POWER_CTRL_POLARITY_DC_OK (1 << 16)
|
||||
#define POWER_CTRL_DC_OK_IRQ (1 << 15)
|
||||
#define POWER_CTRL_ENIRQ_DC_OK (1 << 14)
|
||||
#define POWER_CTRL_BATT_BO_IRQ (1 << 13)
|
||||
#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12)
|
||||
#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11)
|
||||
#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10)
|
||||
#define POWER_CTRL_VDDA_BO_IRQ (1 << 9)
|
||||
#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8)
|
||||
#define POWER_CTRL_VDDD_BO_IRQ (1 << 7)
|
||||
#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6)
|
||||
#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5)
|
||||
#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4)
|
||||
#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3)
|
||||
#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2)
|
||||
#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1)
|
||||
#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0)
|
||||
|
||||
#define MX28_POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 30)
|
||||
#define MX28_POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 30
|
||||
#define MX28_POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 30)
|
||||
#define MX28_POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 30)
|
||||
#define MX28_POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 30)
|
||||
#define MX28_POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 30)
|
||||
|
||||
#define MX23_POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 28)
|
||||
#define MX23_POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 28
|
||||
#define MX23_POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 28)
|
||||
#define MX23_POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 28)
|
||||
#define MX23_POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 28)
|
||||
#define MX23_POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 28)
|
||||
|
||||
#define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24)
|
||||
#define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24
|
||||
#define MX28_POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x3 << 20)
|
||||
#define MX23_POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x1 << 20)
|
||||
#define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20
|
||||
#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12)
|
||||
#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12
|
||||
#define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8)
|
||||
#define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8
|
||||
#define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8)
|
||||
#define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8)
|
||||
#define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8)
|
||||
#define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8)
|
||||
#define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8)
|
||||
#define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8)
|
||||
#define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8)
|
||||
#define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8)
|
||||
#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7)
|
||||
#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6)
|
||||
#define POWER_5VCTRL_DCDC_XFER (1 << 5)
|
||||
#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4)
|
||||
#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3)
|
||||
#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2)
|
||||
#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1)
|
||||
#define POWER_5VCTRL_ENABLE_DCDC (1 << 0)
|
||||
|
||||
#define POWER_MINPWR_LOWPWR_4P2 (1 << 14)
|
||||
#define MX23_POWER_MINPWR_VDAC_DUMP_CTRL (1 << 13)
|
||||
#define POWER_MINPWR_PWD_BO (1 << 12)
|
||||
#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11)
|
||||
#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10)
|
||||
#define POWER_MINPWR_ENABLE_OSC (1 << 9)
|
||||
#define POWER_MINPWR_SELECT_OSC (1 << 8)
|
||||
#define POWER_MINPWR_VBG_OFF (1 << 7)
|
||||
#define POWER_MINPWR_DOUBLE_FETS (1 << 6)
|
||||
#define POWER_MINPWR_HALFFETS (1 << 5)
|
||||
#define POWER_MINPWR_LESSANA_I (1 << 4)
|
||||
#define POWER_MINPWR_PWD_XTAL24 (1 << 3)
|
||||
#define POWER_MINPWR_DC_STOPCLK (1 << 2)
|
||||
#define POWER_MINPWR_EN_DC_PFM (1 << 1)
|
||||
#define POWER_MINPWR_DC_HALFCLK (1 << 0)
|
||||
|
||||
#define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24)
|
||||
#define POWER_CHARGE_ADJ_VOLT_OFFSET 24
|
||||
#define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24)
|
||||
#define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24)
|
||||
#define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24)
|
||||
#define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24)
|
||||
#define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24)
|
||||
#define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24)
|
||||
#define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24)
|
||||
#define POWER_CHARGE_ENABLE_LOAD (1 << 22)
|
||||
#define MX23_POWER_CHARGE_ENABLE_CHARGER_RESISTORS (1 << 21)
|
||||
#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20)
|
||||
#define POWER_CHARGE_CHRG_STS_OFF (1 << 19)
|
||||
#define MX28_POWER_CHARGE_LIION_4P1 (1 << 18)
|
||||
#define MX23_POWER_CHARGE_USE_EXTERN_R (1 << 17)
|
||||
#define POWER_CHARGE_PWD_BATTCHRG (1 << 16)
|
||||
#define MX28_POWER_CHARGE_ENABLE_CHARGER_USB1 (1 << 13)
|
||||
#define MX28_POWER_CHARGE_ENABLE_CHARGER_USB0 (1 << 12)
|
||||
#define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8)
|
||||
#define POWER_CHARGE_STOP_ILIMIT_OFFSET 8
|
||||
#define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8)
|
||||
#define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8)
|
||||
#define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8)
|
||||
#define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8)
|
||||
#define POWER_CHARGE_BATTCHRG_I_MASK 0x3f
|
||||
#define POWER_CHARGE_BATTCHRG_I_OFFSET 0
|
||||
#define POWER_CHARGE_BATTCHRG_I_10MA 0x01
|
||||
#define POWER_CHARGE_BATTCHRG_I_20MA 0x02
|
||||
#define POWER_CHARGE_BATTCHRG_I_50MA 0x04
|
||||
#define POWER_CHARGE_BATTCHRG_I_100MA 0x08
|
||||
#define POWER_CHARGE_BATTCHRG_I_200MA 0x10
|
||||
#define POWER_CHARGE_BATTCHRG_I_400MA 0x20
|
||||
|
||||
#define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28)
|
||||
#define POWER_VDDDCTRL_ADJTN_OFFSET 28
|
||||
#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23)
|
||||
#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22)
|
||||
#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21)
|
||||
#define POWER_VDDDCTRL_DISABLE_FET (1 << 20)
|
||||
#define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16)
|
||||
#define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16
|
||||
#define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16)
|
||||
#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16)
|
||||
#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16)
|
||||
#define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16)
|
||||
#define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8)
|
||||
#define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8
|
||||
#define POWER_VDDDCTRL_TRG_MASK 0x1f
|
||||
#define POWER_VDDDCTRL_TRG_OFFSET 0
|
||||
|
||||
#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19)
|
||||
#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18)
|
||||
#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17)
|
||||
#define POWER_VDDACTRL_DISABLE_FET (1 << 16)
|
||||
#define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12)
|
||||
#define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12
|
||||
#define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12)
|
||||
#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12)
|
||||
#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12)
|
||||
#define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12)
|
||||
#define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8)
|
||||
#define POWER_VDDACTRL_BO_OFFSET_OFFSET 8
|
||||
#define POWER_VDDACTRL_TRG_MASK 0x1f
|
||||
#define POWER_VDDACTRL_TRG_OFFSET 0
|
||||
|
||||
#define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20)
|
||||
#define POWER_VDDIOCTRL_ADJTN_OFFSET 20
|
||||
#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18)
|
||||
#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17)
|
||||
#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16)
|
||||
#define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12)
|
||||
#define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12
|
||||
#define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12)
|
||||
#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12)
|
||||
#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12)
|
||||
#define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12)
|
||||
#define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8)
|
||||
#define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8
|
||||
#define POWER_VDDIOCTRL_TRG_MASK 0x1f
|
||||
#define POWER_VDDIOCTRL_TRG_OFFSET 0
|
||||
|
||||
#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10)
|
||||
#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9)
|
||||
#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8)
|
||||
#define MX28_POWER_VDDMEMCTRL_BO_OFFSET_MASK (0x7 << 5)
|
||||
#define MX28_POWER_VDDMEMCTRL_BO_OFFSET_OFFSET 5
|
||||
#define POWER_VDDMEMCTRL_TRG_MASK 0x1f
|
||||
#define POWER_VDDMEMCTRL_TRG_OFFSET 0
|
||||
|
||||
#define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28)
|
||||
#define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28
|
||||
#define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30)
|
||||
#define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30)
|
||||
#define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30)
|
||||
#define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30)
|
||||
#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28)
|
||||
#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28)
|
||||
#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28)
|
||||
#define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24)
|
||||
#define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24
|
||||
#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23)
|
||||
#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22)
|
||||
#define POWER_DCDC4P2_HYST_DIR (1 << 21)
|
||||
#define POWER_DCDC4P2_HYST_THRESH (1 << 20)
|
||||
#define POWER_DCDC4P2_TRG_MASK (0x7 << 16)
|
||||
#define POWER_DCDC4P2_TRG_OFFSET 16
|
||||
#define POWER_DCDC4P2_TRG_4V2 (0x0 << 16)
|
||||
#define POWER_DCDC4P2_TRG_4V1 (0x1 << 16)
|
||||
#define POWER_DCDC4P2_TRG_4V0 (0x2 << 16)
|
||||
#define POWER_DCDC4P2_TRG_3V9 (0x3 << 16)
|
||||
#define POWER_DCDC4P2_TRG_BATT (0x4 << 16)
|
||||
#define POWER_DCDC4P2_BO_MASK (0x1f << 8)
|
||||
#define POWER_DCDC4P2_BO_OFFSET 8
|
||||
#define POWER_DCDC4P2_CMPTRIP_MASK 0x1f
|
||||
#define POWER_DCDC4P2_CMPTRIP_OFFSET 0
|
||||
|
||||
#define POWER_MISC_FREQSEL_MASK (0x7 << 4)
|
||||
#define POWER_MISC_FREQSEL_OFFSET 4
|
||||
#define POWER_MISC_FREQSEL_20MHZ (0x1 << 4)
|
||||
#define POWER_MISC_FREQSEL_24MHZ (0x2 << 4)
|
||||
#define POWER_MISC_FREQSEL_19MHZ (0x3 << 4)
|
||||
#define POWER_MISC_FREQSEL_14MHZ (0x4 << 4)
|
||||
#define POWER_MISC_FREQSEL_18MHZ (0x5 << 4)
|
||||
#define POWER_MISC_FREQSEL_21MHZ (0x6 << 4)
|
||||
#define POWER_MISC_FREQSEL_17MHZ (0x7 << 4)
|
||||
#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3)
|
||||
#define POWER_MISC_DELAY_TIMING (1 << 2)
|
||||
#define POWER_MISC_TEST (1 << 1)
|
||||
#define POWER_MISC_SEL_PLLCLK (1 << 0)
|
||||
|
||||
#define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8)
|
||||
#define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8
|
||||
#define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f
|
||||
#define POWER_DCLIMITS_NEGLIMIT_OFFSET 0
|
||||
|
||||
#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20)
|
||||
#define POWER_LOOPCTRL_HYST_SIGN (1 << 19)
|
||||
#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18)
|
||||
#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17)
|
||||
#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16)
|
||||
#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15)
|
||||
#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14)
|
||||
#define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12)
|
||||
#define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12
|
||||
#define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12)
|
||||
#define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12)
|
||||
#define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12)
|
||||
#define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12)
|
||||
#define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8)
|
||||
#define POWER_LOOPCTRL_DC_FF_OFFSET 8
|
||||
#define POWER_LOOPCTRL_DC_R_MASK (0xf << 4)
|
||||
#define POWER_LOOPCTRL_DC_R_OFFSET 4
|
||||
#define POWER_LOOPCTRL_DC_C_MASK 0x3
|
||||
#define POWER_LOOPCTRL_DC_C_OFFSET 0
|
||||
#define POWER_LOOPCTRL_DC_C_MAX 0x0
|
||||
#define POWER_LOOPCTRL_DC_C_2X 0x1
|
||||
#define POWER_LOOPCTRL_DC_C_4X 0x2
|
||||
#define POWER_LOOPCTRL_DC_C_MIN 0x3
|
||||
|
||||
#define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24)
|
||||
#define POWER_STS_PWRUP_SOURCE_OFFSET 24
|
||||
#define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24)
|
||||
#define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24)
|
||||
#define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24)
|
||||
#define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24)
|
||||
#define POWER_STS_PSWITCH_MASK (0x3 << 20)
|
||||
#define POWER_STS_PSWITCH_OFFSET 20
|
||||
#define MX28_POWER_STS_THERMAL_WARNING (1 << 19)
|
||||
#define MX28_POWER_STS_VDDMEM_BO (1 << 18)
|
||||
#define POWER_STS_AVALID0_STATUS (1 << 17)
|
||||
#define POWER_STS_BVALID0_STATUS (1 << 16)
|
||||
#define POWER_STS_VBUSVALID0_STATUS (1 << 15)
|
||||
#define POWER_STS_SESSEND0_STATUS (1 << 14)
|
||||
#define POWER_STS_BATT_BO (1 << 13)
|
||||
#define POWER_STS_VDD5V_FAULT (1 << 12)
|
||||
#define POWER_STS_CHRGSTS (1 << 11)
|
||||
#define POWER_STS_DCDC_4P2_BO (1 << 10)
|
||||
#define POWER_STS_DC_OK (1 << 9)
|
||||
#define POWER_STS_VDDIO_BO (1 << 8)
|
||||
#define POWER_STS_VDDA_BO (1 << 7)
|
||||
#define POWER_STS_VDDD_BO (1 << 6)
|
||||
#define POWER_STS_VDD5V_GT_VDDIO (1 << 5)
|
||||
#define POWER_STS_VDD5V_DROOP (1 << 4)
|
||||
#define POWER_STS_AVALID0 (1 << 3)
|
||||
#define POWER_STS_BVALID0 (1 << 2)
|
||||
#define POWER_STS_VBUSVALID0 (1 << 1)
|
||||
#define POWER_STS_SESSEND0 (1 << 0)
|
||||
|
||||
#define MX23_POWER_SPEED_STATUS_MASK (0xff << 16)
|
||||
#define MX23_POWER_SPEED_STATUS_OFFSET 16
|
||||
#define MX28_POWER_SPEED_STATUS_MASK (0xffff << 8)
|
||||
#define MX28_POWER_SPEED_STATUS_OFFSET 8
|
||||
#define MX28_POWER_SPEED_STATUS_SEL_MASK (0x3 << 6)
|
||||
#define MX28_POWER_SPEED_STATUS_SEL_OFFSET 6
|
||||
#define MX28_POWER_SPEED_STATUS_SEL_DCDC_STAT (0x0 << 6)
|
||||
#define MX28_POWER_SPEED_STATUS_SEL_CORE_STAT (0x1 << 6)
|
||||
#define MX28_POWER_SPEED_STATUS_SEL_ARM_STAT (0x2 << 6)
|
||||
#define POWER_SPEED_CTRL_MASK 0x3
|
||||
#define POWER_SPEED_CTRL_OFFSET 0
|
||||
#define POWER_SPEED_CTRL_SS_OFF 0x0
|
||||
#define POWER_SPEED_CTRL_SS_ON 0x1
|
||||
#define POWER_SPEED_CTRL_SS_ENABLE 0x3
|
||||
|
||||
#define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16)
|
||||
#define POWER_BATTMONITOR_BATT_VAL_OFFSET 16
|
||||
#define MX28_POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN (1 << 11)
|
||||
#define POWER_BATTMONITOR_EN_BATADJ (1 << 10)
|
||||
#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9)
|
||||
#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8)
|
||||
#define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f
|
||||
#define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0
|
||||
|
||||
#define POWER_RESET_UNLOCK_MASK (0xffff << 16)
|
||||
#define POWER_RESET_UNLOCK_OFFSET 16
|
||||
#define POWER_RESET_UNLOCK_KEY (0x3e77 << 16)
|
||||
#define MX28_POWER_RESET_FASTFALL_PSWITCH_OFF (1 << 2)
|
||||
#define POWER_RESET_PWD_OFF (1 << 1)
|
||||
#define POWER_RESET_PWD (1 << 0)
|
||||
|
||||
#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3)
|
||||
#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2)
|
||||
#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1)
|
||||
#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0)
|
||||
|
||||
#define MX28_POWER_THERMAL_TEST (1 << 8)
|
||||
#define MX28_POWER_THERMAL_PWD (1 << 7)
|
||||
#define MX28_POWER_THERMAL_LOW_POWER (1 << 6)
|
||||
#define MX28_POWER_THERMAL_OFFSET_ADJ_MASK (0x3 << 4)
|
||||
#define MX28_POWER_THERMAL_OFFSET_ADJ_OFFSET 4
|
||||
#define MX28_POWER_THERMAL_OFFSET_ADJ_ENABLE (1 << 3)
|
||||
#define MX28_POWER_THERMAL_TEMP_THRESHOLD_MASK 0x7
|
||||
#define MX28_POWER_THERMAL_TEMP_THRESHOLD_OFFSET 0
|
||||
|
||||
#define MX28_POWER_USB1CTRL_AVALID1 (1 << 3)
|
||||
#define MX28_POWER_USB1CTRL_BVALID1 (1 << 2)
|
||||
#define MX28_POWER_USB1CTRL_VBUSVALID1 (1 << 1)
|
||||
#define MX28_POWER_USB1CTRL_SESSEND1 (1 << 0)
|
||||
|
||||
#define POWER_SPECIAL_TEST_MASK 0xffffffff
|
||||
#define POWER_SPECIAL_TEST_OFFSET 0
|
||||
|
||||
#define POWER_VERSION_MAJOR_MASK (0xff << 24)
|
||||
#define POWER_VERSION_MAJOR_OFFSET 24
|
||||
#define POWER_VERSION_MINOR_MASK (0xff << 16)
|
||||
#define POWER_VERSION_MINOR_OFFSET 16
|
||||
#define POWER_VERSION_STEP_MASK 0xffff
|
||||
#define POWER_VERSION_STEP_OFFSET 0
|
||||
|
||||
#define MX28_POWER_ANACLKCTRL_CLKGATE_0 (1 << 31)
|
||||
#define MX28_POWER_ANACLKCTRL_OUTDIV_MASK (0x7 << 28)
|
||||
#define MX28_POWER_ANACLKCTRL_OUTDIV_OFFSET 28
|
||||
#define MX28_POWER_ANACLKCTRL_INVERT_OUTCLK (1 << 27)
|
||||
#define MX28_POWER_ANACLKCTRL_CLKGATE_I (1 << 26)
|
||||
#define MX28_POWER_ANACLKCTRL_DITHER_OFF (1 << 10)
|
||||
#define MX28_POWER_ANACLKCTRL_SLOW_DITHER (1 << 9)
|
||||
#define MX28_POWER_ANACLKCTRL_INVERT_INCLK (1 << 8)
|
||||
#define MX28_POWER_ANACLKCTRL_INCLK_SHIFT_MASK (0x3 << 4)
|
||||
#define MX28_POWER_ANACLKCTRL_INCLK_SHIFT_OFFSET 4
|
||||
#define MX28_POWER_ANACLKCTRL_INDIV_MASK 0x7
|
||||
#define MX28_POWER_ANACLKCTRL_INDIV_OFFSET 0
|
||||
|
||||
#define MX28_POWER_REFCTRL_FASTSETTLING (1 << 26)
|
||||
#define MX28_POWER_REFCTRL_RAISE_REF (1 << 25)
|
||||
#define MX28_POWER_REFCTRL_XTAL_BGR_BIAS (1 << 24)
|
||||
#define MX28_POWER_REFCTRL_VBG_ADJ_MASK (0x7 << 20)
|
||||
#define MX28_POWER_REFCTRL_VBG_ADJ_OFFSET 20
|
||||
#define MX28_POWER_REFCTRL_LOW_PWR (1 << 19)
|
||||
#define MX28_POWER_REFCTRL_BIAS_CTRL_MASK (0x3 << 16)
|
||||
#define MX28_POWER_REFCTRL_BIAS_CTRL_OFFSET 16
|
||||
#define MX28_POWER_REFCTRL_VDDXTAL_TO_VDDD (1 << 14)
|
||||
#define MX28_POWER_REFCTRL_ADJ_ANA (1 << 13)
|
||||
#define MX28_POWER_REFCTRL_ADJ_VAG (1 << 12)
|
||||
#define MX28_POWER_REFCTRL_ANA_REFVAL_MASK (0xf << 8)
|
||||
#define MX28_POWER_REFCTRL_ANA_REFVAL_OFFSET 8
|
||||
#define MX28_POWER_REFCTRL_VAG_VAL_MASK (0xf << 4)
|
||||
#define MX28_POWER_REFCTRL_VAG_VAL_OFFSET 4
|
||||
|
||||
#endif /* __MX28_REGS_POWER_H__ */
|
||||
|
|
@ -0,0 +1,134 @@
|
|||
/*
|
||||
* Freescale i.MX28 RTC Register Definitions
|
||||
*
|
||||
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
|
||||
* on behalf of DENX Software Engineering GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __MX28_REGS_RTC_H__
|
||||
#define __MX28_REGS_RTC_H__
|
||||
|
||||
#include <mach/regs-common.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct mxs_rtc_regs {
|
||||
mxs_reg_32(hw_rtc_ctrl)
|
||||
mxs_reg_32(hw_rtc_stat)
|
||||
mxs_reg_32(hw_rtc_milliseconds)
|
||||
mxs_reg_32(hw_rtc_seconds)
|
||||
mxs_reg_32(hw_rtc_rtc_alarm)
|
||||
mxs_reg_32(hw_rtc_watchdog)
|
||||
mxs_reg_32(hw_rtc_persistent0)
|
||||
mxs_reg_32(hw_rtc_persistent1)
|
||||
mxs_reg_32(hw_rtc_persistent2)
|
||||
mxs_reg_32(hw_rtc_persistent3)
|
||||
mxs_reg_32(hw_rtc_persistent4)
|
||||
mxs_reg_32(hw_rtc_persistent5)
|
||||
mxs_reg_32(hw_rtc_debug)
|
||||
mxs_reg_32(hw_rtc_version)
|
||||
};
|
||||
#endif
|
||||
|
||||
#define RTC_CTRL_SFTRST (1 << 31)
|
||||
#define RTC_CTRL_CLKGATE (1 << 30)
|
||||
#define RTC_CTRL_SUPPRESS_COPY2ANALOG (1 << 6)
|
||||
#define RTC_CTRL_FORCE_UPDATE (1 << 5)
|
||||
#define RTC_CTRL_WATCHDOGEN (1 << 4)
|
||||
#define RTC_CTRL_ONEMSEC_IRQ (1 << 3)
|
||||
#define RTC_CTRL_ALARM_IRQ (1 << 2)
|
||||
#define RTC_CTRL_ONEMSEC_IRQ_EN (1 << 1)
|
||||
#define RTC_CTRL_ALARM_IRQ_EN (1 << 0)
|
||||
|
||||
#define RTC_STAT_RTC_PRESENT (1 << 31)
|
||||
#define RTC_STAT_ALARM_PRESENT (1 << 30)
|
||||
#define RTC_STAT_WATCHDOG_PRESENT (1 << 29)
|
||||
#define RTC_STAT_XTAL32000_PRESENT (1 << 28)
|
||||
#define RTC_STAT_XTAL32768_PRESENT (1 << 27)
|
||||
#define RTC_STAT_STALE_REGS_MASK (0xff << 16)
|
||||
#define RTC_STAT_STALE_REGS_OFFSET 16
|
||||
#define RTC_STAT_NEW_REGS_MASK (0xff << 8)
|
||||
#define RTC_STAT_NEW_REGS_OFFSET 8
|
||||
|
||||
#define RTC_MILLISECONDS_COUNT_MASK 0xffffffff
|
||||
#define RTC_MILLISECONDS_COUNT_OFFSET 0
|
||||
|
||||
#define RTC_SECONDS_COUNT_MASK 0xffffffff
|
||||
#define RTC_SECONDS_COUNT_OFFSET 0
|
||||
|
||||
#define RTC_ALARM_VALUE_MASK 0xffffffff
|
||||
#define RTC_ALARM_VALUE_OFFSET 0
|
||||
|
||||
#define RTC_WATCHDOG_COUNT_MASK 0xffffffff
|
||||
#define RTC_WATCHDOG_COUNT_OFFSET 0
|
||||
|
||||
#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_MASK (0xf << 28)
|
||||
#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_OFFSET 28
|
||||
#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V83 (0x0 << 28)
|
||||
#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V78 (0x1 << 28)
|
||||
#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V73 (0x2 << 28)
|
||||
#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V68 (0x3 << 28)
|
||||
#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V62 (0x4 << 28)
|
||||
#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V57 (0x5 << 28)
|
||||
#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V52 (0x6 << 28)
|
||||
#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V48 (0x7 << 28)
|
||||
#define RTC_PERSISTENT0_EXTERNAL_RESET (1 << 21)
|
||||
#define RTC_PERSISTENT0_THERMAL_RESET (1 << 20)
|
||||
#define RTC_PERSISTENT0_ENABLE_LRADC_PWRUP (1 << 18)
|
||||
#define RTC_PERSISTENT0_AUTO_RESTART (1 << 17)
|
||||
#define RTC_PERSISTENT0_DISABLE_PSWITCH (1 << 16)
|
||||
#define RTC_PERSISTENT0_LOWERBIAS_MASK (0xf << 14)
|
||||
#define RTC_PERSISTENT0_LOWERBIAS_OFFSET 14
|
||||
#define RTC_PERSISTENT0_LOWERBIAS_NOMINAL (0x0 << 14)
|
||||
#define RTC_PERSISTENT0_LOWERBIAS_M25P (0x1 << 14)
|
||||
#define RTC_PERSISTENT0_LOWERBIAS_M50P (0x3 << 14)
|
||||
#define RTC_PERSISTENT0_DISABLE_XTALOK (1 << 13)
|
||||
#define RTC_PERSISTENT0_MSEC_RES_MASK (0x1f << 8)
|
||||
#define RTC_PERSISTENT0_MSEC_RES_OFFSET 8
|
||||
#define RTC_PERSISTENT0_MSEC_RES_1MS (0x01 << 8)
|
||||
#define RTC_PERSISTENT0_MSEC_RES_2MS (0x02 << 8)
|
||||
#define RTC_PERSISTENT0_MSEC_RES_4MS (0x04 << 8)
|
||||
#define RTC_PERSISTENT0_MSEC_RES_8MS (0x08 << 8)
|
||||
#define RTC_PERSISTENT0_MSEC_RES_16MS (0x10 << 8)
|
||||
#define RTC_PERSISTENT0_ALARM_WAKE (1 << 7)
|
||||
#define RTC_PERSISTENT0_XTAL32_FREQ (1 << 6)
|
||||
#define RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5)
|
||||
#define RTC_PERSISTENT0_XTAL24KHZ_PWRUP (1 << 4)
|
||||
#define RTC_PERSISTENT0_LCK_SECS (1 << 3)
|
||||
#define RTC_PERSISTENT0_ALARM_EN (1 << 2)
|
||||
#define RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1)
|
||||
#define RTC_PERSISTENT0_CLOCKSOURCE (1 << 0)
|
||||
|
||||
#define RTC_PERSISTENT1_GENERAL_MASK 0xffffffff
|
||||
#define RTC_PERSISTENT1_GENERAL_OFFSET 0
|
||||
#define RTC_PERSISTENT1_GENERAL_OTG_ALT_ROLE 0x0080
|
||||
#define RTC_PERSISTENT1_GENERAL_OTG_HNP 0x0100
|
||||
#define RTC_PERSISTENT1_GENERAL_USB_LPM 0x0200
|
||||
#define RTC_PERSISTENT1_GENERAL_SKIP_CHECKDISK 0x0400
|
||||
#define RTC_PERSISTENT1_GENERAL_USB_BOOT_PLAYER 0x0800
|
||||
#define RTC_PERSISTENT1_GENERAL_ENUM_500MA_2X 0x1000
|
||||
|
||||
#define RTC_PERSISTENT2_GENERAL_MASK 0xffffffff
|
||||
#define RTC_PERSISTENT2_GENERAL_OFFSET 0
|
||||
|
||||
#define RTC_PERSISTENT3_GENERAL_MASK 0xffffffff
|
||||
#define RTC_PERSISTENT3_GENERAL_OFFSET 0
|
||||
|
||||
#define RTC_PERSISTENT4_GENERAL_MASK 0xffffffff
|
||||
#define RTC_PERSISTENT4_GENERAL_OFFSET 0
|
||||
|
||||
#define RTC_PERSISTENT5_GENERAL_MASK 0xffffffff
|
||||
#define RTC_PERSISTENT5_GENERAL_OFFSET 0
|
||||
|
||||
#define RTC_DEBUG_WATCHDOG_RESET_MASK (1 << 1)
|
||||
#define RTC_DEBUG_WATCHDOG_RESET (1 << 0)
|
||||
|
||||
#define RTC_VERSION_MAJOR_MASK (0xff << 24)
|
||||
#define RTC_VERSION_MAJOR_OFFSET 24
|
||||
#define RTC_VERSION_MINOR_MASK (0xff << 16)
|
||||
#define RTC_VERSION_MINOR_OFFSET 16
|
||||
#define RTC_VERSION_STEP_MASK 0xffff
|
||||
#define RTC_VERSION_STEP_OFFSET 0
|
||||
|
||||
#endif /* __MX28_REGS_RTC_H__ */
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* Freescale i.MX28 Battery measurement init
|
||||
*
|
||||
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
|
||||
* on behalf of DENX Software Engineering GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <asm/io.h>
|
||||
#include <mach/imx-regs.h>
|
||||
#include <mach/regs-lradc.h>
|
||||
#include <mach/init.h>
|
||||
|
||||
void mxs_lradc_init(void)
|
||||
{
|
||||
struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)IMX_LRADC_BASE;
|
||||
|
||||
writel(LRADC_CTRL0_SFTRST, ®s->hw_lradc_ctrl0_clr);
|
||||
writel(LRADC_CTRL0_CLKGATE, ®s->hw_lradc_ctrl0_clr);
|
||||
writel(LRADC_CTRL0_ONCHIP_GROUNDREF, ®s->hw_lradc_ctrl0_clr);
|
||||
|
||||
clrsetbits_le32(®s->hw_lradc_ctrl3,
|
||||
LRADC_CTRL3_CYCLE_TIME_MASK,
|
||||
LRADC_CTRL3_CYCLE_TIME_6MHZ);
|
||||
|
||||
clrsetbits_le32(®s->hw_lradc_ctrl4,
|
||||
LRADC_CTRL4_LRADC7SELECT_MASK |
|
||||
LRADC_CTRL4_LRADC6SELECT_MASK,
|
||||
LRADC_CTRL4_LRADC7SELECT_CHANNEL7 |
|
||||
LRADC_CTRL4_LRADC6SELECT_CHANNEL10);
|
||||
}
|
||||
|
||||
void mxs_lradc_enable_batt_measurement(void)
|
||||
{
|
||||
struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)IMX_LRADC_BASE;
|
||||
|
||||
/* Check if the channel is present at all. */
|
||||
if (!(readl(®s->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT))
|
||||
return;
|
||||
|
||||
writel(LRADC_CTRL1_LRADC7_IRQ_EN, ®s->hw_lradc_ctrl1_clr);
|
||||
writel(LRADC_CTRL1_LRADC7_IRQ, ®s->hw_lradc_ctrl1_clr);
|
||||
|
||||
clrsetbits_le32(®s->hw_lradc_conversion,
|
||||
LRADC_CONVERSION_SCALE_FACTOR_MASK,
|
||||
LRADC_CONVERSION_SCALE_FACTOR_LI_ION);
|
||||
writel(LRADC_CONVERSION_AUTOMATIC, ®s->hw_lradc_conversion_set);
|
||||
|
||||
/* Configure the channel. */
|
||||
writel((1 << 7) << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
|
||||
®s->hw_lradc_ctrl2_clr);
|
||||
writel(0xffffffff, ®s->hw_lradc_ch7_clr);
|
||||
clrbits_le32(®s->hw_lradc_ch7, LRADC_CH_NUM_SAMPLES_MASK);
|
||||
writel(LRADC_CH_ACCUMULATE, ®s->hw_lradc_ch7_clr);
|
||||
|
||||
/* Schedule the channel. */
|
||||
writel(1 << 7, ®s->hw_lradc_ctrl0_set);
|
||||
|
||||
/* Start the channel sampling. */
|
||||
writel(((1 << 7) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) |
|
||||
((1 << 3) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) |
|
||||
100, ®s->hw_lradc_delay3);
|
||||
|
||||
writel(0xffffffff, ®s->hw_lradc_ch7_clr);
|
||||
|
||||
writel(LRADC_DELAY_KICK, ®s->hw_lradc_delay3_set);
|
||||
}
|
||||
|
|
@ -0,0 +1,371 @@
|
|||
/*
|
||||
* Freescale i.MX28 RAM init
|
||||
*
|
||||
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
|
||||
* on behalf of DENX Software Engineering GmbH
|
||||
*
|
||||
* Copyright 2013 Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <io.h>
|
||||
#include <mach/imx-regs.h>
|
||||
#include <linux/compiler.h>
|
||||
|
||||
#include <mach/init.h>
|
||||
#include <mach/regs-power-mx28.h>
|
||||
#if defined CONFIG_ARCH_IMX23
|
||||
# include <mach/regs-clkctrl-mx23.h>
|
||||
#endif
|
||||
#if defined CONFIG_ARCH_IMX28
|
||||
# include <mach/regs-clkctrl-mx28.h>
|
||||
#endif
|
||||
|
||||
/* 1 second delay should be plenty of time for block reset. */
|
||||
#define RESET_MAX_TIMEOUT 1000000
|
||||
|
||||
#define MXS_BLOCK_SFTRST (1 << 31)
|
||||
#define MXS_BLOCK_CLKGATE (1 << 30)
|
||||
|
||||
int mxs_early_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
|
||||
int timeout)
|
||||
{
|
||||
while (--timeout) {
|
||||
if ((readl(®->reg) & mask) == mask)
|
||||
break;
|
||||
mxs_early_delay(1);
|
||||
}
|
||||
|
||||
return !timeout;
|
||||
}
|
||||
|
||||
int mxs_early_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
|
||||
int timeout)
|
||||
{
|
||||
while (--timeout) {
|
||||
if ((readl(®->reg) & mask) == 0)
|
||||
break;
|
||||
mxs_early_delay(1);
|
||||
}
|
||||
|
||||
return !timeout;
|
||||
}
|
||||
|
||||
int mxs_early_reset_block(struct mxs_register_32 *reg)
|
||||
{
|
||||
/* Clear SFTRST */
|
||||
writel(MXS_BLOCK_SFTRST, ®->reg_clr);
|
||||
|
||||
if (mxs_early_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
|
||||
return 1;
|
||||
|
||||
/* Clear CLKGATE */
|
||||
writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
|
||||
|
||||
/* Set SFTRST */
|
||||
writel(MXS_BLOCK_SFTRST, ®->reg_set);
|
||||
|
||||
/* Wait for CLKGATE being set */
|
||||
if (mxs_early_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
|
||||
return 1;
|
||||
|
||||
/* Clear SFTRST */
|
||||
writel(MXS_BLOCK_SFTRST, ®->reg_clr);
|
||||
|
||||
if (mxs_early_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
|
||||
return 1;
|
||||
|
||||
/* Clear CLKGATE */
|
||||
writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
|
||||
|
||||
if (mxs_early_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint32_t mx28_dram_vals[] = {
|
||||
/*
|
||||
* i.MX28 DDR2 at 200MHz
|
||||
*/
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000100, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00010101, 0x01010101,
|
||||
0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101,
|
||||
0x00000100, 0x00000100, 0x00000000, 0x00000002,
|
||||
0x01010000, 0x07080403, 0x06005003, 0x0a0000c8,
|
||||
0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612,
|
||||
0x02030202, 0x00c8001c, 0x00000000, 0x00000000,
|
||||
0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
|
||||
0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
|
||||
0x00000003, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000612, 0x01000F02,
|
||||
0x06120612, 0x00000200, 0x00020007, 0xf4004a27,
|
||||
0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07000300,
|
||||
0x07000300, 0x07400300, 0x07400300, 0x00000005,
|
||||
0x00000000, 0x00000000, 0x01000000, 0x01020408,
|
||||
0x08040201, 0x000f1133, 0x00000000, 0x00001f04,
|
||||
0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
|
||||
0x00001f04, 0x00001f04, 0x00001f04, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00010000, 0x00030404,
|
||||
0x00000003, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x01010000,
|
||||
0x01000000, 0x03030000, 0x00010303, 0x01020202,
|
||||
0x00000000, 0x02040303, 0x21002103, 0x00061200,
|
||||
0x06120612, 0x04420442, 0x04420442, 0x00040004,
|
||||
0x00040004, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0xffffffff
|
||||
};
|
||||
|
||||
/*
|
||||
* i.MX23 DDR at 133MHz
|
||||
*/
|
||||
uint32_t mx23_dram_vals[] = {
|
||||
0x01010001, 0x00010100, 0x01000101, 0x00000001,
|
||||
0x00000101, 0x00000000, 0x00010000, 0x01000001,
|
||||
0x00000000, 0x00000001, 0x07000200, 0x00070202,
|
||||
0x02020000, 0x04040a01, 0x00000201, 0x02040000,
|
||||
0x02000000, 0x19000f08, 0x0d0d0000, 0x02021313,
|
||||
0x02061521, 0x0000000a, 0x00080008, 0x00200020,
|
||||
0x00200020, 0x00200020, 0x000003f7, 0x00000000,
|
||||
0x00000000, 0x00000020, 0x00000020, 0x00c80000,
|
||||
0x000a23cd, 0x000000c8, 0x00006665, 0x00000000,
|
||||
0x00000101, 0x00040001, 0x00000000, 0x00000000,
|
||||
0x00010000
|
||||
};
|
||||
|
||||
static void mx28_initialize_dram_values(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mx28_dram_vals); i++)
|
||||
writel(mx28_dram_vals[i], IMX_SDRAMC_BASE + (4 * i));
|
||||
}
|
||||
|
||||
static void mx23_initialize_dram_values(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/*
|
||||
* HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as
|
||||
* per FSL bootlets code.
|
||||
*
|
||||
* mx23 Reference Manual marks HW_DRAM_CTL27 and HW_DRAM_CTL28 as
|
||||
* "reserved".
|
||||
* HW_DRAM_CTL8 is setup as the last element.
|
||||
* So skip the initialization of these HW_DRAM_CTL registers.
|
||||
*/
|
||||
for (i = 0; i < ARRAY_SIZE(mx23_dram_vals); i++) {
|
||||
if (i == 8 || i == 27 || i == 28 || i == 35)
|
||||
continue;
|
||||
writel(mx23_dram_vals[i], IMX_SDRAMC_BASE + (4 * i));
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last
|
||||
* element to be set
|
||||
*/
|
||||
writel((1 << 24), IMX_SDRAMC_BASE + (4 * 8));
|
||||
}
|
||||
|
||||
void mxs_mem_init_clock(unsigned char divider)
|
||||
{
|
||||
struct mxs_clkctrl_regs *clkctrl_regs =
|
||||
(struct mxs_clkctrl_regs *)IMX_CCM_BASE;
|
||||
|
||||
/* Gate EMI clock */
|
||||
writeb(CLKCTRL_FRAC_CLKGATE,
|
||||
&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]);
|
||||
|
||||
/* Set fractional divider for ref_emi */
|
||||
writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK),
|
||||
&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
|
||||
|
||||
/* Ungate EMI clock */
|
||||
writeb(CLKCTRL_FRAC_CLKGATE,
|
||||
&clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]);
|
||||
|
||||
mxs_early_delay(11000);
|
||||
|
||||
/* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */
|
||||
writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) |
|
||||
(1 << CLKCTRL_EMI_DIV_XTAL_OFFSET),
|
||||
&clkctrl_regs->hw_clkctrl_emi);
|
||||
|
||||
/* Unbypass EMI */
|
||||
writel(CLKCTRL_CLKSEQ_BYPASS_EMI,
|
||||
&clkctrl_regs->hw_clkctrl_clkseq_clr);
|
||||
|
||||
mxs_early_delay(10000);
|
||||
}
|
||||
|
||||
void mxs_mem_setup_cpu_and_hbus(void)
|
||||
{
|
||||
struct mxs_clkctrl_regs *clkctrl_regs =
|
||||
(struct mxs_clkctrl_regs *)IMX_CCM_BASE;
|
||||
|
||||
/* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
|
||||
* and ungate CPU clock */
|
||||
writeb(19 & CLKCTRL_FRAC_FRAC_MASK,
|
||||
(uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
|
||||
|
||||
/* Set CPU bypass */
|
||||
writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
|
||||
&clkctrl_regs->hw_clkctrl_clkseq_set);
|
||||
|
||||
/* HBUS = 151MHz */
|
||||
writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set);
|
||||
writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK,
|
||||
&clkctrl_regs->hw_clkctrl_hbus_clr);
|
||||
|
||||
mxs_early_delay(10000);
|
||||
|
||||
/* CPU clock divider = 1 */
|
||||
clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu,
|
||||
CLKCTRL_CPU_DIV_CPU_MASK, 1);
|
||||
|
||||
/* Disable CPU bypass */
|
||||
writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
|
||||
&clkctrl_regs->hw_clkctrl_clkseq_clr);
|
||||
|
||||
mxs_early_delay(15000);
|
||||
}
|
||||
|
||||
void mxs_mem_setup_vdda(void)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)IMX_POWER_BASE;
|
||||
|
||||
writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
|
||||
(0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
|
||||
POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW,
|
||||
&power_regs->hw_power_vddactrl);
|
||||
}
|
||||
|
||||
static void mx23_mem_setup_vddmem(void)
|
||||
{
|
||||
struct mxs_power_regs *power_regs =
|
||||
(struct mxs_power_regs *)IMX_POWER_BASE;
|
||||
|
||||
/* We must wait before and after disabling the current limiter! */
|
||||
mxs_early_delay(10000);
|
||||
|
||||
clrbits_le32(&power_regs->hw_power_vddmemctrl,
|
||||
POWER_VDDMEMCTRL_ENABLE_ILIMIT);
|
||||
|
||||
mxs_early_delay(10000);
|
||||
}
|
||||
|
||||
void mx23_mem_init(void)
|
||||
{
|
||||
mxs_early_delay(11000);
|
||||
|
||||
/* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */
|
||||
mxs_mem_init_clock(33);
|
||||
|
||||
mxs_mem_setup_vdda();
|
||||
|
||||
/*
|
||||
* Reset/ungate the EMI block. This is essential, otherwise the system
|
||||
* suffers from memory instability. This thing is mx23 specific and is
|
||||
* no longer present on mx28.
|
||||
*/
|
||||
mxs_early_reset_block((struct mxs_register_32 *)IMX_EMI_BASE);
|
||||
|
||||
mx23_mem_setup_vddmem();
|
||||
|
||||
/*
|
||||
* Configure the DRAM registers
|
||||
*/
|
||||
|
||||
/* Clear START and SREFRESH bit from DRAM_CTL8 */
|
||||
clrbits_le32(IMX_SDRAMC_BASE + 0x20, (1 << 16) | (1 << 8));
|
||||
|
||||
mx23_initialize_dram_values();
|
||||
|
||||
/* Set START bit in DRAM_CTL8 */
|
||||
setbits_le32(IMX_SDRAMC_BASE + 0x20, 1 << 16);
|
||||
|
||||
clrbits_le32(IMX_SDRAMC_BASE + 0x40, 1 << 17);
|
||||
|
||||
/* Wait for EMI_STAT bit DRAM_HALTED */
|
||||
for (;;) {
|
||||
if (!(readl(IMX_EMI_BASE + 0x10) & (1 << 1)))
|
||||
break;
|
||||
mxs_early_delay(1000);
|
||||
}
|
||||
|
||||
/* Adjust EMI port priority. */
|
||||
clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);
|
||||
mxs_early_delay(20000);
|
||||
|
||||
setbits_le32(IMX_SDRAMC_BASE + 0x40, 1 << 19);
|
||||
setbits_le32(IMX_SDRAMC_BASE + 0x40, 1 << 11);
|
||||
|
||||
mxs_early_delay(10000);
|
||||
|
||||
mxs_mem_setup_cpu_and_hbus();
|
||||
}
|
||||
|
||||
#define PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2 (0x3 << 16)
|
||||
|
||||
void mx28_mem_init(void)
|
||||
{
|
||||
mxs_early_delay(11000);
|
||||
|
||||
/* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */
|
||||
mxs_mem_init_clock(21);
|
||||
|
||||
mxs_mem_setup_vdda();
|
||||
|
||||
/* Set DDR2 mode */
|
||||
writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
|
||||
IMX_IOMUXC_BASE + 0x1b80);
|
||||
|
||||
/*
|
||||
* Configure the DRAM registers
|
||||
*/
|
||||
|
||||
/* Clear START bit from DRAM_CTL16 */
|
||||
clrbits_le32(IMX_SDRAMC_BASE + 0x40, 1);
|
||||
|
||||
mx28_initialize_dram_values();
|
||||
|
||||
/* Clear SREFRESH bit from DRAM_CTL17 */
|
||||
clrbits_le32(IMX_SDRAMC_BASE + 0x44, 1);
|
||||
|
||||
/* Set START bit in DRAM_CTL16 */
|
||||
setbits_le32(IMX_SDRAMC_BASE + 0x40, 1);
|
||||
|
||||
/* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */
|
||||
while (!(readl(IMX_SDRAMC_BASE + 0xe8) & (1 << 20)))
|
||||
;
|
||||
|
||||
mxs_early_delay(10000);
|
||||
|
||||
mxs_mem_setup_cpu_and_hbus();
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue