dts: update to v3.17-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
7955f43151
commit
a595ff6eea
|
|
@ -0,0 +1,7 @@
|
|||
Adapteva Platforms Device Tree Bindings
|
||||
---------------------------------------
|
||||
|
||||
Parallella board
|
||||
|
||||
Required root node properties:
|
||||
- compatible = "adapteva,parallella";
|
||||
|
|
@ -86,3 +86,9 @@ Interrupt controllers:
|
|||
compatible = "arm,versatile-sic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
Required nodes:
|
||||
|
||||
- core-module: the root node to the Versatile platforms must have
|
||||
a core-module with regs and the compatible strings
|
||||
"arm,core-module-versatile", "syscon"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,14 @@
|
|||
Marvell Armada 38x CA9 MPcore SoC Controller
|
||||
============================================
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should be "marvell,armada-380-mpcore-soc-ctrl".
|
||||
|
||||
- reg: should be the register base and length as documented in the
|
||||
datasheet for the CA9 MPcore SoC Control registers
|
||||
|
||||
mpcore-soc-ctrl@20d20 {
|
||||
compatible = "marvell,armada-380-mpcore-soc-ctrl";
|
||||
reg = <0x20d20 0x6c>;
|
||||
};
|
||||
|
|
@ -1,7 +1,10 @@
|
|||
* Power Management Controller (PMC)
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "atmel,at91rm9200-pmc"
|
||||
- compatible: Should be "atmel,<chip>-pmc".
|
||||
<chip> can be: at91rm9200, at91sam9260, at91sam9g45, at91sam9n12,
|
||||
at91sam9x5, sama5d3
|
||||
|
||||
- reg: Should contain PMC registers location and length
|
||||
|
||||
Examples:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,36 @@
|
|||
Broadcom Kona Family CPU Enable Method
|
||||
--------------------------------------
|
||||
This binding defines the enable method used for starting secondary
|
||||
CPUs in the following Broadcom SoCs:
|
||||
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664
|
||||
|
||||
The enable method is specified by defining the following required
|
||||
properties in the "cpus" device tree node:
|
||||
- enable-method = "brcm,bcm11351-cpu-method";
|
||||
- secondary-boot-reg = <...>;
|
||||
|
||||
The secondary-boot-reg property is a u32 value that specifies the
|
||||
physical address of the register used to request the ROM holding pen
|
||||
code release a secondary CPU. The value written to the register is
|
||||
formed by encoding the target CPU id into the low bits of the
|
||||
physical start address it should jump to.
|
||||
|
||||
Example:
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "brcm,bcm11351-cpu-method";
|
||||
secondary-boot-reg = <0x3500417c>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
ARM Broadcom STB platforms Device Tree Bindings
|
||||
-----------------------------------------------
|
||||
Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
|
||||
SoC shall have the following DT organization:
|
||||
|
||||
Required root node properties:
|
||||
- compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
|
||||
|
||||
example:
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
model = "Broadcom STB (bcm7445)";
|
||||
compatible = "brcm,bcm7445", "brcm,brcmstb";
|
||||
|
||||
Further, syscon nodes that map platform-specific registers used for general
|
||||
system control is required:
|
||||
|
||||
- compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
|
||||
- compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon"
|
||||
- compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
|
||||
|
||||
example:
|
||||
rdb {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0x00 0xf0000000 0x1000000>;
|
||||
|
||||
sun_top_ctrl: syscon@404000 {
|
||||
compatible = "brcm,bcm7445-sun-top-ctrl", "syscon";
|
||||
reg = <0x404000 0x51c>;
|
||||
};
|
||||
|
||||
hif_cpubiuctrl: syscon@3e2400 {
|
||||
compatible = "brcm,bcm7445-hif-cpubiuctrl", "syscon";
|
||||
reg = <0x3e2400 0x5b4>;
|
||||
};
|
||||
|
||||
hif_continuation: syscon@452000 {
|
||||
compatible = "brcm,bcm7445-hif-continuation", "syscon";
|
||||
reg = <0x452000 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
Lastly, nodes that allow for support of SMP initialization and reboot are
|
||||
required:
|
||||
|
||||
smpboot
|
||||
-------
|
||||
Required properties:
|
||||
|
||||
- compatible
|
||||
The string "brcm,brcmstb-smpboot".
|
||||
|
||||
- syscon-cpu
|
||||
A phandle / integer array property which lets the BSP know the location
|
||||
of certain CPU power-on registers.
|
||||
|
||||
The layout of the property is as follows:
|
||||
o a phandle to the "hif_cpubiuctrl" syscon node
|
||||
o offset to the base CPU power zone register
|
||||
o offset to the base CPU reset register
|
||||
|
||||
- syscon-cont
|
||||
A phandle pointing to the syscon node which describes the CPU boot
|
||||
continuation registers.
|
||||
o a phandle to the "hif_continuation" syscon node
|
||||
|
||||
example:
|
||||
smpboot {
|
||||
compatible = "brcm,brcmstb-smpboot";
|
||||
syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
|
||||
syscon-cont = <&hif_continuation>;
|
||||
};
|
||||
|
||||
reboot
|
||||
-------
|
||||
Required properties
|
||||
|
||||
- compatible
|
||||
The string property "brcm,brcmstb-reboot".
|
||||
|
||||
- syscon
|
||||
A phandle / integer array that points to the syscon node which describes
|
||||
the general system reset registers.
|
||||
o a phandle to "sun_top_ctrl"
|
||||
o offset to the "reset source enable" register
|
||||
o offset to the "software master reset" register
|
||||
|
||||
example:
|
||||
reboot {
|
||||
compatible = "brcm,brcmstb-reboot";
|
||||
syscon = <&sun_top_ctrl 0x304 0x308>;
|
||||
};
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
* ARM CCN (Cache Coherent Network)
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: (standard compatible string) should be one of:
|
||||
"arm,ccn-504"
|
||||
"arm,ccn-508"
|
||||
|
||||
- reg: (standard registers property) physical address and size
|
||||
(16MB) of the configuration registers block
|
||||
|
||||
- interrupts: (standard interrupt property) single interrupt
|
||||
generated by the control block
|
||||
|
||||
Example:
|
||||
|
||||
ccn@0x2000000000 {
|
||||
compatible = "arm,ccn-504";
|
||||
reg = <0x20 0x00000000 0 0x1000000>;
|
||||
interrupts = <0 181 4>;
|
||||
};
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
========================================================
|
||||
Secondary CPU enable-method "marvell,berlin-smp" binding
|
||||
========================================================
|
||||
|
||||
This document describes the "marvell,berlin-smp" method for enabling secondary
|
||||
CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
|
||||
be defined in the "cpus" node.
|
||||
|
||||
Enable method name: "marvell,berlin-smp"
|
||||
Compatible machines: "marvell,berlin2" and "marvell,berlin2q"
|
||||
Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9"
|
||||
Related properties: (none)
|
||||
|
||||
Note:
|
||||
This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
|
||||
"marvell,berlin-cpu-ctrl"[1].
|
||||
|
||||
Example:
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "marvell,berlin-smp";
|
||||
|
||||
cpu@0 {
|
||||
compatible = "marvell,pj4b";
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&l2>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "marvell,pj4b";
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&l2>;
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
--
|
||||
[1] arm/marvell,berlin.txt
|
||||
|
|
@ -152,7 +152,9 @@ nodes to be present and contain the properties described below.
|
|||
"arm,cortex-a7"
|
||||
"arm,cortex-a8"
|
||||
"arm,cortex-a9"
|
||||
"arm,cortex-a12"
|
||||
"arm,cortex-a15"
|
||||
"arm,cortex-a17"
|
||||
"arm,cortex-a53"
|
||||
"arm,cortex-a57"
|
||||
"arm,cortex-m0"
|
||||
|
|
@ -163,6 +165,7 @@ nodes to be present and contain the properties described below.
|
|||
"arm,cortex-r4"
|
||||
"arm,cortex-r5"
|
||||
"arm,cortex-r7"
|
||||
"brcm,brahma-b15"
|
||||
"faraday,fa526"
|
||||
"intel,sa110"
|
||||
"intel,sa1100"
|
||||
|
|
@ -184,6 +187,7 @@ nodes to be present and contain the properties described below.
|
|||
can be one of:
|
||||
"allwinner,sun6i-a31"
|
||||
"arm,psci"
|
||||
"brcm,brahma-b15"
|
||||
"marvell,armada-375-smp"
|
||||
"marvell,armada-380-smp"
|
||||
"marvell,armada-xp-smp"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,79 @@
|
|||
* ARM Generic Interrupt Controller, version 3
|
||||
|
||||
AArch64 SMP cores are often associated with a GICv3, providing Private
|
||||
Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
|
||||
Software Generated Interrupts (SGI), and Locality-specific Peripheral
|
||||
Interrupts (LPI).
|
||||
|
||||
Main node required properties:
|
||||
|
||||
- compatible : should at least contain "arm,gic-v3".
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt source. Must be a single cell with a value of at least 3.
|
||||
|
||||
The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
|
||||
interrupts. Other values are reserved for future use.
|
||||
|
||||
The 2nd cell contains the interrupt number for the interrupt type.
|
||||
SPI interrupts are in the range [0-987]. PPI interrupts are in the
|
||||
range [0-15].
|
||||
|
||||
The 3rd cell is the flags, encoded as follows:
|
||||
bits[3:0] trigger type and level flags.
|
||||
1 = edge triggered
|
||||
4 = level triggered
|
||||
|
||||
Cells 4 and beyond are reserved for future use. When the 1st cell
|
||||
has a value of 0 or 1, cells 4 and beyond act as padding, and may be
|
||||
ignored. It is recommended that padding cells have a value of 0.
|
||||
|
||||
- reg : Specifies base physical address(s) and size of the GIC
|
||||
registers, in the following order:
|
||||
- GIC Distributor interface (GICD)
|
||||
- GIC Redistributors (GICR), one range per redistributor region
|
||||
- GIC CPU interface (GICC)
|
||||
- GIC Hypervisor interface (GICH)
|
||||
- GIC Virtual CPU interface (GICV)
|
||||
|
||||
GICC, GICH and GICV are optional.
|
||||
|
||||
- interrupts : Interrupt source of the VGIC maintenance interrupt.
|
||||
|
||||
Optional
|
||||
|
||||
- redistributor-stride : If using padding pages, specifies the stride
|
||||
of consecutive redistributors. Must be a multiple of 64kB.
|
||||
|
||||
- #redistributor-regions: The number of independent contiguous regions
|
||||
occupied by the redistributors. Required if more than one such
|
||||
region is present.
|
||||
|
||||
Examples:
|
||||
|
||||
gic: interrupt-controller@2cf00000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x2f000000 0 0x10000>, // GICD
|
||||
<0x0 0x2f100000 0 0x200000>, // GICR
|
||||
<0x0 0x2c000000 0 0x2000>, // GICC
|
||||
<0x0 0x2c010000 0 0x2000>, // GICH
|
||||
<0x0 0x2c020000 0 0x2000>; // GICV
|
||||
interrupts = <1 9 4>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@2c010000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
redistributor-stride = <0x0 0x40000>; // 256kB stride
|
||||
#redistributor-regions = <2>;
|
||||
reg = <0x0 0x2c010000 0 0x10000>, // GICD
|
||||
<0x0 0x2d000000 0 0x800000>, // GICR 1: CPUs 0-31
|
||||
<0x0 0x2e000000 0 0x800000>; // GICR 2: CPUs 32-63
|
||||
<0x0 0x2c040000 0 0x2000>, // GICC
|
||||
<0x0 0x2c060000 0 0x2000>, // GICH
|
||||
<0x0 0x2c080000 0 0x2000>; // GICV
|
||||
interrupts = <1 9 4>;
|
||||
};
|
||||
|
|
@ -16,6 +16,7 @@ Main node required properties:
|
|||
"arm,cortex-a9-gic"
|
||||
"arm,cortex-a7-gic"
|
||||
"arm,arm11mp-gic"
|
||||
"brcm,brahma-b15-gic"
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt source. The type shall be a <u32> and the value shall be 3.
|
||||
|
|
|
|||
|
|
@ -31,6 +31,17 @@ Example:
|
|||
reboot-offset = <0x4>;
|
||||
};
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
Hisilicon CPU controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "hisilicon,cpuctrl"
|
||||
- reg : Register address and size
|
||||
|
||||
The clock registers and power registers of secondary cores are defined
|
||||
in CPU controller, especially in HIX5HD2 SoC.
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
PCTRL: Peripheral misc control register
|
||||
|
||||
Required Properties:
|
||||
|
|
|
|||
|
|
@ -24,6 +24,22 @@ SoC and board used. Currently known SoC compatibles are:
|
|||
...
|
||||
}
|
||||
|
||||
* Marvell Berlin CPU control bindings
|
||||
|
||||
CPU control register allows various operations on CPUs, like resetting them
|
||||
independently.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "marvell,berlin-cpu-ctrl"
|
||||
- reg: address and length of the register set
|
||||
|
||||
Example:
|
||||
|
||||
cpu-ctrl@f7dd0000 {
|
||||
compatible = "marvell,berlin-cpu-ctrl";
|
||||
reg = <0xf7dd0000 0x10000>;
|
||||
};
|
||||
|
||||
* Marvell Berlin2 chip control binding
|
||||
|
||||
Marvell Berlin SoCs have a chip control register set providing several
|
||||
|
|
|
|||
|
|
@ -0,0 +1,8 @@
|
|||
Mediatek MT6589 Platforms Device Tree Bindings
|
||||
|
||||
Boards with a SoC of the Mediatek MT6589 shall have the following property:
|
||||
|
||||
Required root node property:
|
||||
|
||||
compatible: must contain "mediatek,mt6589"
|
||||
|
||||
|
|
@ -10,6 +10,7 @@ Required properties:
|
|||
- compatible : Should be "ti,irq-crossbar"
|
||||
- reg: Base address and the size of the crossbar registers.
|
||||
- ti,max-irqs: Total number of irqs available at the interrupt controller.
|
||||
- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
|
||||
- ti,reg-size: Size of a individual register in bytes. Every individual
|
||||
register is assumed to be of same size. Valid sizes are 1, 2, 4.
|
||||
- ti,irqs-reserved: List of the reserved irq lines that are not muxed using
|
||||
|
|
@ -17,11 +18,46 @@ Required properties:
|
|||
so crossbar bar driver should not consider them as free
|
||||
lines.
|
||||
|
||||
Optional properties:
|
||||
- ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for
|
||||
SOC-specific hard-wiring of those irqs which unexpectedly bypasses the
|
||||
crossbar. These irqs have a crossbar register, but still cannot be used.
|
||||
|
||||
- ti,irqs-safe-map: integer which maps to a safe configuration to use
|
||||
when the interrupt controller irq is unused (when not provided, default is 0)
|
||||
|
||||
Examples:
|
||||
crossbar_mpu: @4a020000 {
|
||||
compatible = "ti,irq-crossbar";
|
||||
reg = <0x4a002a48 0x130>;
|
||||
ti,max-irqs = <160>;
|
||||
ti,max-crossbar-sources = <400>;
|
||||
ti,reg-size = <2>;
|
||||
ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
|
||||
ti,irqs-skip = <10 133 139 140>;
|
||||
};
|
||||
|
||||
Consumer:
|
||||
========
|
||||
See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and
|
||||
Documentation/devicetree/bindings/arm/gic.txt for further details.
|
||||
|
||||
An interrupt consumer on an SoC using crossbar will use:
|
||||
interrupts = <GIC_SPI request_number interrupt_level>
|
||||
When the request number is between 0 to that described by
|
||||
"ti,max-crossbar-sources", it is assumed to be a crossbar mapping. If the
|
||||
request_number is greater than "ti,max-crossbar-sources", then it is mapped as a
|
||||
quirky hardware mapping direct to GIC.
|
||||
|
||||
Example:
|
||||
device_x@0x4a023000 {
|
||||
/* Crossbar 8 used */
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
...
|
||||
};
|
||||
|
||||
device_y@0x4a033000 {
|
||||
/* Direct mapped GIC SPI 1 used */
|
||||
interrupts = <GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH>;
|
||||
...
|
||||
};
|
||||
|
|
|
|||
|
|
@ -129,6 +129,9 @@ Boards:
|
|||
- AM437x GP EVM
|
||||
compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43"
|
||||
|
||||
- AM437x SK EVM: AM437x StarterKit Evaluation Module
|
||||
compatible = "ti,am437x-sk-evm", "ti,am4372", "ti,am43"
|
||||
|
||||
- DRA742 EVM: Software Development Board for DRA742
|
||||
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,65 @@
|
|||
OMAP PRCM bindings
|
||||
|
||||
Power Reset and Clock Manager lists the device clocks and clockdomains under
|
||||
a DT hierarchy. Each TI SoC can have multiple PRCM entities listed for it,
|
||||
each describing one module and the clock hierarchy under it. see [1] for
|
||||
documentation about the individual clock/clockdomain nodes.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/ti/*
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be one of:
|
||||
"ti,am3-prcm"
|
||||
"ti,am3-scrm"
|
||||
"ti,am4-prcm"
|
||||
"ti,am4-scrm"
|
||||
"ti,omap2-prcm"
|
||||
"ti,omap2-scrm"
|
||||
"ti,omap3-prm"
|
||||
"ti,omap3-cm"
|
||||
"ti,omap3-scrm"
|
||||
"ti,omap4-cm1"
|
||||
"ti,omap4-prm"
|
||||
"ti,omap4-cm2"
|
||||
"ti,omap4-scrm"
|
||||
"ti,omap5-prm"
|
||||
"ti,omap5-cm-core-aon"
|
||||
"ti,omap5-scrm"
|
||||
"ti,omap5-cm-core"
|
||||
"ti,dra7-prm"
|
||||
"ti,dra7-cm-core-aon"
|
||||
"ti,dra7-cm-core"
|
||||
- reg: Contains PRCM module register address range
|
||||
(base address and length)
|
||||
- clocks: clocks for this module
|
||||
- clockdomains: clockdomains for this module
|
||||
|
||||
Example:
|
||||
|
||||
cm: cm@48004000 {
|
||||
compatible = "ti,omap3-cm";
|
||||
reg = <0x48004000 0x4000>;
|
||||
|
||||
cm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
cm_clockdomains: clockdomains {
|
||||
};
|
||||
}
|
||||
|
||||
&cm_clocks {
|
||||
omap2_32k_fck: omap_32k_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
&cm_clockdomains {
|
||||
core_l3_clkdm: core_l3_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&sdrc_ick>;
|
||||
};
|
||||
};
|
||||
|
|
@ -14,14 +14,21 @@ Required properties:
|
|||
for exynos4412/5250 controllers.
|
||||
Must be "samsung,exynos-adc-v2" for
|
||||
future controllers.
|
||||
Must be "samsung,exynos3250-adc" for
|
||||
controllers compatible with ADC of Exynos3250.
|
||||
- reg: Contains ADC register address range (base address and
|
||||
length) and the address of the phy enable register.
|
||||
- interrupts: Contains the interrupt information for the timer. The
|
||||
format is being dependent on which interrupt controller
|
||||
the Samsung device uses.
|
||||
- #io-channel-cells = <1>; As ADC has multiple outputs
|
||||
- clocks From common clock binding: handle to adc clock.
|
||||
- clock-names From common clock binding: Shall be "adc".
|
||||
- clocks From common clock bindings: handles to clocks specified
|
||||
in "clock-names" property, in the same order.
|
||||
- clock-names From common clock bindings: list of clock input names
|
||||
used by ADC block:
|
||||
- "adc" : ADC bus clock
|
||||
- "sclk" : ADC special clock (only for Exynos3250 and
|
||||
compatible ADC block)
|
||||
- vdd-supply VDD input supply.
|
||||
|
||||
Note: child nodes can be added for auto probing from device tree.
|
||||
|
|
@ -41,6 +48,20 @@ adc: adc@12D10000 {
|
|||
vdd-supply = <&buck5_reg>;
|
||||
};
|
||||
|
||||
Example: adding device info in dtsi file for Exynos3250 with additional sclk
|
||||
|
||||
adc: adc@126C0000 {
|
||||
compatible = "samsung,exynos3250-adc", "samsung,exynos-adc-v2;
|
||||
reg = <0x126C0000 0x100>, <0x10020718 0x4>;
|
||||
interrupts = <0 137 0>;
|
||||
#io-channel-cells = <1>;
|
||||
io-channel-ranges;
|
||||
|
||||
clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
|
||||
clock-names = "adc", "sclk";
|
||||
|
||||
vdd-supply = <&buck5_reg>;
|
||||
};
|
||||
|
||||
Example: Adding child nodes in dts file
|
||||
|
||||
|
|
|
|||
|
|
@ -7,13 +7,45 @@ Properties:
|
|||
- "samsung,exynos4212-pmu" - for Exynos4212 SoC,
|
||||
- "samsung,exynos4412-pmu" - for Exynos4412 SoC,
|
||||
- "samsung,exynos5250-pmu" - for Exynos5250 SoC,
|
||||
- "samsung,exynos5260-pmu" - for Exynos5260 SoC.
|
||||
- "samsung,exynos5410-pmu" - for Exynos5410 SoC,
|
||||
- "samsung,exynos5420-pmu" - for Exynos5420 SoC.
|
||||
second value must be always "syscon".
|
||||
|
||||
- reg : offset and length of the register set.
|
||||
|
||||
- #clock-cells : must be <1>, since PMU requires once cell as clock specifier.
|
||||
The single specifier cell is used as index to list of clocks
|
||||
provided by PMU, which is currently:
|
||||
0 : SoC clock output (CLKOUT pin)
|
||||
|
||||
- clock-names : list of clock names for particular CLKOUT mux inputs in
|
||||
following format:
|
||||
"clkoutN", where N is a decimal number corresponding to
|
||||
CLKOUT mux control bits value for given input, e.g.
|
||||
"clkout0", "clkout7", "clkout15".
|
||||
|
||||
- clocks : list of phandles and specifiers to all input clocks listed in
|
||||
clock-names property.
|
||||
|
||||
Example :
|
||||
pmu_system_controller: system-controller@10040000 {
|
||||
compatible = "samsung,exynos5250-pmu", "syscon";
|
||||
reg = <0x10040000 0x5000>;
|
||||
#clock-cells = <1>;
|
||||
clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
|
||||
"clkout4", "clkout8", "clkout9";
|
||||
clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
|
||||
<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
|
||||
<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
|
||||
<&clock CLK_XUSBXTI>;
|
||||
};
|
||||
|
||||
Example of clock consumer :
|
||||
|
||||
usb3503: usb3503@08 {
|
||||
/* ... */
|
||||
clock-names = "refclk";
|
||||
clocks = <&pmu_system_controller 0>;
|
||||
/* ... */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,9 @@
|
|||
SPEAr Misc configuration
|
||||
===========================
|
||||
SPEAr SOCs have some miscellaneous registers which are used to configure
|
||||
few properties of different peripheral controllers.
|
||||
|
||||
misc node required properties:
|
||||
|
||||
- compatible Should be "st,spear1340-misc", "syscon".
|
||||
- reg: Address range of misc space upto 8K
|
||||
|
|
@ -30,6 +30,8 @@ board-specific compatible values:
|
|||
nvidia,seaboard
|
||||
nvidia,ventana
|
||||
nvidia,whistler
|
||||
toradex,apalis_t30
|
||||
toradex,apalis_t30-eval
|
||||
toradex,colibri_t20-512
|
||||
toradex,iris
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
Xilinx Zynq EP107 Emulation Platform board
|
||||
Xilinx Zynq Platforms Device Tree Bindings
|
||||
|
||||
This board is an emulation platform for the Zynq product which is
|
||||
based on an ARM Cortex A9 processor.
|
||||
Boards with Zynq-7000 SOC based on an ARM Cortex A9 processor
|
||||
shall have the following properties.
|
||||
|
||||
Required root node properties:
|
||||
- compatible = "xlnx,zynq-ep107";
|
||||
- compatible = "xlnx,zynq-7000";
|
||||
|
|
|
|||
|
|
@ -3,28 +3,43 @@
|
|||
SATA nodes are defined to describe on-chip Serial ATA controllers.
|
||||
Each SATA controller should have its own node.
|
||||
|
||||
It is possible, but not required, to represent each port as a sub-node.
|
||||
It allows to enable each port independently when dealing with multiple
|
||||
PHYs.
|
||||
|
||||
Required properties:
|
||||
- compatible : compatible string, one of:
|
||||
- "allwinner,sun4i-a10-ahci"
|
||||
- "fsl,imx53-ahci"
|
||||
- "fsl,imx6q-ahci"
|
||||
- "hisilicon,hisi-ahci"
|
||||
- "ibm,476gtr-ahci"
|
||||
- "marvell,armada-380-ahci"
|
||||
- "snps,dwc-ahci"
|
||||
- "snps,exynos5440-ahci"
|
||||
- "snps,spear-ahci"
|
||||
- "generic-ahci"
|
||||
- interrupts : <interrupt mapping for SATA IRQ>
|
||||
- reg : <registers mapping>
|
||||
|
||||
Please note that when using "generic-ahci" you must also specify a SoC specific
|
||||
compatible:
|
||||
compatible = "manufacturer,soc-model-ahci", "generic-ahci";
|
||||
|
||||
Optional properties:
|
||||
- dma-coherent : Present if dma operations are coherent
|
||||
- clocks : a list of phandle + clock specifier pairs
|
||||
- target-supply : regulator for SATA target power
|
||||
- phys : reference to the SATA PHY node
|
||||
- phy-names : must be "sata-phy"
|
||||
|
||||
Required properties when using sub-nodes:
|
||||
- #address-cells : number of cells to encode an address
|
||||
- #size-cells : number of cells representing the size of an address
|
||||
|
||||
|
||||
Sub-nodes required properties:
|
||||
- reg : the port number
|
||||
- phys : reference to the SATA PHY node
|
||||
|
||||
"fsl,imx53-ahci", "fsl,imx6q-ahci" required properties:
|
||||
- clocks : must contain the sata, sata_ref and ahb clocks
|
||||
- clock-names : must contain "ahb" for the ahb clock
|
||||
|
||||
Examples:
|
||||
sata@ffe08000 {
|
||||
|
|
@ -40,3 +55,23 @@ Examples:
|
|||
clocks = <&pll6 0>, <&ahb_gates 25>;
|
||||
target-supply = <®_ahci_5v>;
|
||||
};
|
||||
|
||||
With sub-nodes:
|
||||
sata@f7e90000 {
|
||||
compatible = "marvell,berlin2q-achi", "generic-ahci";
|
||||
reg = <0xe90000 0x1000>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&chip CLKID_SATA>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sata0: sata-port@0 {
|
||||
reg = <0>;
|
||||
phys = <&sata_phy 0>;
|
||||
};
|
||||
|
||||
sata1: sata-port@1 {
|
||||
reg = <1>;
|
||||
phys = <&sata_phy 1>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,31 @@
|
|||
STMicroelectronics STi SATA controller
|
||||
|
||||
This binding describes a SATA device.
|
||||
|
||||
Required properties:
|
||||
- compatible : Must be "st,sti-ahci"
|
||||
- reg : Physical base addresses and length of register sets
|
||||
- interrupts : Interrupt associated with the SATA device
|
||||
- interrupt-names : Associated name must be; "hostc"
|
||||
- resets : The power-down and soft-reset lines of SATA IP
|
||||
- reset-names : Associated names must be; "pwr-dwn" and "sw-rst"
|
||||
- clocks : The phandle for the clock
|
||||
- clock-names : Associated name must be; "ahci_clk"
|
||||
- phys : The phandle for the PHY device
|
||||
- phy-names : Associated name must be; "ahci_phy"
|
||||
|
||||
Example:
|
||||
|
||||
sata0: sata@fe380000 {
|
||||
compatible = "st,sti-ahci";
|
||||
reg = <0xfe380000 0x1000>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "hostc";
|
||||
phys = <&miphy365x_phy MIPHY_PORT_0 MIPHY_TYPE_SATA>;
|
||||
phy-names = "ahci_phy";
|
||||
resets = <&powerdown STIH416_SATA0_POWERDOWN>,
|
||||
<&softreset STIH416_SATA0_SOFTRESET>;
|
||||
reset-names = "pwr-dwn", "sw-rst";
|
||||
clocks = <&clk_s_a0_ls CLK_ICN_REG>;
|
||||
clock-names = "ahci_clk";
|
||||
};
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
* Freescale i.MX AHCI SATA Controller
|
||||
|
||||
The Freescale i.MX SATA controller mostly conforms to the AHCI interface
|
||||
with some special extensions at integration level.
|
||||
|
||||
Required properties:
|
||||
- compatible : should be one of the following:
|
||||
- "fsl,imx53-ahci" for i.MX53 SATA controller
|
||||
- "fsl,imx6q-ahci" for i.MX6Q SATA controller
|
||||
- interrupts : interrupt mapping for SATA IRQ
|
||||
- reg : registers mapping
|
||||
- clocks : list of clock specifiers, must contain an entry for each
|
||||
required entry in clock-names
|
||||
- clock-names : should include "sata", "sata_ref" and "ahb" entries
|
||||
|
||||
Optional properties:
|
||||
- fsl,transmit-level-mV : transmit voltage level, in millivolts.
|
||||
- fsl,transmit-boost-mdB : transmit boost level, in milli-decibels
|
||||
- fsl,transmit-atten-16ths : transmit attenuation, in 16ths
|
||||
- fsl,receive-eq-mdB : receive equalisation, in milli-decibels
|
||||
Please refer to the technical documentation or the driver source code
|
||||
for the list of legal values for these options.
|
||||
- fsl,no-spread-spectrum : disable spread-spectrum clocking on the SATA
|
||||
link.
|
||||
|
||||
Examples:
|
||||
|
||||
sata@02200000 {
|
||||
compatible = "fsl,imx6q-ahci";
|
||||
reg = <0x02200000 0x4000>;
|
||||
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6QDL_CLK_SATA>,
|
||||
<&clks IMX6QDL_CLK_SATA_REF_100M>,
|
||||
<&clks IMX6QDL_CLK_AHB>;
|
||||
clock-names = "sata", "sata_ref", "ahb";
|
||||
};
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
Tegra124 SoC SATA AHCI controller
|
||||
|
||||
Required properties :
|
||||
- compatible : "nvidia,tegra124-ahci".
|
||||
- reg : Should contain 2 entries:
|
||||
- AHCI register set (SATA BAR5)
|
||||
- SATA register set
|
||||
- interrupts : Defines the interrupt used by SATA
|
||||
- clocks : Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names : Must include the following entries:
|
||||
- sata
|
||||
- sata-oob
|
||||
- cml1
|
||||
- pll_e
|
||||
- resets : Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names : Must include the following entries:
|
||||
- sata
|
||||
- sata-oob
|
||||
- sata-cold
|
||||
- phys : Must contain an entry for each entry in phy-names.
|
||||
See ../phy/phy-bindings.txt for details.
|
||||
- phy-names : Must include the following entries:
|
||||
- sata-phy : XUSB PADCTL SATA PHY
|
||||
- hvdd-supply : Defines the SATA HVDD regulator
|
||||
- vddio-supply : Defines the SATA VDDIO regulator
|
||||
- avdd-supply : Defines the SATA AVDD regulator
|
||||
- target-5v-supply : Defines the SATA 5V power regulator
|
||||
- target-12v-supply : Defines the SATA 12V power regulator
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
Clock bindings for ARM Integrator Core Module clocks
|
||||
Clock bindings for ARM Integrator and Versatile Core Module clocks
|
||||
|
||||
Auxilary Oscillator Clock
|
||||
|
||||
|
|
@ -12,7 +12,7 @@ parent node.
|
|||
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "arm,integrator-cm-auxosc"
|
||||
- compatible: must be "arm,integrator-cm-auxosc" or "arm,versatile-cm-auxosc"
|
||||
- #clock-cells: must be <0>
|
||||
|
||||
Optional properties:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,35 @@
|
|||
* Palmas 32KHz clocks *
|
||||
|
||||
Palmas device has two clock output pins for 32KHz, KG and KG_AUDIO.
|
||||
|
||||
This binding uses the common clock binding ./clock-bindings.txt.
|
||||
|
||||
Required properties:
|
||||
- compatible : "ti,palmas-clk32kg" for clk32kg clock
|
||||
"ti,palmas-clk32kgaudio" for clk32kgaudio clock
|
||||
- #clock-cells : shall be set to 0.
|
||||
|
||||
Optional property:
|
||||
- ti,external-sleep-control: The external enable input pins controlled the
|
||||
enable/disable of clocks. The external enable input pins ENABLE1,
|
||||
ENABLE2 and NSLEEP. The valid values for the external pins are:
|
||||
PALMAS_EXT_CONTROL_PIN_ENABLE1 for ENABLE1 pin
|
||||
PALMAS_EXT_CONTROL_PIN_ENABLE2 for ENABLE2 pin
|
||||
PALMAS_EXT_CONTROL_PIN_NSLEEP for NSLEEP pin
|
||||
Option 0 or missing this property means the clock is enabled/disabled
|
||||
via register access and these pins do not have any control.
|
||||
The macros of external control pins for DTS is defined at
|
||||
dt-bindings/mfd/palmas.h
|
||||
|
||||
Example:
|
||||
#include <dt-bindings/mfd/palmas.h>
|
||||
...
|
||||
palmas: tps65913@58 {
|
||||
...
|
||||
clk32kg: palmas_clk32k@0 {
|
||||
compatible = "ti,palmas-clk32kg";
|
||||
#clock-cells = <0>;
|
||||
ti,external-sleep-control = <PALMAS_EXT_CONTROL_PIN_NSLEEP>;
|
||||
};
|
||||
...
|
||||
};
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
* Samsung Audio Subsystem Clock Controller
|
||||
|
||||
The Samsung Audio Subsystem clock controller generates and supplies clocks
|
||||
to Audio Subsystem block available in the S5PV210 and compatible SoCs.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "samsung,s5pv210-audss-clock".
|
||||
- reg: physical base address and length of the controller's register set.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
- clocks:
|
||||
- hclk: AHB bus clock of the Audio Subsystem.
|
||||
- xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If
|
||||
not specified (i.e. xusbxti is used for PLL reference), it is fixed to
|
||||
a clock named "xxti".
|
||||
- fout_epll: Input PLL to the AudioSS block, parent of mout_audss.
|
||||
- iiscdclk0: Optional external i2s clock, parent of mout_i2s. If not
|
||||
specified, it is fixed to a clock named "iiscdclk0".
|
||||
- sclk_audio0: Audio bus clock, parent of mout_i2s.
|
||||
|
||||
- clock-names: Aliases for the above clocks. They should be "hclk",
|
||||
"xxti", "fout_epll", "iiscdclk0", and "sclk_audio0" respectively.
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/s5pv210-audss-clk.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
Example: Clock controller node.
|
||||
|
||||
clk_audss: clock-controller@c0900000 {
|
||||
compatible = "samsung,s5pv210-audss-clock";
|
||||
reg = <0xc0900000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
clock-names = "hclk", "xxti",
|
||||
"fout_epll", "sclk_audio0";
|
||||
clocks = <&clocks DOUT_HCLKP>, <&xxti>,
|
||||
<&clocks FOUT_EPLL>, <&clocks SCLK_AUDIO0>;
|
||||
};
|
||||
|
||||
Example: I2S controller node that consumes the clock generated by the clock
|
||||
controller. Refer to the standard clock bindings for information
|
||||
about 'clocks' and 'clock-names' property.
|
||||
|
||||
i2s0: i2s@03830000 {
|
||||
/* ... */
|
||||
clock-names = "iis", "i2s_opclk0",
|
||||
"i2s_opclk1";
|
||||
clocks = <&clk_audss CLK_I2S>, <&clk_audss CLK_I2S>,
|
||||
<&clk_audss CLK_DOUT_AUD_BUS>;
|
||||
/* ... */
|
||||
};
|
||||
|
|
@ -131,3 +131,39 @@ clock signal, and a UART.
|
|||
("pll" and "pll-switched").
|
||||
* The UART has its baud clock connected the external oscillator and its
|
||||
register clock connected to the PLL clock (the "pll-switched" signal)
|
||||
|
||||
==Assigned clock parents and rates==
|
||||
|
||||
Some platforms may require initial configuration of default parent clocks
|
||||
and clock frequencies. Such a configuration can be specified in a device tree
|
||||
node through assigned-clocks, assigned-clock-parents and assigned-clock-rates
|
||||
properties. The assigned-clock-parents property should contain a list of parent
|
||||
clocks in form of phandle and clock specifier pairs, the assigned-clock-parents
|
||||
property the list of assigned clock frequency values - corresponding to clocks
|
||||
listed in the assigned-clocks property.
|
||||
|
||||
To skip setting parent or rate of a clock its corresponding entry should be
|
||||
set to 0, or can be omitted if it is not followed by any non-zero entry.
|
||||
|
||||
uart@a000 {
|
||||
compatible = "fsl,imx-uart";
|
||||
reg = <0xa000 0x1000>;
|
||||
...
|
||||
clocks = <&osc 0>, <&pll 1>;
|
||||
clock-names = "baud", "register";
|
||||
|
||||
assigned-clocks = <&clkcon 0>, <&pll 2>;
|
||||
assigned-clock-parents = <&pll 2>;
|
||||
assigned-clock-rates = <0>, <460800>;
|
||||
};
|
||||
|
||||
In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and
|
||||
the <&pll 2> clock is assigned a frequency value of 460800 Hz.
|
||||
|
||||
Configuring a clock's parent and rate through the device node that consumes
|
||||
the clock can be done only for clocks that have a single user. Specifying
|
||||
conflicting parent or rate configuration in multiple consumer nodes for
|
||||
a shared clock is forbidden.
|
||||
|
||||
Configuration of common clocks, which affect multiple consumer devices can
|
||||
be similarly specified in the clock provider node.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,19 @@
|
|||
* Clock bindings for the Cirrus Logic CLPS711X CPUs
|
||||
|
||||
Required properties:
|
||||
- compatible : Shall contain "cirrus,clps711x-clk".
|
||||
- reg : Address of the internal register set.
|
||||
- startup-frequency: Factory set CPU startup frequency in HZ.
|
||||
- #clock-cells : Should be <1>.
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/clps711x-clock.h
|
||||
for the full list of CLPS711X clock IDs.
|
||||
|
||||
Example:
|
||||
clks: clks@80000000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "cirrus,ep7312-clk", "cirrus,clps711x-clk";
|
||||
reg = <0x80000000 0xc000>;
|
||||
startup-frequency = <73728000>;
|
||||
};
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
* Clock bindings for Freescale i.MX1 CPUs
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx1-ccm".
|
||||
- reg: Address and length of the register set.
|
||||
- #clock-cells: Should be <1>.
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h
|
||||
for the full list of i.MX1 clock IDs.
|
||||
|
||||
Examples:
|
||||
clks: ccm@0021b000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "fsl,imx1-ccm";
|
||||
reg = <0x0021b000 0x1000>;
|
||||
};
|
||||
|
||||
pwm: pwm@00208000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx1-pwm";
|
||||
reg = <0x00208000 0x1000>;
|
||||
interrupts = <34>;
|
||||
clocks = <&clks IMX1_CLK_DUMMY>, <&clks IMX1_CLK_PER1>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
* Clock bindings for Freescale i.MX21
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "fsl,imx21-ccm".
|
||||
- reg : Address and length of the register set.
|
||||
- interrupts : Should contain CCM interrupt.
|
||||
- #clock-cells: Should be <1>.
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h
|
||||
for the full list of i.MX21 clock IDs.
|
||||
|
||||
Examples:
|
||||
clks: ccm@10027000{
|
||||
compatible = "fsl,imx21-ccm";
|
||||
reg = <0x10027000 0x800>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
uart1: serial@1000a000 {
|
||||
compatible = "fsl,imx21-uart";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
interrupts = <20>;
|
||||
clocks = <&clks IMX21_CLK_UART1_IPG_GATE>,
|
||||
<&clks IMX21_CLK_PER1>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -7,117 +7,22 @@ Required properties:
|
|||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX27
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
-----------------------
|
||||
dummy 0
|
||||
ckih 1
|
||||
ckil 2
|
||||
mpll 3
|
||||
spll 4
|
||||
mpll_main2 5
|
||||
ahb 6
|
||||
ipg 7
|
||||
nfc_div 8
|
||||
per1_div 9
|
||||
per2_div 10
|
||||
per3_div 11
|
||||
per4_div 12
|
||||
vpu_sel 13
|
||||
vpu_div 14
|
||||
usb_div 15
|
||||
cpu_sel 16
|
||||
clko_sel 17
|
||||
cpu_div 18
|
||||
clko_div 19
|
||||
ssi1_sel 20
|
||||
ssi2_sel 21
|
||||
ssi1_div 22
|
||||
ssi2_div 23
|
||||
clko_en 24
|
||||
ssi2_ipg_gate 25
|
||||
ssi1_ipg_gate 26
|
||||
slcdc_ipg_gate 27
|
||||
sdhc3_ipg_gate 28
|
||||
sdhc2_ipg_gate 29
|
||||
sdhc1_ipg_gate 30
|
||||
scc_ipg_gate 31
|
||||
sahara_ipg_gate 32
|
||||
rtc_ipg_gate 33
|
||||
pwm_ipg_gate 34
|
||||
owire_ipg_gate 35
|
||||
lcdc_ipg_gate 36
|
||||
kpp_ipg_gate 37
|
||||
iim_ipg_gate 38
|
||||
i2c2_ipg_gate 39
|
||||
i2c1_ipg_gate 40
|
||||
gpt6_ipg_gate 41
|
||||
gpt5_ipg_gate 42
|
||||
gpt4_ipg_gate 43
|
||||
gpt3_ipg_gate 44
|
||||
gpt2_ipg_gate 45
|
||||
gpt1_ipg_gate 46
|
||||
gpio_ipg_gate 47
|
||||
fec_ipg_gate 48
|
||||
emma_ipg_gate 49
|
||||
dma_ipg_gate 50
|
||||
cspi3_ipg_gate 51
|
||||
cspi2_ipg_gate 52
|
||||
cspi1_ipg_gate 53
|
||||
nfc_baud_gate 54
|
||||
ssi2_baud_gate 55
|
||||
ssi1_baud_gate 56
|
||||
vpu_baud_gate 57
|
||||
per4_gate 58
|
||||
per3_gate 59
|
||||
per2_gate 60
|
||||
per1_gate 61
|
||||
usb_ahb_gate 62
|
||||
slcdc_ahb_gate 63
|
||||
sahara_ahb_gate 64
|
||||
lcdc_ahb_gate 65
|
||||
vpu_ahb_gate 66
|
||||
fec_ahb_gate 67
|
||||
emma_ahb_gate 68
|
||||
emi_ahb_gate 69
|
||||
dma_ahb_gate 70
|
||||
csi_ahb_gate 71
|
||||
brom_ahb_gate 72
|
||||
ata_ahb_gate 73
|
||||
wdog_ipg_gate 74
|
||||
usb_ipg_gate 75
|
||||
uart6_ipg_gate 76
|
||||
uart5_ipg_gate 77
|
||||
uart4_ipg_gate 78
|
||||
uart3_ipg_gate 79
|
||||
uart2_ipg_gate 80
|
||||
uart1_ipg_gate 81
|
||||
ckih_div1p5 82
|
||||
fpm 83
|
||||
mpll_osc_sel 84
|
||||
mpll_sel 85
|
||||
spll_gate 86
|
||||
mshc_div 87
|
||||
rtic_ipg_gate 88
|
||||
mshc_ipg_gate 89
|
||||
rtic_ahb_gate 90
|
||||
mshc_baud_gate 91
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h
|
||||
for the full list of i.MX27 clock IDs.
|
||||
|
||||
Examples:
|
||||
clks: ccm@10027000{
|
||||
compatible = "fsl,imx27-ccm";
|
||||
reg = <0x10027000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clks: ccm@10027000{
|
||||
compatible = "fsl,imx27-ccm";
|
||||
reg = <0x10027000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
uart1: serial@1000a000 {
|
||||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
interrupts = <20>;
|
||||
clocks = <&clks 81>, <&clks 61>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
uart1: serial@1000a000 {
|
||||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
interrupts = <20>;
|
||||
clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER1_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -7,223 +7,13 @@ Required properties:
|
|||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX6Q
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
---------------------------
|
||||
dummy 0
|
||||
ckil 1
|
||||
ckih 2
|
||||
osc 3
|
||||
pll2_pfd0_352m 4
|
||||
pll2_pfd1_594m 5
|
||||
pll2_pfd2_396m 6
|
||||
pll3_pfd0_720m 7
|
||||
pll3_pfd1_540m 8
|
||||
pll3_pfd2_508m 9
|
||||
pll3_pfd3_454m 10
|
||||
pll2_198m 11
|
||||
pll3_120m 12
|
||||
pll3_80m 13
|
||||
pll3_60m 14
|
||||
twd 15
|
||||
step 16
|
||||
pll1_sw 17
|
||||
periph_pre 18
|
||||
periph2_pre 19
|
||||
periph_clk2_sel 20
|
||||
periph2_clk2_sel 21
|
||||
axi_sel 22
|
||||
esai_sel 23
|
||||
asrc_sel 24
|
||||
spdif_sel 25
|
||||
gpu2d_axi 26
|
||||
gpu3d_axi 27
|
||||
gpu2d_core_sel 28
|
||||
gpu3d_core_sel 29
|
||||
gpu3d_shader_sel 30
|
||||
ipu1_sel 31
|
||||
ipu2_sel 32
|
||||
ldb_di0_sel 33
|
||||
ldb_di1_sel 34
|
||||
ipu1_di0_pre_sel 35
|
||||
ipu1_di1_pre_sel 36
|
||||
ipu2_di0_pre_sel 37
|
||||
ipu2_di1_pre_sel 38
|
||||
ipu1_di0_sel 39
|
||||
ipu1_di1_sel 40
|
||||
ipu2_di0_sel 41
|
||||
ipu2_di1_sel 42
|
||||
hsi_tx_sel 43
|
||||
pcie_axi_sel 44
|
||||
ssi1_sel 45
|
||||
ssi2_sel 46
|
||||
ssi3_sel 47
|
||||
usdhc1_sel 48
|
||||
usdhc2_sel 49
|
||||
usdhc3_sel 50
|
||||
usdhc4_sel 51
|
||||
enfc_sel 52
|
||||
emi_sel 53
|
||||
emi_slow_sel 54
|
||||
vdo_axi_sel 55
|
||||
vpu_axi_sel 56
|
||||
cko1_sel 57
|
||||
periph 58
|
||||
periph2 59
|
||||
periph_clk2 60
|
||||
periph2_clk2 61
|
||||
ipg 62
|
||||
ipg_per 63
|
||||
esai_pred 64
|
||||
esai_podf 65
|
||||
asrc_pred 66
|
||||
asrc_podf 67
|
||||
spdif_pred 68
|
||||
spdif_podf 69
|
||||
can_root 70
|
||||
ecspi_root 71
|
||||
gpu2d_core_podf 72
|
||||
gpu3d_core_podf 73
|
||||
gpu3d_shader 74
|
||||
ipu1_podf 75
|
||||
ipu2_podf 76
|
||||
ldb_di0_podf 77
|
||||
ldb_di1_podf 78
|
||||
ipu1_di0_pre 79
|
||||
ipu1_di1_pre 80
|
||||
ipu2_di0_pre 81
|
||||
ipu2_di1_pre 82
|
||||
hsi_tx_podf 83
|
||||
ssi1_pred 84
|
||||
ssi1_podf 85
|
||||
ssi2_pred 86
|
||||
ssi2_podf 87
|
||||
ssi3_pred 88
|
||||
ssi3_podf 89
|
||||
uart_serial_podf 90
|
||||
usdhc1_podf 91
|
||||
usdhc2_podf 92
|
||||
usdhc3_podf 93
|
||||
usdhc4_podf 94
|
||||
enfc_pred 95
|
||||
enfc_podf 96
|
||||
emi_podf 97
|
||||
emi_slow_podf 98
|
||||
vpu_axi_podf 99
|
||||
cko1_podf 100
|
||||
axi 101
|
||||
mmdc_ch0_axi_podf 102
|
||||
mmdc_ch1_axi_podf 103
|
||||
arm 104
|
||||
ahb 105
|
||||
apbh_dma 106
|
||||
asrc 107
|
||||
can1_ipg 108
|
||||
can1_serial 109
|
||||
can2_ipg 110
|
||||
can2_serial 111
|
||||
ecspi1 112
|
||||
ecspi2 113
|
||||
ecspi3 114
|
||||
ecspi4 115
|
||||
ecspi5 116
|
||||
enet 117
|
||||
esai 118
|
||||
gpt_ipg 119
|
||||
gpt_ipg_per 120
|
||||
gpu2d_core 121
|
||||
gpu3d_core 122
|
||||
hdmi_iahb 123
|
||||
hdmi_isfr 124
|
||||
i2c1 125
|
||||
i2c2 126
|
||||
i2c3 127
|
||||
iim 128
|
||||
enfc 129
|
||||
ipu1 130
|
||||
ipu1_di0 131
|
||||
ipu1_di1 132
|
||||
ipu2 133
|
||||
ipu2_di0 134
|
||||
ldb_di0 135
|
||||
ldb_di1 136
|
||||
ipu2_di1 137
|
||||
hsi_tx 138
|
||||
mlb 139
|
||||
mmdc_ch0_axi 140
|
||||
mmdc_ch1_axi 141
|
||||
ocram 142
|
||||
openvg_axi 143
|
||||
pcie_axi 144
|
||||
pwm1 145
|
||||
pwm2 146
|
||||
pwm3 147
|
||||
pwm4 148
|
||||
per1_bch 149
|
||||
gpmi_bch_apb 150
|
||||
gpmi_bch 151
|
||||
gpmi_io 152
|
||||
gpmi_apb 153
|
||||
sata 154
|
||||
sdma 155
|
||||
spba 156
|
||||
ssi1 157
|
||||
ssi2 158
|
||||
ssi3 159
|
||||
uart_ipg 160
|
||||
uart_serial 161
|
||||
usboh3 162
|
||||
usdhc1 163
|
||||
usdhc2 164
|
||||
usdhc3 165
|
||||
usdhc4 166
|
||||
vdo_axi 167
|
||||
vpu_axi 168
|
||||
cko1 169
|
||||
pll1_sys 170
|
||||
pll2_bus 171
|
||||
pll3_usb_otg 172
|
||||
pll4_audio 173
|
||||
pll5_video 174
|
||||
pll8_mlb 175
|
||||
pll7_usb_host 176
|
||||
pll6_enet 177
|
||||
ssi1_ipg 178
|
||||
ssi2_ipg 179
|
||||
ssi3_ipg 180
|
||||
rom 181
|
||||
usbphy1 182
|
||||
usbphy2 183
|
||||
ldb_di0_div_3_5 184
|
||||
ldb_di1_div_3_5 185
|
||||
sata_ref 186
|
||||
sata_ref_100m 187
|
||||
pcie_ref 188
|
||||
pcie_ref_125m 189
|
||||
enet_ref 190
|
||||
usbphy1_gate 191
|
||||
usbphy2_gate 192
|
||||
pll4_post_div 193
|
||||
pll5_post_div 194
|
||||
pll5_video_div 195
|
||||
eim_slow 196
|
||||
spdif 197
|
||||
cko2_sel 198
|
||||
cko2_podf 199
|
||||
cko2 200
|
||||
cko 201
|
||||
vdoa 202
|
||||
pll4_audio_div 203
|
||||
lvds1_sel 204
|
||||
lvds2_sel 205
|
||||
lvds1_gate 206
|
||||
lvds2_gate 207
|
||||
esai_ahb 208
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h
|
||||
for the full list of i.MX6 Quad and DualLite clock IDs.
|
||||
|
||||
Examples:
|
||||
|
||||
#include <dt-bindings/clock/imx6qdl-clock.h>
|
||||
|
||||
clks: ccm@020c4000 {
|
||||
compatible = "fsl,imx6q-ccm";
|
||||
reg = <0x020c4000 0x4000>;
|
||||
|
|
@ -235,7 +25,7 @@ uart1: serial@02020000 {
|
|||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02020000 0x4000>;
|
||||
interrupts = <0 26 0x04>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -3,14 +3,15 @@ Device Tree Clock bindings for cpu clock of Marvell EBU platforms
|
|||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
|
||||
- reg : Address and length of the clock complex register set
|
||||
- reg : Address and length of the clock complex register set, followed
|
||||
by address and length of the PMU DFS registers
|
||||
- #clock-cells : should be set to 1.
|
||||
- clocks : shall be the input parent clock phandle for the clock.
|
||||
|
||||
cpuclk: clock-complex@d0018700 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "marvell,armada-xp-cpu-clock";
|
||||
reg = <0xd0018700 0xA0>;
|
||||
reg = <0xd0018700 0xA0>, <0x1c054 0x10>;
|
||||
clocks = <&coreclk 1>;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -5,6 +5,8 @@ Required properties :
|
|||
- compatible : shall contain only one of the following:
|
||||
|
||||
"qcom,gcc-apq8064"
|
||||
"qcom,gcc-apq8084"
|
||||
"qcom,gcc-ipq8064"
|
||||
"qcom,gcc-msm8660"
|
||||
"qcom,gcc-msm8960"
|
||||
"qcom,gcc-msm8974"
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@ Qualcomm Multimedia Clock & Reset Controller Binding
|
|||
Required properties :
|
||||
- compatible : shall contain only one of the following:
|
||||
|
||||
"qcom,mmcc-apq8064"
|
||||
"qcom,mmcc-apq8084"
|
||||
"qcom,mmcc-msm8660"
|
||||
"qcom,mmcc-msm8960"
|
||||
"qcom,mmcc-msm8974"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,61 @@
|
|||
* Rockchip RK3188/RK3066 Clock and Reset Unit
|
||||
|
||||
The RK3188/RK3066 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
|
||||
"rockchip,rk3066a-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
|
||||
dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
|
||||
Similar macros exist for the reset sources in these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "xin27m" - 27mhz crystal input on rk3066 - optional,
|
||||
- "ext_hsadc" - external HSADC clock - optional,
|
||||
- "ext_cif0" - external camera clock - optional,
|
||||
- "ext_rmii" - external RMII clock - optional,
|
||||
- "ext_jtag" - externalJTAG clock - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: cru@20000000 {
|
||||
compatible = "rockchip,rk3188-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@10124000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x10124000 0x400>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
* Rockchip RK3288 Clock and Reset Unit
|
||||
|
||||
The RK3288 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3288-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "ext_i2s" - external I2S clock - optional,
|
||||
- "ext_hsadc" - external HSADC clock - optional,
|
||||
- "ext_edp_24m" - external display port clock - optional,
|
||||
- "ext_vip" - external VIP clock - optional,
|
||||
- "ext_isp" - external ISP clock - optional,
|
||||
- "ext_jtag" - external JTAG clock - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: cru@20000000 {
|
||||
compatible = "rockchip,rk3188-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@10124000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x10124000 0x400>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
||||
|
|
@ -6,6 +6,9 @@ This binding uses the common clock binding[1].
|
|||
|
||||
== Gate clocks ==
|
||||
|
||||
These bindings are deprecated!
|
||||
Please use the soc specific CRU bindings instead.
|
||||
|
||||
The gate registers form a continuos block which makes the dt node
|
||||
structure a matter of taste, as either all gates can be put into
|
||||
one gate clock spanning all registers or they can be divided into
|
||||
|
|
|
|||
|
|
@ -0,0 +1,78 @@
|
|||
* Samsung S5P6442/S5PC110/S5PV210 Clock Controller
|
||||
|
||||
Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock
|
||||
controller, which generates and supplies clock to various controllers
|
||||
within the SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of following:
|
||||
- "samsung,s5pv210-clock" : for clock controller of Samsung
|
||||
S5PC110/S5PV210 SoCs,
|
||||
- "samsung,s5p6442-clock" : for clock controller of Samsung
|
||||
S5P6442 SoC.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xxti": external crystal oscillator connected to XXTI and XXTO pins of
|
||||
the SoC,
|
||||
- "xusbxti": external crystal oscillator connected to XUSBXTI and XUSBXTO
|
||||
pins of the SoC,
|
||||
|
||||
A subset of above clocks available on given board shall be specified in
|
||||
board device tree, including the system base clock, as selected by XOM[0]
|
||||
pin of the SoC. Refer to generic fixed rate clock bindings
|
||||
documentation[1] for more information how to specify these clocks.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/fixed-clock.txt
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
clock: clock-controller@7e00f000 {
|
||||
compatible = "samsung,s5pv210-clock";
|
||||
reg = <0x7e00f000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example: Required external clocks:
|
||||
|
||||
xxti: clock-xxti {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "xxti";
|
||||
clock-frequency = <24000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
xusbxti: clock-xusbxti {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "xusbxti";
|
||||
clock-frequency = <24000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller (refer to the standard clock bindings for information about
|
||||
"clocks" and "clock-names" properties):
|
||||
|
||||
uart0: serial@e2900000 {
|
||||
compatible = "samsung,s5pv210-uart";
|
||||
reg = <0xe2900000 0x400>;
|
||||
interrupt-parent = <&vic1>;
|
||||
interrupts = <10>;
|
||||
clock-names = "uart", "clk_uart_baud0",
|
||||
"clk_uart_baud1";
|
||||
clocks = <&clocks UART0>, <&clocks UART0>,
|
||||
<&clocks SCLK_UART0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -24,26 +24,26 @@ Required properties:
|
|||
|
||||
Example:
|
||||
|
||||
clockgenA@fd345000 {
|
||||
clockgen-a@fd345000 {
|
||||
reg = <0xfd345000 0xb50>;
|
||||
|
||||
CLK_M_A1_DIV1: CLK_M_A1_DIV1 {
|
||||
clk_m_a1_div1: clk-m-a1-div1 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgena-divmux-c32-odf1",
|
||||
"st,clkgena-divmux";
|
||||
|
||||
clocks = <&CLK_M_A1_OSC_PREDIV>,
|
||||
<&CLK_M_A1_PLL0 1>, /* PLL0 PHI1 */
|
||||
<&CLK_M_A1_PLL1 1>; /* PLL1 PHI1 */
|
||||
clocks = <&clk_m_a1_osc_prediv>,
|
||||
<&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
|
||||
<&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
|
||||
|
||||
clock-output-names = "CLK_M_RX_ICN_TS",
|
||||
"CLK_M_RX_ICN_VDP_0",
|
||||
"", /* Unused */
|
||||
"CLK_M_PRV_T1_BUS",
|
||||
"CLK_M_ICN_REG_12",
|
||||
"CLK_M_ICN_REG_10",
|
||||
"", /* Unused */
|
||||
"CLK_M_ICN_ST231";
|
||||
clock-output-names = "clk-m-rx-icn-ts",
|
||||
"clk-m-rx-icn-vdp-0",
|
||||
"", /* unused */
|
||||
"clk-m-prv-t1-bus",
|
||||
"clk-m-icn-reg-12",
|
||||
"clk-m-icn-reg-10",
|
||||
"", /* unused */
|
||||
"clk-m-icn-st231";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ Required properties:
|
|||
"st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"
|
||||
"st,stih415-clkgen-a9-mux", "st,clkgen-mux"
|
||||
"st,stih416-clkgen-a9-mux", "st,clkgen-mux"
|
||||
|
||||
"st,stih407-clkgen-a9-mux", "st,clkgen-mux"
|
||||
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
|
||||
|
|
@ -27,10 +27,10 @@ Required properties:
|
|||
|
||||
Example:
|
||||
|
||||
CLK_M_HVA: CLK_M_HVA {
|
||||
clk_m_hva: clk-m-hva@fd690868 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
|
||||
reg = <0xfd690868 4>;
|
||||
|
||||
clocks = <&CLOCKGEN_F 1>, <&CLK_M_A1_DIV0 3>;
|
||||
clocks = <&clockgen_f 1>, <&clk_m_a1_div0 3>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -19,11 +19,14 @@ Required properties:
|
|||
"st,stih415-plls-c32-ddr", "st,clkgen-plls-c32"
|
||||
"st,stih416-plls-c32-a9", "st,clkgen-plls-c32"
|
||||
"st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
|
||||
"st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
|
||||
"st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
|
||||
"st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
|
||||
"st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"
|
||||
|
||||
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
|
||||
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
|
||||
|
||||
|
||||
- #clock-cells : From common clock binding; shall be set to 1.
|
||||
|
||||
- clocks : From common clock binding
|
||||
|
|
@ -32,17 +35,17 @@ Required properties:
|
|||
|
||||
Example:
|
||||
|
||||
clockgenA@fee62000 {
|
||||
clockgen-a@fee62000 {
|
||||
reg = <0xfee62000 0xb48>;
|
||||
|
||||
CLK_S_A0_PLL: CLK_S_A0_PLL {
|
||||
clk_s_a0_pll: clk-s-a0-pll {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgena-plls-c65";
|
||||
|
||||
clocks = <&CLK_SYSIN>;
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "CLK_S_A0_PLL0_HS",
|
||||
"CLK_S_A0_PLL0_LS",
|
||||
"CLK_S_A0_PLL1";
|
||||
clock-output-names = "clk-s-a0-pll0-hs",
|
||||
"clk-s-a0-pll0-ls",
|
||||
"clk-s-a0-pll1";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -20,17 +20,17 @@ Required properties:
|
|||
|
||||
Example:
|
||||
|
||||
clockgenA@fd345000 {
|
||||
clockgen-a@fd345000 {
|
||||
reg = <0xfd345000 0xb50>;
|
||||
|
||||
CLK_M_A2_OSC_PREDIV: CLK_M_A2_OSC_PREDIV {
|
||||
clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,clkgena-prediv-c32",
|
||||
"st,clkgena-prediv";
|
||||
|
||||
clocks = <&CLK_SYSIN>;
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "CLK_M_A2_OSC_PREDIV";
|
||||
clock-output-names = "clk-m-a2-osc-prediv";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -32,22 +32,30 @@ Required properties:
|
|||
|
||||
Example:
|
||||
|
||||
CLOCKGEN_C_VCC: CLOCKGEN_C_VCC {
|
||||
clockgen_c_vcc: clockgen-c-vcc@0xfe8308ac {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
|
||||
reg = <0xfe8308ac 12>;
|
||||
|
||||
clocks = <&CLK_S_VCC_HD>, <&CLOCKGEN_C 1>,
|
||||
<&CLK_S_TMDS_FROMPHY>, <&CLOCKGEN_C 2>;
|
||||
clocks = <&clk_s_vcc_hd>,
|
||||
<&clockgen_c 1>,
|
||||
<&clk_s_tmds_fromphy>,
|
||||
<&clockgen_c 2>;
|
||||
|
||||
clock-output-names =
|
||||
"CLK_S_PIX_HDMI", "CLK_S_PIX_DVO",
|
||||
"CLK_S_OUT_DVO", "CLK_S_PIX_HD",
|
||||
"CLK_S_HDDAC", "CLK_S_DENC",
|
||||
"CLK_S_SDDAC", "CLK_S_PIX_MAIN",
|
||||
"CLK_S_PIX_AUX", "CLK_S_STFE_FRC_0",
|
||||
"CLK_S_REF_MCRU", "CLK_S_SLAVE_MCRU",
|
||||
"CLK_S_TMDS_HDMI", "CLK_S_HDMI_REJECT_PLL",
|
||||
"CLK_S_THSENS";
|
||||
clock-output-names = "clk-s-pix-hdmi",
|
||||
"clk-s-pix-dvo",
|
||||
"clk-s-out-dvo",
|
||||
"clk-s-pix-hd",
|
||||
"clk-s-hddac",
|
||||
"clk-s-denc",
|
||||
"clk-s-sddac",
|
||||
"clk-s-pix-main",
|
||||
"clk-s-pix-aux",
|
||||
"clk-s-stfe-frc-0",
|
||||
"clk-s-ref-mcru",
|
||||
"clk-s-slave-mcru",
|
||||
"clk-s-tmds-hdmi",
|
||||
"clk-s-hdmi-reject-pll",
|
||||
"clk-s-thsens";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -24,60 +24,77 @@ address is common of all subnode.
|
|||
quadfs_node {
|
||||
...
|
||||
};
|
||||
|
||||
mux_node {
|
||||
...
|
||||
};
|
||||
|
||||
vcc_node {
|
||||
...
|
||||
};
|
||||
|
||||
flexgen_node {
|
||||
...
|
||||
};
|
||||
...
|
||||
};
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
Each subnode should use the binding discribe in [2]..[4]
|
||||
Each subnode should use the binding discribe in [2]..[7]
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/st,quadfs.txt
|
||||
[3] Documentation/devicetree/bindings/clock/st,quadfs.txt
|
||||
[4] Documentation/devicetree/bindings/clock/st,quadfs.txt
|
||||
[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
|
||||
[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt
|
||||
[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
|
||||
[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
|
||||
[6] Documentation/devicetree/bindings/clock/st,vcc.txt
|
||||
[7] Documentation/devicetree/bindings/clock/st,quadfs.txt
|
||||
[8] Documentation/devicetree/bindings/clock/st,flexgen.txt
|
||||
|
||||
|
||||
Required properties:
|
||||
- reg : A Base address and length of the register set.
|
||||
|
||||
Example:
|
||||
|
||||
clockgenA@fee62000 {
|
||||
clockgen-a@fee62000 {
|
||||
|
||||
reg = <0xfee62000 0xb48>;
|
||||
|
||||
CLK_S_A0_PLL: CLK_S_A0_PLL {
|
||||
clk_s_a0_pll: clk-s-a0-pll {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgena-plls-c65";
|
||||
|
||||
clocks = <&CLK_SYSIN>;
|
||||
clocks = <&clk-sysin>;
|
||||
|
||||
clock-output-names = "CLK_S_A0_PLL0_HS",
|
||||
"CLK_S_A0_PLL0_LS",
|
||||
"CLK_S_A0_PLL1";
|
||||
clock-output-names = "clk-s-a0-pll0-hs",
|
||||
"clk-s-a0-pll0-ls",
|
||||
"clk-s-a0-pll1";
|
||||
};
|
||||
|
||||
CLK_S_A0_OSC_PREDIV: CLK_S_A0_OSC_PREDIV {
|
||||
clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,clkgena-prediv-c65",
|
||||
"st,clkgena-prediv";
|
||||
|
||||
clocks = <&CLK_SYSIN>;
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "CLK_S_A0_OSC_PREDIV";
|
||||
clock-output-names = "clk-s-a0-osc-prediv";
|
||||
};
|
||||
|
||||
CLK_S_A0_HS: CLK_S_A0_HS {
|
||||
clk_s_a0_hs: clk-s-a0-hs {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgena-divmux-c65-hs",
|
||||
"st,clkgena-divmux";
|
||||
|
||||
clocks = <&CLK_S_A0_OSC_PREDIV>,
|
||||
<&CLK_S_A0_PLL 0>, /* PLL0 HS */
|
||||
<&CLK_S_A0_PLL 2>; /* PLL1 */
|
||||
clocks = <&clk-s_a0_osc_prediv>,
|
||||
<&clk-s_a0_pll 0>, /* pll0 hs */
|
||||
<&clk-s_a0_pll 2>; /* pll1 */
|
||||
|
||||
clock-output-names = "CLK_S_FDMA_0",
|
||||
"CLK_S_FDMA_1",
|
||||
""; /* CLK_S_JIT_SENSE */
|
||||
/* Fourth output unused */
|
||||
clock-output-names = "clk-s-fdma-0",
|
||||
"clk-s-fdma-1",
|
||||
""; /* clk-s-jit-sense */
|
||||
/* fourth output unused */
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,119 @@
|
|||
Binding for a type of flexgen structure found on certain
|
||||
STMicroelectronics consumer electronics SoC devices
|
||||
|
||||
This structure includes:
|
||||
- a clock cross bar (represented by a mux element)
|
||||
- a pre and final dividers (represented by a divider and gate elements)
|
||||
|
||||
Flexgen structure is a part of Clockgen[1].
|
||||
|
||||
Please find an example below:
|
||||
|
||||
Clockgen block diagram
|
||||
-------------------------------------------------------------------
|
||||
| Flexgen stucture |
|
||||
| --------------------------------------------- |
|
||||
| | ------- -------- -------- | |
|
||||
clk_sysin | | | | | | | | |
|
||||
---|-----------------|-->| | | | | | | |
|
||||
| | | | | | | | | | |
|
||||
| | ------- | | | |Pre | |Final | | |
|
||||
| | |PLL0 | | | | |Dividers| |Dividers| | |
|
||||
| |->| | | | | | x32 | | x32 | | |
|
||||
| | | odf_0|----|-->| | | | | | | |
|
||||
| | | | | | | | | | | | |
|
||||
| | | | | | | | | | | | |
|
||||
| | | | | | | | | | | | |
|
||||
| | | | | | | | | | | | |
|
||||
| | ------- | | | | | | | | |
|
||||
| | | | | | | | | | |
|
||||
| | ------- | | Clock | | | | | | |
|
||||
| | |PLL1 | | | | | | | | | |
|
||||
| |->| | | | Cross | | | | | | |
|
||||
| | | odf_0|----|-->| | | | | | CLK_DIV[31:0]
|
||||
| | | | | | Bar |====>| |====>| |===|=========>
|
||||
| | | | | | | | | | | | |
|
||||
| | | | | | | | | | | | |
|
||||
| | | | | | | | | | | | |
|
||||
| | ------- | | | | | | | | |
|
||||
| | | | | | | | | | |
|
||||
| | ------- | | | | | | | | |
|
||||
| | |QUADFS | | | | | | | | | |
|
||||
| |->| ch0|----|-->| | | | | | | |
|
||||
| | | | | | | | | | | |
|
||||
| | ch1|----|-->| | | | | | | |
|
||||
| | | | | | | | | | | |
|
||||
| | ch2|----|-->| | | DIV | | DIV | | |
|
||||
| | | | | | | 1 to | | 1 to | | |
|
||||
| | ch3|----|-->| | | 1024 | | 64 | | |
|
||||
| ------- | | | | | | | | |
|
||||
| | ------- -------- -------- | |
|
||||
| -------------------------------------------- |
|
||||
| |
|
||||
-------------------------------------------------------------------
|
||||
|
||||
This binding uses the common clock binding[2].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
|
||||
[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be:
|
||||
"st,flexgen"
|
||||
|
||||
- #clock-cells : from common clock binding; shall be set to 1 (multiple clock
|
||||
outputs).
|
||||
|
||||
- clocks : must be set to the parent's phandle. it's could be output clocks of
|
||||
a quadsfs or/and a pll or/and clk_sysin (up to 7 clocks)
|
||||
|
||||
- clock-output-names : List of strings used to name the clock outputs.
|
||||
|
||||
Example:
|
||||
|
||||
clk_s_c0_flexgen: clk-s-c0-flexgen {
|
||||
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,flexgen";
|
||||
|
||||
clocks = <&clk_s_c0_pll0 0>,
|
||||
<&clk_s_c0_pll1 0>,
|
||||
<&clk_s_c0_quadfs 0>,
|
||||
<&clk_s_c0_quadfs 1>,
|
||||
<&clk_s_c0_quadfs 2>,
|
||||
<&clk_s_c0_quadfs 3>,
|
||||
<&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-icn-gpu",
|
||||
"clk-fdma",
|
||||
"clk-nand",
|
||||
"clk-hva",
|
||||
"clk-proc-stfe",
|
||||
"clk-proc-tp",
|
||||
"clk-rx-icn-dmu",
|
||||
"clk-rx-icn-hva",
|
||||
"clk-icn-cpu",
|
||||
"clk-tx-icn-dmu",
|
||||
"clk-mmc-0",
|
||||
"clk-mmc-1",
|
||||
"clk-jpegdec",
|
||||
"clk-ext2fa9",
|
||||
"clk-ic-bdisp-0",
|
||||
"clk-ic-bdisp-1",
|
||||
"clk-pp-dmu",
|
||||
"clk-vid-dmu",
|
||||
"clk-dss-lpc",
|
||||
"clk-st231-aud-0",
|
||||
"clk-st231-gp-1",
|
||||
"clk-st231-dmu",
|
||||
"clk-icn-lmi",
|
||||
"clk-tx-icn-disp-1",
|
||||
"clk-icn-sbc",
|
||||
"clk-stfe-frc2",
|
||||
"clk-eth-phy",
|
||||
"clk-eth-ref-phyclk",
|
||||
"clk-flash-promip",
|
||||
"clk-main-disp",
|
||||
"clk-aux-disp",
|
||||
"clk-compo-dvp";
|
||||
};
|
||||
|
|
@ -15,6 +15,9 @@ Required properties:
|
|||
"st,stih416-quadfs432", "st,quadfs"
|
||||
"st,stih416-quadfs660-E", "st,quadfs"
|
||||
"st,stih416-quadfs660-F", "st,quadfs"
|
||||
"st,stih407-quadfs660-C", "st,quadfs"
|
||||
"st,stih407-quadfs660-D", "st,quadfs"
|
||||
|
||||
|
||||
- #clock-cells : from common clock binding; shall be set to 1.
|
||||
|
||||
|
|
@ -32,14 +35,14 @@ Required properties:
|
|||
|
||||
Example:
|
||||
|
||||
CLOCKGEN_E: CLOCKGEN_E {
|
||||
clockgen_e: clockgen-e@fd3208bc {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,stih416-quadfs660-E", "st,quadfs";
|
||||
reg = <0xfd3208bc 0xB0>;
|
||||
|
||||
clocks = <&CLK_SYSIN>;
|
||||
clock-output-names = "CLK_M_PIX_MDTP_0",
|
||||
"CLK_M_PIX_MDTP_1",
|
||||
"CLK_M_PIX_MDTP_2",
|
||||
"CLK_M_MPELPC";
|
||||
clocks = <&clk_sysin>;
|
||||
clock-output-names = "clk-m-pix-mdtp-0",
|
||||
"clk-m-pix-mdtp-1",
|
||||
"clk-m-pix-mdtp-2",
|
||||
"clk-m-mpelpc";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -9,11 +9,13 @@ Required properties:
|
|||
"allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
|
||||
"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
|
||||
"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
|
||||
"allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
|
||||
"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
|
||||
"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
|
||||
"allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
|
||||
"allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
|
||||
"allwinner,sun4i-a10-axi-clk" - for the AXI clock
|
||||
"allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
|
||||
"allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
|
||||
"allwinner,sun4i-a10-ahb-clk" - for the AHB clock
|
||||
"allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
|
||||
|
|
@ -23,13 +25,16 @@ Required properties:
|
|||
"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
|
||||
"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
|
||||
"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
|
||||
"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
|
||||
"allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
|
||||
"allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
|
||||
"allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
|
||||
"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
|
||||
"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
|
||||
"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
|
||||
"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
|
||||
"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
|
||||
"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
|
||||
"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
|
||||
"allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
|
||||
"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
|
||||
|
|
@ -37,8 +42,10 @@ Required properties:
|
|||
"allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
|
||||
"allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
|
||||
"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
|
||||
"allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
|
||||
"allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
|
||||
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
|
||||
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
|
||||
"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
|
||||
"allwinner,sun7i-a20-out-clk" - for the external output clocks
|
||||
"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
|
||||
|
|
|
|||
|
|
@ -0,0 +1,19 @@
|
|||
* AMD Cryptographic Coprocessor driver (ccp)
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "amd,ccp-seattle-v1a"
|
||||
- reg: Address and length of the register set for the device
|
||||
- interrupt-parent: Should be the phandle for the interrupt controller
|
||||
that services interrupts for this device
|
||||
- interrupts: Should contain the CCP interrupt
|
||||
|
||||
Optional properties:
|
||||
- dma-coherent: Present if dma operations are coherent
|
||||
|
||||
Example:
|
||||
ccp@e0100000 {
|
||||
compatible = "amd,ccp-seattle-v1a";
|
||||
reg = <0 0xe0100000 0 0x10000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 3 4>;
|
||||
};
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
Qualcomm crypto engine driver
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "qcom,crypto-v5.1"
|
||||
- reg : specifies base physical address and size of the registers map
|
||||
- clocks : phandle to clock-controller plus clock-specifier pair
|
||||
- clock-names : "iface" clocks register interface
|
||||
"bus" clocks data transfer interface
|
||||
"core" clocks rest of the crypto block
|
||||
- dmas : DMA specifiers for tx and rx dma channels. For more see
|
||||
Documentation/devicetree/bindings/dma/dma.txt
|
||||
- dma-names : DMA request names should be "rx" and "tx"
|
||||
|
||||
Example:
|
||||
crypto@fd45a000 {
|
||||
compatible = "qcom,crypto-v5.1";
|
||||
reg = <0xfd45a000 0x6000>;
|
||||
clocks = <&gcc GCC_CE2_AHB_CLK>,
|
||||
<&gcc GCC_CE2_AXI_CLK>,
|
||||
<&gcc GCC_CE2_CLK>;
|
||||
clock-names = "iface", "bus", "core";
|
||||
dmas = <&cryptobam 2>, <&cryptobam 3>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
|
|
@ -47,6 +47,7 @@ The full ID of peripheral types can be found below.
|
|||
20 ASRC
|
||||
21 ESAI
|
||||
22 SSI Dual FIFO (needs firmware ver >= 2)
|
||||
23 Shared ASRC
|
||||
|
||||
The third cell specifies the transfer priority as below.
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,29 @@
|
|||
* Freescale MPC512x and MPC8308 DMA Controller
|
||||
|
||||
The DMA controller in Freescale MPC512x and MPC8308 SoCs can move
|
||||
blocks of memory contents between memory and peripherals or
|
||||
from memory to memory.
|
||||
|
||||
Refer to "Generic DMA Controller and DMA request bindings" in
|
||||
the dma/dma.txt file for a more detailed description of binding.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "fsl,mpc5121-dma" or "fsl,mpc8308-dma";
|
||||
- reg: should contain the DMA controller registers location and length;
|
||||
- interrupt for the DMA controller: syntax of interrupt client node
|
||||
is described in interrupt-controller/interrupts.txt file.
|
||||
- #dma-cells: the length of the DMA specifier, must be <1>.
|
||||
Each channel of this DMA controller has a peripheral request line,
|
||||
the assignment is fixed in hardware. This one cell
|
||||
in dmas property of a client device represents the channel number.
|
||||
|
||||
Example:
|
||||
|
||||
dma0: dma@14000 {
|
||||
compatible = "fsl,mpc5121-dma";
|
||||
reg = <0x14000 0x1800>;
|
||||
interrupts = <65 0x8>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
DMA clients must use the format described in dma/dma.txt file.
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
* Renesas "Type-AXI" NBPFAXI* DMA controllers
|
||||
|
||||
* DMA controller
|
||||
|
||||
Required properties
|
||||
|
||||
- compatible: must be one of
|
||||
"renesas,nbpfaxi64dmac1b4"
|
||||
"renesas,nbpfaxi64dmac1b8"
|
||||
"renesas,nbpfaxi64dmac1b16"
|
||||
"renesas,nbpfaxi64dmac4b4"
|
||||
"renesas,nbpfaxi64dmac4b8"
|
||||
"renesas,nbpfaxi64dmac4b16"
|
||||
"renesas,nbpfaxi64dmac8b4"
|
||||
"renesas,nbpfaxi64dmac8b8"
|
||||
"renesas,nbpfaxi64dmac8b16"
|
||||
- #dma-cells: must be 2: the first integer is a terminal number, to which this
|
||||
slave is connected, the second one is flags. Flags is a bitmask
|
||||
with the following bits defined:
|
||||
|
||||
#define NBPF_SLAVE_RQ_HIGH 1
|
||||
#define NBPF_SLAVE_RQ_LOW 2
|
||||
#define NBPF_SLAVE_RQ_LEVEL 4
|
||||
|
||||
Optional properties:
|
||||
|
||||
You can use dma-channels and dma-requests as described in dma.txt, although they
|
||||
won't be used, this information is derived from the compatibility string.
|
||||
|
||||
Example:
|
||||
|
||||
dma: dma-controller@48000000 {
|
||||
compatible = "renesas,nbpfaxi64dmac8b4";
|
||||
reg = <0x48000000 0x400>;
|
||||
interrupts = <0 12 0x4
|
||||
0 13 0x4
|
||||
0 14 0x4
|
||||
0 15 0x4
|
||||
0 16 0x4
|
||||
0 17 0x4
|
||||
0 18 0x4
|
||||
0 19 0x4>;
|
||||
#dma-cells = <2>;
|
||||
dma-channels = <8>;
|
||||
dma-requests = <8>;
|
||||
};
|
||||
|
||||
* DMA client
|
||||
|
||||
Required properties:
|
||||
|
||||
dmas and dma-names are required, as described in dma.txt.
|
||||
|
||||
Example:
|
||||
|
||||
#include <dt-bindings/dma/nbpfaxi.h>
|
||||
|
||||
...
|
||||
dmas = <&dma 0 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)
|
||||
&dma 1 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
|
||||
dma-names = "rx", "tx";
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
* R-Car Audio DMAC peri peri Device Tree bindings
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "renesas,rcar-audmapp"
|
||||
- #dma-cells: should be <1>, see "dmas" property below
|
||||
|
||||
Example:
|
||||
audmapp: audio-dma-pp@0xec740000 {
|
||||
compatible = "renesas,rcar-audmapp";
|
||||
#dma-cells = <1>;
|
||||
|
||||
reg = <0 0xec740000 0 0x200>;
|
||||
};
|
||||
|
||||
|
||||
* DMA client
|
||||
|
||||
Required properties:
|
||||
- dmas: a list of <[DMA multiplexer phandle] [SRS/DRS value]> pairs,
|
||||
where SRS/DRS values are fixed handles, specified in the SoC
|
||||
manual as the value that would be written into the PDMACHCR.
|
||||
- dma-names: a list of DMA channel names, one per "dmas" entry
|
||||
|
||||
Example:
|
||||
|
||||
dmas = <&audmapp 0x2d00
|
||||
&audmapp 0x3700>;
|
||||
dma-names = "src0_ssiu0",
|
||||
"dvc0_ssiu0";
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
* Renesas R-Car DMA Controller Device Tree bindings
|
||||
|
||||
Renesas R-Car Generation 2 SoCs have have multiple multi-channel DMA
|
||||
controller instances named DMAC capable of serving multiple clients. Channels
|
||||
can be dedicated to specific clients or shared between a large number of
|
||||
clients.
|
||||
|
||||
DMA clients are connected to the DMAC ports referenced by an 8-bit identifier
|
||||
called MID/RID.
|
||||
|
||||
Each DMA client is connected to one dedicated port of the DMAC, identified by
|
||||
an 8-bit port number called the MID/RID. A DMA controller can thus serve up to
|
||||
256 clients in total. When the number of hardware channels is lower than the
|
||||
number of clients to be served, channels must be shared between multiple DMA
|
||||
clients. The association of DMA clients to DMAC channels is fully dynamic and
|
||||
not described in these device tree bindings.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: must contain "renesas,rcar-dmac"
|
||||
|
||||
- reg: base address and length of the registers block for the DMAC
|
||||
|
||||
- interrupts: interrupt specifiers for the DMAC, one for each entry in
|
||||
interrupt-names.
|
||||
- interrupt-names: one entry per channel, named "ch%u", where %u is the
|
||||
channel number ranging from zero to the number of channels minus one.
|
||||
|
||||
- clock-names: "fck" for the functional clock
|
||||
- clocks: a list of phandle + clock-specifier pairs, one for each entry
|
||||
in clock-names.
|
||||
- clock-names: must contain "fck" for the functional clock.
|
||||
|
||||
- #dma-cells: must be <1>, the cell specifies the MID/RID of the DMAC port
|
||||
connected to the DMA client
|
||||
- dma-channels: number of DMA channels
|
||||
|
||||
Example: R8A7790 (R-Car H2) SYS-DMACs
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
compatible = "renesas,rcar-dmac";
|
||||
reg = <0 0xe6700000 0 0x20000>;
|
||||
interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
|
||||
0 200 IRQ_TYPE_LEVEL_HIGH
|
||||
0 201 IRQ_TYPE_LEVEL_HIGH
|
||||
0 202 IRQ_TYPE_LEVEL_HIGH
|
||||
0 203 IRQ_TYPE_LEVEL_HIGH
|
||||
0 204 IRQ_TYPE_LEVEL_HIGH
|
||||
0 205 IRQ_TYPE_LEVEL_HIGH
|
||||
0 206 IRQ_TYPE_LEVEL_HIGH
|
||||
0 207 IRQ_TYPE_LEVEL_HIGH
|
||||
0 208 IRQ_TYPE_LEVEL_HIGH
|
||||
0 209 IRQ_TYPE_LEVEL_HIGH
|
||||
0 210 IRQ_TYPE_LEVEL_HIGH
|
||||
0 211 IRQ_TYPE_LEVEL_HIGH
|
||||
0 212 IRQ_TYPE_LEVEL_HIGH
|
||||
0 213 IRQ_TYPE_LEVEL_HIGH
|
||||
0 214 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
|
||||
clock-names = "fck";
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@e6720000 {
|
||||
compatible = "renesas,rcar-dmac";
|
||||
reg = <0 0xe6720000 0 0x20000>;
|
||||
interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
|
||||
0 216 IRQ_TYPE_LEVEL_HIGH
|
||||
0 217 IRQ_TYPE_LEVEL_HIGH
|
||||
0 218 IRQ_TYPE_LEVEL_HIGH
|
||||
0 219 IRQ_TYPE_LEVEL_HIGH
|
||||
0 308 IRQ_TYPE_LEVEL_HIGH
|
||||
0 309 IRQ_TYPE_LEVEL_HIGH
|
||||
0 310 IRQ_TYPE_LEVEL_HIGH
|
||||
0 311 IRQ_TYPE_LEVEL_HIGH
|
||||
0 312 IRQ_TYPE_LEVEL_HIGH
|
||||
0 313 IRQ_TYPE_LEVEL_HIGH
|
||||
0 314 IRQ_TYPE_LEVEL_HIGH
|
||||
0 315 IRQ_TYPE_LEVEL_HIGH
|
||||
0 316 IRQ_TYPE_LEVEL_HIGH
|
||||
0 317 IRQ_TYPE_LEVEL_HIGH
|
||||
0 318 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
|
||||
clock-names = "fck";
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
|
|
@ -35,9 +35,11 @@ Required properties:
|
|||
|
||||
Each dmas request consists of 4 cells:
|
||||
1. A phandle pointing to the DMA controller
|
||||
2. Device Type
|
||||
2. Device signal number, the signal line for single and burst requests
|
||||
connected from the device to the DMA40 engine
|
||||
3. The DMA request line number (only when 'use fixed channel' is set)
|
||||
4. A 32bit mask specifying; mode, direction and endianness [NB: This list will grow]
|
||||
4. A 32bit mask specifying; mode, direction and endianness
|
||||
[NB: This list will grow]
|
||||
0x00000001: Mode:
|
||||
Logical channel when unset
|
||||
Physical channel when set
|
||||
|
|
@ -54,6 +56,74 @@ Each dmas request consists of 4 cells:
|
|||
Normal priority when unset
|
||||
High priority when set
|
||||
|
||||
Existing signal numbers for the DB8500 ASIC. Unless specified, the signals are
|
||||
bidirectional, i.e. the same for RX and TX operations:
|
||||
|
||||
0: SPI controller 0
|
||||
1: SD/MMC controller 0 (unused)
|
||||
2: SD/MMC controller 1 (unused)
|
||||
3: SD/MMC controller 2 (unused)
|
||||
4: I2C port 1
|
||||
5: I2C port 3
|
||||
6: I2C port 2
|
||||
7: I2C port 4
|
||||
8: Synchronous Serial Port SSP0
|
||||
9: Synchronous Serial Port SSP1
|
||||
10: Multi-Channel Display Engine MCDE RX
|
||||
11: UART port 2
|
||||
12: UART port 1
|
||||
13: UART port 0
|
||||
14: Multirate Serial Port MSP2
|
||||
15: I2C port 0
|
||||
16: USB OTG in/out endpoints 7 & 15
|
||||
17: USB OTG in/out endpoints 6 & 14
|
||||
18: USB OTG in/out endpoints 5 & 13
|
||||
19: USB OTG in/out endpoints 4 & 12
|
||||
20: SLIMbus or HSI channel 0
|
||||
21: SLIMbus or HSI channel 1
|
||||
22: SLIMbus or HSI channel 2
|
||||
23: SLIMbus or HSI channel 3
|
||||
24: Multimedia DSP SXA0
|
||||
25: Multimedia DSP SXA1
|
||||
26: Multimedia DSP SXA2
|
||||
27: Multimedia DSP SXA3
|
||||
28: SD/MM controller 2
|
||||
29: SD/MM controller 0
|
||||
30: MSP port 1 on DB8500 v1, MSP port 3 on DB8500 v2
|
||||
31: MSP port 0 or SLIMbus channel 0
|
||||
32: SD/MM controller 1
|
||||
33: SPI controller 2
|
||||
34: i2c3 RX2 TX2
|
||||
35: SPI controller 1
|
||||
36: USB OTG in/out endpoints 3 & 11
|
||||
37: USB OTG in/out endpoints 2 & 10
|
||||
38: USB OTG in/out endpoints 1 & 9
|
||||
39: USB OTG in/out endpoints 8
|
||||
40: SPI controller 3
|
||||
41: SD/MM controller 3
|
||||
42: SD/MM controller 4
|
||||
43: SD/MM controller 5
|
||||
44: Multimedia DSP SXA4
|
||||
45: Multimedia DSP SXA5
|
||||
46: SLIMbus channel 8 or Multimedia DSP SXA6
|
||||
47: SLIMbus channel 9 or Multimedia DSP SXA7
|
||||
48: Crypto Accelerator 1
|
||||
49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
|
||||
50: Hash Accelerator 1 TX
|
||||
51: memcpy TX (to be used by the DMA driver for memcpy operations)
|
||||
52: SLIMbus or HSI channel 4
|
||||
53: SLIMbus or HSI channel 5
|
||||
54: SLIMbus or HSI channel 6
|
||||
55: SLIMbus or HSI channel 7
|
||||
56: memcpy (to be used by the DMA driver for memcpy operations)
|
||||
57: memcpy (to be used by the DMA driver for memcpy operations)
|
||||
58: memcpy (to be used by the DMA driver for memcpy operations)
|
||||
59: memcpy (to be used by the DMA driver for memcpy operations)
|
||||
60: memcpy (to be used by the DMA driver for memcpy operations)
|
||||
61: Crypto Accelerator 0
|
||||
62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX
|
||||
63: Hash Accelerator 0 TX
|
||||
|
||||
Example:
|
||||
|
||||
uart@80120000 {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,45 @@
|
|||
Allwinner A31 DMA Controller
|
||||
|
||||
This driver follows the generic DMA bindings defined in dma.txt.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Must be "allwinner,sun6i-a31-dma"
|
||||
- reg: Should contain the registers base address and length
|
||||
- interrupts: Should contain a reference to the interrupt used by this device
|
||||
- clocks: Should contain a reference to the parent AHB clock
|
||||
- resets: Should contain a reference to the reset controller asserting
|
||||
this device in reset
|
||||
- #dma-cells : Should be 1, a single cell holding a line request number
|
||||
|
||||
Example:
|
||||
dma: dma-controller@01c02000 {
|
||||
compatible = "allwinner,sun6i-a31-dma";
|
||||
reg = <0x01c02000 0x1000>;
|
||||
interrupts = <0 50 4>;
|
||||
clocks = <&ahb1_gates 6>;
|
||||
resets = <&ahb1_rst 6>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
Clients:
|
||||
|
||||
DMA clients connected to the A31 DMA controller must use the format
|
||||
described in the dma.txt file, using a two-cell specifier for each
|
||||
channel: a phandle plus one integer cells.
|
||||
The two cells in order are:
|
||||
|
||||
1. A phandle pointing to the DMA controller.
|
||||
2. The port ID as specified in the datasheet
|
||||
|
||||
Example:
|
||||
spi2: spi@01c6a000 {
|
||||
compatible = "allwinner,sun6i-a31-spi";
|
||||
reg = <0x01c6a000 0x1000>;
|
||||
interrupts = <0 67 4>;
|
||||
clocks = <&ahb1_gates 22>, <&spi2_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
dmas = <&dma 25>, <&dma 25>;
|
||||
dma-names = "rx", "tx";
|
||||
resets = <&ahb1_rst 22>;
|
||||
};
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
Device Tree bindings for Armada DRM CRTC driver
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be "marvell,dove-lcd".
|
||||
- reg: base address and size of the LCD controller
|
||||
- interrupts: single interrupt number for the LCD controller
|
||||
- port: video output port with endpoints, as described by graph.txt
|
||||
|
||||
Optional properties:
|
||||
|
||||
- clocks: as described by clock-bindings.txt
|
||||
- clock-names: as described by clock-bindings.txt
|
||||
"axiclk" - axi bus clock for pixel clock
|
||||
"plldivider" - pll divider clock for pixel clock
|
||||
"ext_ref_clk0" - external clock 0 for pixel clock
|
||||
"ext_ref_clk1" - external clock 1 for pixel clock
|
||||
|
||||
Note: all clocks are optional but at least one must be specified.
|
||||
Further clocks may be added in the future according to requirements of
|
||||
different SoCs.
|
||||
|
||||
Example:
|
||||
|
||||
lcd0: lcd-controller@820000 {
|
||||
compatible = "marvell,dove-lcd";
|
||||
reg = <0x820000 0x1000>;
|
||||
interrupts = <47>;
|
||||
clocks = <&si5351 0>;
|
||||
clock-names = "ext_ref_clk_1";
|
||||
};
|
||||
|
|
@ -3,6 +3,8 @@ Device-Tree bindings for the NXP TDA998x HDMI transmitter
|
|||
Required properties;
|
||||
- compatible: must be "nxp,tda998x"
|
||||
|
||||
- reg: I2C address
|
||||
|
||||
Optional properties:
|
||||
- interrupts: interrupt number and trigger type
|
||||
default: polling
|
||||
|
|
|
|||
|
|
@ -0,0 +1,52 @@
|
|||
Qualcomm adreno/snapdragon GPU
|
||||
|
||||
Required properties:
|
||||
- compatible: "qcom,adreno-3xx"
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt signal from the gpu.
|
||||
- clocks: device clocks
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: the following clocks are required:
|
||||
* "core_clk"
|
||||
* "iface_clk"
|
||||
* "mem_iface_clk"
|
||||
- qcom,chipid: gpu chip-id. Note this may become optional for future
|
||||
devices if we can reliably read the chipid from hw
|
||||
- qcom,gpu-pwrlevels: list of operating points
|
||||
- compatible: "qcom,gpu-pwrlevels"
|
||||
- for each qcom,gpu-pwrlevel:
|
||||
- qcom,gpu-freq: requested gpu clock speed
|
||||
- NOTE: downstream android driver defines additional parameters to
|
||||
configure memory bandwidth scaling per OPP.
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
gpu: qcom,kgsl-3d0@4300000 {
|
||||
compatible = "qcom,adreno-3xx";
|
||||
reg = <0x04300000 0x20000>;
|
||||
reg-names = "kgsl_3d0_reg_memory";
|
||||
interrupts = <GIC_SPI 80 0>;
|
||||
interrupt-names = "kgsl_3d0_irq";
|
||||
clock-names =
|
||||
"core_clk",
|
||||
"iface_clk",
|
||||
"mem_iface_clk";
|
||||
clocks =
|
||||
<&mmcc GFX3D_CLK>,
|
||||
<&mmcc GFX3D_AHB_CLK>,
|
||||
<&mmcc MMSS_IMEM_AHB_CLK>;
|
||||
qcom,chipid = <0x03020100>;
|
||||
qcom,gpu-pwrlevels {
|
||||
compatible = "qcom,gpu-pwrlevels";
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
qcom,gpu-freq = <450000000>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
qcom,gpu-freq = <27000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
Qualcomm adreno/snapdragon hdmi output
|
||||
|
||||
Required properties:
|
||||
- compatible: one of the following
|
||||
* "qcom,hdmi-tx-8660"
|
||||
* "qcom,hdmi-tx-8960"
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- reg-names: "core_physical"
|
||||
- interrupts: The interrupt signal from the hdmi block.
|
||||
- clocks: device clocks
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin
|
||||
- qcom,hdmi-tx-ddc-data-gpio: ddc data pin
|
||||
- qcom,hdmi-tx-hpd-gpio: hpd pin
|
||||
- core-vdda-supply: phandle to supply regulator
|
||||
- hdmi-mux-supply: phandle to mux regulator
|
||||
|
||||
Optional properties:
|
||||
- qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin
|
||||
- qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
hdmi: qcom,hdmi-tx-8960@4a00000 {
|
||||
compatible = "qcom,hdmi-tx-8960";
|
||||
reg-names = "core_physical";
|
||||
reg = <0x04a00000 0x1000>;
|
||||
interrupts = <GIC_SPI 79 0>;
|
||||
clock-names =
|
||||
"core_clk",
|
||||
"master_iface_clk",
|
||||
"slave_iface_clk";
|
||||
clocks =
|
||||
<&mmcc HDMI_APP_CLK>,
|
||||
<&mmcc HDMI_M_AHB_CLK>,
|
||||
<&mmcc HDMI_S_AHB_CLK>;
|
||||
qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>;
|
||||
qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>;
|
||||
qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>;
|
||||
core-vdda-supply = <&pm8921_hdmi_mvs>;
|
||||
hdmi-mux-supply = <&ext_3p3v>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
Qualcomm adreno/snapdragon display controller
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
* "qcom,mdp" - mdp4
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt signal from the display controller.
|
||||
- connectors: array of phandles for output device(s)
|
||||
- clocks: device clocks
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: the following clocks are required:
|
||||
* "core_clk"
|
||||
* "iface_clk"
|
||||
* "lut_clk"
|
||||
* "src_clk"
|
||||
* "hdmi_clk"
|
||||
* "mpd_clk"
|
||||
|
||||
Optional properties:
|
||||
- gpus: phandle for gpu device
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
mdp: qcom,mdp@5100000 {
|
||||
compatible = "qcom,mdp";
|
||||
reg = <0x05100000 0xf0000>;
|
||||
interrupts = <GIC_SPI 75 0>;
|
||||
connectors = <&hdmi>;
|
||||
gpus = <&gpu>;
|
||||
clock-names =
|
||||
"core_clk",
|
||||
"iface_clk",
|
||||
"lut_clk",
|
||||
"src_clk",
|
||||
"hdmi_clk",
|
||||
"mdp_clk";
|
||||
clocks =
|
||||
<&mmcc MDP_SRC>,
|
||||
<&mmcc MDP_AHB_CLK>,
|
||||
<&mmcc MDP_LUT_CLK>,
|
||||
<&mmcc TV_SRC>,
|
||||
<&mmcc HDMI_TV_CLK>,
|
||||
<&mmcc MDP_TV_CLK>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
|
||||
* SM5502 MUIC (Micro-USB Interface Controller) device
|
||||
|
||||
The Silicon Mitus SM5502 is a MUIC (Micro-USB Interface Controller) device
|
||||
which can detect the state of external accessory when external accessory is
|
||||
attached or detached and button is pressed or released. It is interfaced to
|
||||
the host controller using an I2C interface.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "siliconmitus,sm5502-muic"
|
||||
- reg: Specifies the I2C slave address of the MUIC block. It should be 0x25
|
||||
- interrupt-parent: Specifies the phandle of the interrupt controller to which
|
||||
the interrupts from sm5502 are delivered to.
|
||||
- interrupts: Interrupt specifiers for detection interrupt sources.
|
||||
|
||||
Example:
|
||||
|
||||
sm5502@25 {
|
||||
compatible = "siliconmitus,sm5502-muic";
|
||||
interrupt-parent = <&gpx1>;
|
||||
interrupts = <5 0>;
|
||||
reg = <0x25>;
|
||||
};
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.
|
||||
|
||||
Required properties:
|
||||
- compatible : should be:
|
||||
"nvidia,tegra20-efuse"
|
||||
"nvidia,tegra30-efuse"
|
||||
"nvidia,tegra114-efuse"
|
||||
"nvidia,tegra124-efuse"
|
||||
Details:
|
||||
nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
|
||||
due to a hardware bug. Tegra20 also lacks certain information which is
|
||||
available in later generations such as fab code, lot code, wafer id,..
|
||||
nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse:
|
||||
The differences between these SoCs are the size of the efuse array,
|
||||
the location of the spare (OEM programmable) bits and the location of
|
||||
the speedo data.
|
||||
- reg: Should contain 1 entry: the entry gives the physical address and length
|
||||
of the fuse registers.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
- fuse
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- fuse
|
||||
|
||||
Example:
|
||||
|
||||
fuse@7000f800 {
|
||||
compatible = "nvidia,tegra20-efuse";
|
||||
reg = <0x7000F800 0x400>,
|
||||
<0x70000000 0x400>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_FUSE>;
|
||||
clock-names = "fuse";
|
||||
resets = <&tegra_car 39>;
|
||||
reset-names = "fuse";
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
Xilinx Zynq GPIO controller Device Tree Bindings
|
||||
-------------------------------------------
|
||||
|
||||
Required properties:
|
||||
- #gpio-cells : Should be two
|
||||
- First cell is the GPIO line number
|
||||
- Second cell is used to specify optional
|
||||
parameters (unused)
|
||||
- compatible : Should be "xlnx,zynq-gpio-1.0"
|
||||
- clocks : Clock specifier (see clock bindings for details)
|
||||
- gpio-controller : Marks the device node as a GPIO controller.
|
||||
- interrupts : Interrupt specifier (see interrupt bindings for
|
||||
details)
|
||||
- interrupt-parent : Must be core interrupt controller
|
||||
- reg : Address and length of the register set for the device
|
||||
|
||||
Example:
|
||||
gpio@e000a000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "xlnx,zynq-gpio-1.0";
|
||||
clocks = <&clkc 42>;
|
||||
gpio-controller;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 20 4>;
|
||||
reg = <0xe000a000 0x1000>;
|
||||
};
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
NVIDIA GK20A Graphics Processing Unit
|
||||
|
||||
Required properties:
|
||||
- compatible: "nvidia,<chip>-<gpu>"
|
||||
Currently recognized values:
|
||||
- nvidia,tegra124-gk20a
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
Must contain two entries:
|
||||
- first entry for bar0
|
||||
- second entry for bar1
|
||||
- interrupts: Must contain an entry for each entry in interrupt-names.
|
||||
See ../interrupt-controller/interrupts.txt for details.
|
||||
- interrupt-names: Must include the following entries:
|
||||
- stall
|
||||
- nonstall
|
||||
- vdd-supply: regulator for supply voltage.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
- gpu
|
||||
- pwr
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- gpu
|
||||
|
||||
Example:
|
||||
|
||||
gpu@0,57000000 {
|
||||
compatible = "nvidia,gk20a";
|
||||
reg = <0x0 0x57000000 0x0 0x01000000>,
|
||||
<0x0 0x58000000 0x0 0x01000000>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "stall", "nonstall";
|
||||
vdd-supply = <&vdd_gpu>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_GPU>,
|
||||
<&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
|
||||
clock-names = "gpu", "pwr";
|
||||
resets = <&tegra_car 184>;
|
||||
reset-names = "gpu";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -0,0 +1,189 @@
|
|||
STMicroelectronics stih4xx platforms
|
||||
|
||||
- sti-vtg: video timing generator
|
||||
Required properties:
|
||||
- compatible: "st,vtg"
|
||||
- reg: Physical base address of the IP registers and length of memory mapped region.
|
||||
Optional properties:
|
||||
- interrupts : VTG interrupt number to the CPU.
|
||||
- st,slave: phandle on a slave vtg
|
||||
|
||||
- sti-vtac: video timing advanced inter dye communication Rx and TX
|
||||
Required properties:
|
||||
- compatible: "st,vtac-main" or "st,vtac-aux"
|
||||
- reg: Physical base address of the IP registers and length of memory mapped region.
|
||||
- clocks: from common clock binding: handle hardware IP needed clocks, the
|
||||
number of clocks may depend of the SoC type.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: names of the clocks listed in clocks property in the same
|
||||
order.
|
||||
|
||||
- sti-display-subsystem: Master device for DRM sub-components
|
||||
This device must be the parent of all the sub-components and is responsible
|
||||
of bind them.
|
||||
Required properties:
|
||||
- compatible: "st,sti-display-subsystem"
|
||||
- ranges: to allow probing of subdevices
|
||||
|
||||
- sti-compositor: frame compositor engine
|
||||
must be a child of sti-display-subsystem
|
||||
Required properties:
|
||||
- compatible: "st,stih<chip>-compositor"
|
||||
- reg: Physical base address of the IP registers and length of memory mapped region.
|
||||
- clocks: from common clock binding: handle hardware IP needed clocks, the
|
||||
number of clocks may depend of the SoC type.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: names of the clocks listed in clocks property in the same
|
||||
order.
|
||||
- resets: resets to be used by the device
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: names of the resets listed in resets property in the same
|
||||
order.
|
||||
- st,vtg: phandle(s) on vtg device (main and aux) nodes.
|
||||
|
||||
- sti-tvout: video out hardware block
|
||||
must be a child of sti-display-subsystem
|
||||
Required properties:
|
||||
- compatible: "st,stih<chip>-tvout"
|
||||
- reg: Physical base address of the IP registers and length of memory mapped region.
|
||||
- reg-names: names of the mapped memory regions listed in regs property in
|
||||
the same order.
|
||||
- resets: resets to be used by the device
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: names of the resets listed in resets property in the same
|
||||
order.
|
||||
- ranges: to allow probing of subdevices
|
||||
|
||||
- sti-hdmi: hdmi output block
|
||||
must be a child of sti-tvout
|
||||
Required properties:
|
||||
- compatible: "st,stih<chip>-hdmi";
|
||||
- reg: Physical base address of the IP registers and length of memory mapped region.
|
||||
- reg-names: names of the mapped memory regions listed in regs property in
|
||||
the same order.
|
||||
- interrupts : HDMI interrupt number to the CPU.
|
||||
- interrupt-names: name of the interrupts listed in interrupts property in
|
||||
the same order
|
||||
- clocks: from common clock binding: handle hardware IP needed clocks, the
|
||||
number of clocks may depend of the SoC type.
|
||||
- clock-names: names of the clocks listed in clocks property in the same
|
||||
order.
|
||||
- hdmi,hpd-gpio: gpio id to detect if an hdmi cable is plugged or not.
|
||||
|
||||
sti-hda:
|
||||
Required properties:
|
||||
must be a child of sti-tvout
|
||||
- compatible: "st,stih<chip>-hda"
|
||||
- reg: Physical base address of the IP registers and length of memory mapped region.
|
||||
- reg-names: names of the mapped memory regions listed in regs property in
|
||||
the same order.
|
||||
- clocks: from common clock binding: handle hardware IP needed clocks, the
|
||||
number of clocks may depend of the SoC type.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: names of the clocks listed in clocks property in the same
|
||||
order.
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
vtg_main_slave: sti-vtg-main-slave@fe85A800 {
|
||||
compatible = "st,vtg";
|
||||
reg = <0xfe85A800 0x300>;
|
||||
interrupts = <GIC_SPI 175 IRQ_TYPE_NONE>;
|
||||
};
|
||||
|
||||
vtg_main: sti-vtg-main-master@fd348000 {
|
||||
compatible = "st,vtg";
|
||||
reg = <0xfd348000 0x400>;
|
||||
st,slave = <&vtg_main_slave>;
|
||||
};
|
||||
|
||||
vtg_aux_slave: sti-vtg-aux-slave@fd348400 {
|
||||
compatible = "st,vtg";
|
||||
reg = <0xfe858200 0x300>;
|
||||
interrupts = <GIC_SPI 176 IRQ_TYPE_NONE>;
|
||||
};
|
||||
|
||||
vtg_aux: sti-vtg-aux-master@fd348400 {
|
||||
compatible = "st,vtg";
|
||||
reg = <0xfd348400 0x400>;
|
||||
st,slave = <&vtg_aux_slave>;
|
||||
};
|
||||
|
||||
|
||||
sti-vtac-rx-main@fee82800 {
|
||||
compatible = "st,vtac-main";
|
||||
reg = <0xfee82800 0x200>;
|
||||
clock-names = "vtac";
|
||||
clocks = <&clk_m_a2_div0 CLK_M_VTAC_MAIN_PHY>;
|
||||
};
|
||||
|
||||
sti-vtac-rx-aux@fee82a00 {
|
||||
compatible = "st,vtac-aux";
|
||||
reg = <0xfee82a00 0x200>;
|
||||
clock-names = "vtac";
|
||||
clocks = <&clk_m_a2_div0 CLK_M_VTAC_AUX_PHY>;
|
||||
};
|
||||
|
||||
sti-vtac-tx-main@fd349000 {
|
||||
compatible = "st,vtac-main";
|
||||
reg = <0xfd349000 0x200>, <0xfd320000 0x10000>;
|
||||
clock-names = "vtac";
|
||||
clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
|
||||
};
|
||||
|
||||
sti-vtac-tx-aux@fd349200 {
|
||||
compatible = "st,vtac-aux";
|
||||
reg = <0xfd349200 0x200>, <0xfd320000 0x10000>;
|
||||
clock-names = "vtac";
|
||||
clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
|
||||
};
|
||||
|
||||
sti-display-subsystem {
|
||||
compatible = "st,sti-display-subsystem";
|
||||
ranges;
|
||||
|
||||
sti-compositor@fd340000 {
|
||||
compatible = "st,stih416-compositor";
|
||||
reg = <0xfd340000 0x1000>;
|
||||
clock-names = "compo_main", "compo_aux",
|
||||
"pix_main", "pix_aux";
|
||||
clocks = <&clk_m_a2_div1 CLK_M_COMPO_MAIN>, <&clk_m_a2_div1 CLK_M_COMPO_AUX>,
|
||||
<&clockgen_c_vcc CLK_S_PIX_MAIN>, <&clockgen_c_vcc CLK_S_PIX_AUX>;
|
||||
reset-names = "compo-main", "compo-aux";
|
||||
resets = <&softreset STIH416_COMPO_M_SOFTRESET>, <&softreset STIH416_COMPO_A_SOFTRESET>;
|
||||
st,vtg = <&vtg_main>, <&vtg_aux>;
|
||||
};
|
||||
|
||||
sti-tvout@fe000000 {
|
||||
compatible = "st,stih416-tvout";
|
||||
reg = <0xfe000000 0x1000>, <0xfe85a000 0x400>, <0xfe830000 0x10000>;
|
||||
reg-names = "tvout-reg", "hda-reg", "syscfg";
|
||||
reset-names = "tvout";
|
||||
resets = <&softreset STIH416_HDTVOUT_SOFTRESET>;
|
||||
ranges;
|
||||
|
||||
sti-hdmi@fe85c000 {
|
||||
compatible = "st,stih416-hdmi";
|
||||
reg = <0xfe85c000 0x1000>, <0xfe830000 0x10000>;
|
||||
reg-names = "hdmi-reg", "syscfg";
|
||||
interrupts = <GIC_SPI 173 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "irq";
|
||||
clock-names = "pix", "tmds", "phy", "audio";
|
||||
clocks = <&clockgen_c_vcc CLK_S_PIX_HDMI>, <&clockgen_c_vcc CLK_S_TMDS_HDMI>, <&clockgen_c_vcc CLK_S_HDMI_REJECT_PLL>, <&clockgen_b1 CLK_S_PCM_0>;
|
||||
hdmi,hpd-gpio = <&PIO2 5>;
|
||||
};
|
||||
|
||||
sti-hda@fe85a000 {
|
||||
compatible = "st,stih416-hda";
|
||||
reg = <0xfe85a000 0x400>, <0xfe83085c 0x4>;
|
||||
reg-names = "hda-reg", "video-dacs-ctrl";
|
||||
clock-names = "pix", "hddac";
|
||||
clocks = <&clockgen_c_vcc CLK_S_PIX_HD>, <&clockgen_c_vcc CLK_S_HDDAC>;
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
};
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
IBM POWERNV platform sensors
|
||||
----------------------------
|
||||
|
||||
Required node properties:
|
||||
- compatible: must be one of
|
||||
"ibm,opal-sensor-cooling-fan"
|
||||
"ibm,opal-sensor-amb-temp"
|
||||
"ibm,opal-sensor-power-supply"
|
||||
"ibm,opal-sensor-power"
|
||||
- sensor-id: an opaque id provided by the firmware to the kernel, identifies a
|
||||
given sensor and its attribute data
|
||||
|
||||
Example sensors node:
|
||||
|
||||
cooling-fan#8-data {
|
||||
sensor-id = <0x7052107>;
|
||||
compatible = "ibm,opal-sensor-cooling-fan";
|
||||
};
|
||||
|
||||
amb-temp#1-thrs {
|
||||
sensor-id = <0x5096000>;
|
||||
compatible = "ibm,opal-sensor-amb-temp";
|
||||
};
|
||||
|
|
@ -3,6 +3,7 @@ NTC Thermistor hwmon sensors
|
|||
|
||||
Requires node properties:
|
||||
- "compatible" value : one of
|
||||
"epcos,b57330v2103"
|
||||
"murata,ncp15wb473"
|
||||
"murata,ncp18wb473"
|
||||
"murata,ncp21wb473"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,12 @@
|
|||
Bindings for a fan connected to the PWM lines
|
||||
|
||||
Required properties:
|
||||
- compatible : "pwm-fan"
|
||||
- pwms : the PWM that is used to control the PWM fan
|
||||
|
||||
Example:
|
||||
pwm-fan {
|
||||
compatible = "pwm-fan";
|
||||
status = "okay";
|
||||
pwms = <&pwm 0 10000 0>;
|
||||
};
|
||||
|
|
@ -10,7 +10,7 @@ Required properties :
|
|||
Recommended properties :
|
||||
|
||||
- clock-frequency : maximal I2C bus clock frequency in Hz.
|
||||
- efm32,location : Decides the location of the USART I/O pins.
|
||||
- energymicro,location : Decides the location of the USART I/O pins.
|
||||
Allowed range : [0 .. 6]
|
||||
|
||||
Example:
|
||||
|
|
@ -23,7 +23,7 @@ Example:
|
|||
clocks = <&cmu clk_HFPERCLKI2C0>;
|
||||
clock-frequency = <100000>;
|
||||
status = "ok";
|
||||
efm32,location = <3>;
|
||||
energymicro,location = <3>;
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "microchip,24c02";
|
||||
|
|
|
|||
|
|
@ -50,6 +50,7 @@ epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE
|
|||
fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer
|
||||
fsl,mc13892 MC13892: Power Management Integrated Circuit (PMIC) for i.MX35/51
|
||||
fsl,mma8450 MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer
|
||||
fsl,mma8452 MMA8452Q: 3-axis 12-bit / 8-bit Digital Accelerometer
|
||||
fsl,mpr121 MPR121: Proximity Capacitive Touch Sensor Controller
|
||||
fsl,sgtl5000 SGTL5000: Ultra Low-Power Audio Codec
|
||||
gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface
|
||||
|
|
@ -69,6 +70,7 @@ nuvoton,npct501 i2c trusted platform module (TPM)
|
|||
nxp,pca9556 Octal SMBus and I2C registered interface
|
||||
nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset
|
||||
nxp,pcf8563 Real-time clock/calendar
|
||||
nxp,pcf85063 Tiny Real-Time Clock
|
||||
ovti,ov5642 OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus
|
||||
pericom,pt7c4338 Real-time Clock Module
|
||||
plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch
|
||||
|
|
@ -83,5 +85,6 @@ stm,m41t80 M41T80 - SERIAL ACCESS RTC WITH ALARMS
|
|||
taos,tsl2550 Ambient Light Sensor with SMBUS/Two Wire Serial Interface
|
||||
ti,tsc2003 I2C Touch-Screen Controller
|
||||
ti,tmp102 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
|
||||
ti,tmp103 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
|
||||
ti,tmp275 Digital Temperature Sensor
|
||||
winbond,wpct301 i2c trusted platform module (TPM)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,22 @@
|
|||
* Maxim 1027/1029/1031 Analog to Digital Converter (ADC)
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "maxim,max1027" or "maxim,max1029" or "maxim,max1031"
|
||||
- reg: SPI chip select number for the device
|
||||
- interrupt-parent: phandle to the parent interrupt controller
|
||||
see: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
|
||||
- interrupts: IRQ line for the ADC
|
||||
see: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
|
||||
|
||||
Recommended properties:
|
||||
- spi-max-frequency: Definition as per
|
||||
Documentation/devicetree/bindings/spi/spi-bus.txt
|
||||
|
||||
Example:
|
||||
adc@0 {
|
||||
compatible = "maxim,max1027";
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <15 IRQ_TYPE_EDGE_RISING>;
|
||||
spi-max-frequency = <1000000>;
|
||||
};
|
||||
|
|
@ -3,6 +3,10 @@
|
|||
Required properties:
|
||||
|
||||
- compatible : should be "honeywell,hmc5843"
|
||||
Other models which are supported with driver are:
|
||||
"honeywell,hmc5883"
|
||||
"honeywell,hmc5883l"
|
||||
"honeywell,hmc5983"
|
||||
- reg : the I2C address of the magnetometer - typically 0x1e
|
||||
|
||||
Optional properties:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,54 @@
|
|||
STMicroelectronics MEMS sensors
|
||||
|
||||
The STMicroelectronics sensor devices are pretty straight-forward I2C or
|
||||
SPI devices, all sharing the same device tree descriptions no matter what
|
||||
type of sensor it is.
|
||||
|
||||
Required properties:
|
||||
- compatible: see the list of valid compatible strings below
|
||||
- reg: the I2C or SPI address the device will respond to
|
||||
|
||||
Optional properties:
|
||||
- vdd-supply: an optional regulator that needs to be on to provide VDD
|
||||
power to the sensor.
|
||||
- vddio-supply: an optional regulator that needs to be on to provide the
|
||||
VDD IO power to the sensor.
|
||||
- st,drdy-int-pin: the pin on the package that will be used to signal
|
||||
"data ready" (valid values: 1 or 2). This property is not configurable
|
||||
on all sensors.
|
||||
|
||||
Sensors may also have applicable pin control settings, those use the
|
||||
standard bindings from pinctrl/pinctrl-bindings.txt.
|
||||
|
||||
Valid compatible strings:
|
||||
|
||||
Accelerometers:
|
||||
- st,lsm303dlh-accel
|
||||
- st,lsm303dlhc-accel
|
||||
- st,lis3dh-accel
|
||||
- st,lsm330d-accel
|
||||
- st,lsm330dl-accel
|
||||
- st,lsm330dlc-accel
|
||||
- st,lis331dlh-accel
|
||||
- st,lsm303dl-accel
|
||||
- st,lsm303dlm-accel
|
||||
- st,lsm330-accel
|
||||
|
||||
Gyroscopes:
|
||||
- st,l3g4200d-gyro
|
||||
- st,lsm330d-gyro
|
||||
- st,lsm330dl-gyro
|
||||
- st,lsm330dlc-gyro
|
||||
- st,l3gd20-gyro
|
||||
- st,l3g4is-gyro
|
||||
- st,lsm330-gyro
|
||||
|
||||
Magnetometers:
|
||||
- st,lsm303dlhc-magn
|
||||
- st,lsm303dlm-magn
|
||||
- st,lis3mdl-magn
|
||||
|
||||
Pressure sensors:
|
||||
- st,lps001wp-press
|
||||
- st,lps25h-press
|
||||
- st,lps331ap-press
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
Atmel maXTouch touchscreen/touchpad
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
atmel,maxtouch
|
||||
|
||||
- reg: The I2C address of the device
|
||||
|
||||
- interrupts: The sink for the touchpad's IRQ output
|
||||
See ../interrupt-controller/interrupts.txt
|
||||
|
||||
Optional properties for main touchpad device:
|
||||
|
||||
- linux,gpio-keymap: An array of up to 4 entries indicating the Linux
|
||||
keycode generated by each GPIO. Linux keycodes are defined in
|
||||
<dt-bindings/input/input.h>.
|
||||
|
||||
Example:
|
||||
|
||||
touch@4b {
|
||||
compatible = "atmel,maxtouch";
|
||||
reg = <0x4b>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
Device tree bindings for Microchip CAP1106, 6 channel capacitive touch sensor
|
||||
|
||||
The node for this driver must be a child of a I2C controller node, as the
|
||||
device communication via I2C only.
|
||||
|
||||
Required properties:
|
||||
|
||||
compatible: Must be "microchip,cap1106"
|
||||
|
||||
reg: The I2C slave address of the device.
|
||||
Only 0x28 is valid.
|
||||
|
||||
interrupts: Property describing the interrupt line the
|
||||
device's ALERT#/CM_IRQ# pin is connected to.
|
||||
The device only has one interrupt source.
|
||||
|
||||
Optional properties:
|
||||
|
||||
autorepeat: Enables the Linux input system's autorepeat
|
||||
feature on the input device.
|
||||
|
||||
microchip,sensor-gain: Defines the gain of the sensor circuitry. This
|
||||
effectively controls the sensitivity, as a
|
||||
smaller delta capacitance is required to
|
||||
generate the same delta count values.
|
||||
Valid values are 1, 2, 4, and 8.
|
||||
By default, a gain of 1 is set.
|
||||
|
||||
linux,keycodes: Specifies an array of numeric keycode values to
|
||||
be used for the channels. If this property is
|
||||
omitted, KEY_A, KEY_B, etc are used as
|
||||
defaults. The array must have exactly six
|
||||
entries.
|
||||
|
||||
Example:
|
||||
|
||||
i2c_controller {
|
||||
cap1106@28 {
|
||||
compatible = "microchip,cap1106";
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <0 0>;
|
||||
reg = <0x28>;
|
||||
autorepeat;
|
||||
microchip,sensor-gain = <2>;
|
||||
|
||||
linux,keycodes = <103 /* KEY_UP */
|
||||
106 /* KEY_RIGHT */
|
||||
108 /* KEY_DOWN */
|
||||
105 /* KEY_LEFT */
|
||||
109 /* KEY_PAGEDOWN */
|
||||
104>; /* KEY_PAGEUP */
|
||||
};
|
||||
}
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
* Pixcir I2C touchscreen controllers
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "pixcir,pixcir_ts" or "pixcir,pixcir_tangoc"
|
||||
- reg: I2C address of the chip
|
||||
- interrupts: interrupt to which the chip is connected
|
||||
- attb-gpio: GPIO connected to the ATTB line of the chip
|
||||
- touchscreen-size-x: horizontal resolution of touchscreen (in pixels)
|
||||
- touchscreen-size-y: vertical resolution of touchscreen (in pixels)
|
||||
|
||||
Example:
|
||||
|
||||
i2c@00000000 {
|
||||
/* ... */
|
||||
|
||||
pixcir_ts@5c {
|
||||
compatible = "pixcir,pixcir_ts";
|
||||
reg = <0x5c>;
|
||||
interrupts = <2 0>;
|
||||
attb-gpio = <&gpf 2 0 2>;
|
||||
touchscreen-size-x = <800>;
|
||||
touchscreen-size-y = <600>;
|
||||
};
|
||||
|
||||
/* ... */
|
||||
};
|
||||
|
|
@ -9,6 +9,9 @@ Required properties:
|
|||
- x-size: horizontal resolution of touchscreen
|
||||
- y-size: vertical resolution of touchscreen
|
||||
|
||||
Optional properties:
|
||||
- vdd-supply: Regulator controlling the controller supply
|
||||
|
||||
Example:
|
||||
|
||||
i2c@00000000 {
|
||||
|
|
@ -18,6 +21,7 @@ Example:
|
|||
compatible = "neonode,zforce";
|
||||
reg = <0x50>;
|
||||
interrupts = <2 0>;
|
||||
vdd-supply = <®_zforce_vdd>;
|
||||
|
||||
gpios = <&gpio5 6 0>, /* INT */
|
||||
<&gpio5 9 0>; /* RST */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,23 @@
|
|||
OpenRISC 1000 Programmable Interrupt Controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "opencores,or1k-pic-level" for variants with
|
||||
level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with
|
||||
edge triggered interrupt lines or "opencores,or1200-pic" for machines
|
||||
with the non-spec compliant or1200 type implementation.
|
||||
|
||||
"opencores,or1k-pic" is also provided as an alias to "opencores,or1200-pic",
|
||||
but this is only for backwards compatibility.
|
||||
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt source. The value shall be 1.
|
||||
|
||||
Example:
|
||||
|
||||
intc: interrupt-controller {
|
||||
compatible = "opencores,or1k-pic-level";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
|
@ -42,12 +42,6 @@ conditions.
|
|||
|
||||
** System MMU optional properties:
|
||||
|
||||
- smmu-parent : When multiple SMMUs are chained together, this
|
||||
property can be used to provide a phandle to the
|
||||
parent SMMU (that is the next SMMU on the path going
|
||||
from the mmu-masters towards memory) node for this
|
||||
SMMU.
|
||||
|
||||
- calxeda,smmu-secure-config-access : Enable proper handling of buggy
|
||||
implementations that always use secure access to
|
||||
SMMU configuration registers. In this case non-secure
|
||||
|
|
|
|||
|
|
@ -0,0 +1,182 @@
|
|||
This document describes the generic device tree binding for IOMMUs and their
|
||||
master(s).
|
||||
|
||||
|
||||
IOMMU device node:
|
||||
==================
|
||||
|
||||
An IOMMU can provide the following services:
|
||||
|
||||
* Remap address space to allow devices to access physical memory ranges that
|
||||
they otherwise wouldn't be capable of accessing.
|
||||
|
||||
Example: 32-bit DMA to 64-bit physical addresses
|
||||
|
||||
* Implement scatter-gather at page level granularity so that the device does
|
||||
not have to.
|
||||
|
||||
* Provide system protection against "rogue" DMA by forcing all accesses to go
|
||||
through the IOMMU and faulting when encountering accesses to unmapped
|
||||
address regions.
|
||||
|
||||
* Provide address space isolation between multiple contexts.
|
||||
|
||||
Example: Virtualization
|
||||
|
||||
Device nodes compatible with this binding represent hardware with some of the
|
||||
above capabilities.
|
||||
|
||||
IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
|
||||
typically have a fixed association to the master device, whereas multiple-
|
||||
master IOMMU devices can translate accesses from more than one master.
|
||||
|
||||
The device tree node of the IOMMU device's parent bus must contain a valid
|
||||
"dma-ranges" property that describes how the physical address space of the
|
||||
IOMMU maps to memory. An empty "dma-ranges" property means that there is a
|
||||
1:1 mapping from IOMMU to memory.
|
||||
|
||||
Required properties:
|
||||
--------------------
|
||||
- #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
|
||||
address.
|
||||
|
||||
The meaning of the IOMMU specifier is defined by the device tree binding of
|
||||
the specific IOMMU. Below are a few examples of typical use-cases:
|
||||
|
||||
- #iommu-cells = <0>: Single master IOMMU devices are not configurable and
|
||||
therefore no additional information needs to be encoded in the specifier.
|
||||
This may also apply to multiple master IOMMU devices that do not allow the
|
||||
association of masters to be configured. Note that an IOMMU can by design
|
||||
be multi-master yet only expose a single master in a given configuration.
|
||||
In such cases the number of cells will usually be 1 as in the next case.
|
||||
- #iommu-cells = <1>: Multiple master IOMMU devices may need to be configured
|
||||
in order to enable translation for a given master. In such cases the single
|
||||
address cell corresponds to the master device's ID. In some cases more than
|
||||
one cell can be required to represent a single master ID.
|
||||
- #iommu-cells = <4>: Some IOMMU devices allow the DMA window for masters to
|
||||
be configured. The first cell of the address in this may contain the master
|
||||
device's ID for example, while the second cell could contain the start of
|
||||
the DMA window for the given device. The length of the DMA window is given
|
||||
by the third and fourth cells.
|
||||
|
||||
Note that these are merely examples and real-world use-cases may use different
|
||||
definitions to represent their individual needs. Always refer to the specific
|
||||
IOMMU binding for the exact meaning of the cells that make up the specifier.
|
||||
|
||||
|
||||
IOMMU master node:
|
||||
==================
|
||||
|
||||
Devices that access memory through an IOMMU are called masters. A device can
|
||||
have multiple master interfaces (to one or more IOMMU devices).
|
||||
|
||||
Required properties:
|
||||
--------------------
|
||||
- iommus: A list of phandle and IOMMU specifier pairs that describe the IOMMU
|
||||
master interfaces of the device. One entry in the list describes one master
|
||||
interface of the device.
|
||||
|
||||
When an "iommus" property is specified in a device tree node, the IOMMU will
|
||||
be used for address translation. If a "dma-ranges" property exists in the
|
||||
device's parent node it will be ignored. An exception to this rule is if the
|
||||
referenced IOMMU is disabled, in which case the "dma-ranges" property of the
|
||||
parent shall take effect. Note that merely disabling a device tree node does
|
||||
not guarantee that the IOMMU is really disabled since the hardware may not
|
||||
have a means to turn off translation. But it is invalid in such cases to
|
||||
disable the IOMMU's device tree node in the first place because it would
|
||||
prevent any driver from properly setting up the translations.
|
||||
|
||||
|
||||
Notes:
|
||||
======
|
||||
|
||||
One possible extension to the above is to use an "iommus" property along with
|
||||
a "dma-ranges" property in a bus device node (such as PCI host bridges). This
|
||||
can be useful to describe how children on the bus relate to the IOMMU if they
|
||||
are not explicitly listed in the device tree (e.g. PCI devices). However, the
|
||||
requirements of that use-case haven't been fully determined yet. Implementing
|
||||
this is therefore not recommended without further discussion and extension of
|
||||
this binding.
|
||||
|
||||
|
||||
Examples:
|
||||
=========
|
||||
|
||||
Single-master IOMMU:
|
||||
--------------------
|
||||
|
||||
iommu {
|
||||
#iommu-cells = <0>;
|
||||
};
|
||||
|
||||
master {
|
||||
iommus = <&{/iommu}>;
|
||||
};
|
||||
|
||||
Multiple-master IOMMU with fixed associations:
|
||||
----------------------------------------------
|
||||
|
||||
/* multiple-master IOMMU */
|
||||
iommu {
|
||||
/*
|
||||
* Masters are statically associated with this IOMMU and share
|
||||
* the same address translations because the IOMMU does not
|
||||
* have sufficient information to distinguish between masters.
|
||||
*
|
||||
* Consequently address translation is always on or off for
|
||||
* all masters at any given point in time.
|
||||
*/
|
||||
#iommu-cells = <0>;
|
||||
};
|
||||
|
||||
/* static association with IOMMU */
|
||||
master@1 {
|
||||
reg = <1>;
|
||||
iommus = <&{/iommu}>;
|
||||
};
|
||||
|
||||
/* static association with IOMMU */
|
||||
master@2 {
|
||||
reg = <2>;
|
||||
iommus = <&{/iommu}>;
|
||||
};
|
||||
|
||||
Multiple-master IOMMU:
|
||||
----------------------
|
||||
|
||||
iommu {
|
||||
/* the specifier represents the ID of the master */
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
master@1 {
|
||||
/* device has master ID 42 in the IOMMU */
|
||||
iommus = <&{/iommu} 42>;
|
||||
};
|
||||
|
||||
master@2 {
|
||||
/* device has master IDs 23 and 24 in the IOMMU */
|
||||
iommus = <&{/iommu} 23>, <&{/iommu} 24>;
|
||||
};
|
||||
|
||||
Multiple-master IOMMU with configurable DMA window:
|
||||
---------------------------------------------------
|
||||
|
||||
/ {
|
||||
iommu {
|
||||
/*
|
||||
* One cell for the master ID and one cell for the
|
||||
* address of the DMA window. The length of the DMA
|
||||
* window is encoded in two cells.
|
||||
*
|
||||
* The DMA window is the range addressable by the
|
||||
* master (i.e. the I/O virtual address space).
|
||||
*/
|
||||
#iommu-cells = <4>;
|
||||
};
|
||||
|
||||
master {
|
||||
/* master ID 42, 4 GiB DMA window starting at 0 */
|
||||
iommus = <&{/iommu} 42 0 0x1 0x0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,18 +1,19 @@
|
|||
LEDs connected to pca9632, pca9633 or pca9634
|
||||
|
||||
Required properties:
|
||||
- compatible : should be : "nxp,pca9632", "nxp,pca9633" or "nxp,pca9634"
|
||||
- compatible : should be : "nxp,pca9632", "nxp,pca9633", "nxp,pca9634" or "nxp,pca9635"
|
||||
|
||||
Optional properties:
|
||||
- nxp,totem-pole : use totem pole (push-pull) instead of default open-drain
|
||||
- nxp,totem-pole : use totem pole (push-pull) instead of open-drain (pca9632 defaults
|
||||
to open-drain, newer chips to totem pole)
|
||||
- nxp,hw-blink : use hardware blinking instead of software blinking
|
||||
|
||||
Each led is represented as a sub-node of the nxp,pca963x device.
|
||||
|
||||
LED sub-node properties:
|
||||
- label : (optional) see Documentation/devicetree/bindings/leds/common.txt
|
||||
- reg : number of LED line (could be from 0 to 3 in pca9632 or pca9633
|
||||
or 0 to 7 in pca9634)
|
||||
- reg : number of LED line (could be from 0 to 3 in pca9632 or pca9633,
|
||||
0 to 7 in pca9634, or 0 to 15 in pca9635)
|
||||
- linux,default-trigger : (optional)
|
||||
see Documentation/devicetree/bindings/leds/common.txt
|
||||
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ Required properties:
|
|||
|
||||
Optional properties:
|
||||
- gpio-controller: allows lines to be used as output-only GPIOs.
|
||||
- #gpio-cells: if present, must be 0.
|
||||
- #gpio-cells: if present, must not be 0.
|
||||
|
||||
Each led is represented as a sub-node of the ti,tca6507 device.
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,51 @@
|
|||
Atmel Image Sensor Interface (ISI) SoC Camera Subsystem
|
||||
----------------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "atmel,at91sam9g45-isi"
|
||||
- reg: physical base address and length of the registers set for the device;
|
||||
- interrupts: should contain IRQ line for the ISI;
|
||||
- clocks: list of clock specifiers, corresponding to entries in
|
||||
the clock-names property;
|
||||
- clock-names: must contain "isi_clk", which is the isi peripherial clock.
|
||||
|
||||
ISI supports a single port node with parallel bus. It should contain one
|
||||
'port' child node with child 'endpoint' node. Please refer to the bindings
|
||||
defined in Documentation/devicetree/bindings/media/video-interfaces.txt.
|
||||
|
||||
Example:
|
||||
isi: isi@f0034000 {
|
||||
compatible = "atmel,at91sam9g45-isi";
|
||||
reg = <0xf0034000 0x4000>;
|
||||
interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
|
||||
clocks = <&isi_clk>;
|
||||
clock-names = "isi_clk";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_isi>;
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
isi_0: endpoint {
|
||||
remote-endpoint = <&ov2640_0>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c1: i2c@f0018000 {
|
||||
ov2640: camera@0x30 {
|
||||
compatible = "omnivision,ov2640";
|
||||
reg = <0x30>;
|
||||
|
||||
port {
|
||||
ov2640_0: endpoint {
|
||||
remote-endpoint = <&isi_0>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -3,9 +3,13 @@ Samsung S5P/EXYNOS SoC series JPEG codec
|
|||
Required properties:
|
||||
|
||||
- compatible : should be one of:
|
||||
"samsung,s5pv210-jpeg", "samsung,exynos4210-jpeg";
|
||||
"samsung,s5pv210-jpeg", "samsung,exynos4210-jpeg",
|
||||
"samsung,exynos3250-jpeg";
|
||||
- reg : address and length of the JPEG codec IP register set;
|
||||
- interrupts : specifies the JPEG codec IP interrupt;
|
||||
- clocks : should contain the JPEG codec IP gate clock specifier, from the
|
||||
common clock bindings;
|
||||
- clock-names : should contain "jpeg" entry.
|
||||
- clock-names : should contain:
|
||||
- "jpeg" for the core gate clock,
|
||||
- "sclk" for the special clock (optional).
|
||||
- clocks : should contain the clock specifier and clock ID list
|
||||
matching entries in the clock-names property; from
|
||||
the common clock bindings.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,28 @@
|
|||
Micron 1.3Mp CMOS Digital Image Sensor
|
||||
|
||||
The Micron MT9M111 is a CMOS active pixel digital image sensor with an active
|
||||
array size of 1280H x 1024V. It is programmable through a simple two-wire serial
|
||||
interface.
|
||||
|
||||
Required Properties:
|
||||
- compatible: value should be "micron,mt9m111"
|
||||
|
||||
For further reading on port node refer to
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt.
|
||||
|
||||
Example:
|
||||
|
||||
i2c_master {
|
||||
mt9m111@5d {
|
||||
compatible = "micron,mt9m111";
|
||||
reg = <0x5d>;
|
||||
|
||||
remote = <&pxa_camera>;
|
||||
port {
|
||||
mt9m111_1: endpoint {
|
||||
bus-width = <8>;
|
||||
remote-endpoint = <&pxa_camera>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
Marvell PXA camera host interface
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "marvell,pxa270-qci"
|
||||
- reg: register base and size
|
||||
- interrupts: the interrupt number
|
||||
- any required generic properties defined in video-interfaces.txt
|
||||
|
||||
Optional properties:
|
||||
- clocks: input clock (see clock-bindings.txt)
|
||||
- clock-output-names: should contain the name of the clock driving the
|
||||
sensor master clock MCLK
|
||||
- clock-frequency: host interface is driving MCLK, and MCLK rate is this rate
|
||||
|
||||
Example:
|
||||
|
||||
pxa_camera: pxa_camera@50000000 {
|
||||
compatible = "marvell,pxa270-qci";
|
||||
reg = <0x50000000 0x1000>;
|
||||
interrupts = <33>;
|
||||
|
||||
clocks = <&pxa2xx_clks 24>;
|
||||
clock-names = "ciclk";
|
||||
clock-frequency = <50000000>;
|
||||
clock-output-names = "qci_mclk";
|
||||
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Parallel bus endpoint */
|
||||
qci: endpoint@0 {
|
||||
reg = <0>; /* Local endpoint # */
|
||||
remote-endpoint = <&mt9m111_1>;
|
||||
bus-width = <8>; /* Used data lines */
|
||||
hsync-active = <0>; /* Active low */
|
||||
vsync-active = <0>; /* Active low */
|
||||
pclk-sample = <1>; /* Rising */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
Renesas RCar Video Input driver (rcar_vin)
|
||||
------------------------------------------
|
||||
|
||||
The rcar_vin device provides video input capabilities for the Renesas R-Car
|
||||
family of devices. The current blocks are always slaves and suppot one input
|
||||
channel which can be either RGB, YUYV or BT656.
|
||||
|
||||
- compatible: Must be one of the following
|
||||
- "renesas,vin-r8a7791" for the R8A7791 device
|
||||
- "renesas,vin-r8a7790" for the R8A7790 device
|
||||
- "renesas,vin-r8a7779" for the R8A7779 device
|
||||
- "renesas,vin-r8a7778" for the R8A7778 device
|
||||
- reg: the register base and size for the device registers
|
||||
- interrupts: the interrupt for the device
|
||||
- clocks: Reference to the parent clock
|
||||
|
||||
Additionally, an alias named vinX will need to be created to specify
|
||||
which video input device this is.
|
||||
|
||||
The per-board settings:
|
||||
- port sub-node describing a single endpoint connected to the vin
|
||||
as described in video-interfaces.txt[1]. Only the first one will
|
||||
be considered as each vin interface has one input port.
|
||||
|
||||
These settings are used to work out video input format and widths
|
||||
into the system.
|
||||
|
||||
|
||||
Device node example
|
||||
-------------------
|
||||
|
||||
aliases {
|
||||
vin0 = &vin0;
|
||||
};
|
||||
|
||||
vin0: vin@0xe6ef0000 {
|
||||
compatible = "renesas,vin-r8a7790";
|
||||
clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
|
||||
reg = <0 0xe6ef0000 0 0x1000>;
|
||||
interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
Board setup example (vin1 composite video input)
|
||||
------------------------------------------------
|
||||
|
||||
&i2c2 {
|
||||
status = "ok";
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
adv7180@20 {
|
||||
compatible = "adi,adv7180";
|
||||
reg = <0x20>;
|
||||
remote = <&vin1>;
|
||||
|
||||
port {
|
||||
adv7180: endpoint {
|
||||
bus-width = <8>;
|
||||
remote-endpoint = <&vin1ep0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* composite video input */
|
||||
&vin1 {
|
||||
pinctrl-0 = <&vin1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "ok";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vin1ep0: endpoint {
|
||||
remote-endpoint = <&adv7180>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
|
||||
[1] video-interfaces.txt common video media interface
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
Device-Tree bindings for SUNXI IR controller found in sunXi SoC family
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "allwinner,sun4i-a10-ir";
|
||||
- clocks : list of clock specifiers, corresponding to
|
||||
entries in clock-names property;
|
||||
- clock-names : should contain "apb" and "ir" entries;
|
||||
- interrupts : should contain IR IRQ number;
|
||||
- reg : should contain IO map address for IR.
|
||||
|
||||
Optional properties:
|
||||
- linux,rc-map-name : Remote control map name.
|
||||
|
||||
Example:
|
||||
|
||||
ir0: ir@01c21800 {
|
||||
compatible = "allwinner,sun4i-a10-ir";
|
||||
clocks = <&apb0_gates 6>, <&ir0_clk>;
|
||||
clock-names = "apb", "ir";
|
||||
interrupts = <0 5 1>;
|
||||
reg = <0x01C21800 0x40>;
|
||||
linux,rc-map-name = "rc-rc6-mce";
|
||||
};
|
||||
|
|
@ -42,6 +42,16 @@ Optional properties:
|
|||
the chip default will be used. If present exactly five values must
|
||||
be specified.
|
||||
|
||||
- DCVDD-supply, MICVDD-supply : Power supplies, only need to be specified if
|
||||
they are being externally supplied. As covered in
|
||||
Documentation/devicetree/bindings/regulator/regulator.txt
|
||||
|
||||
Optional subnodes:
|
||||
- ldo1 : Initial data for the LDO1 regulator, as covered in
|
||||
Documentation/devicetree/bindings/regulator/regulator.txt
|
||||
- micvdd : Initial data for the MICVDD regulator, as covered in
|
||||
Documentation/devicetree/bindings/regulator/regulator.txt
|
||||
|
||||
Example:
|
||||
|
||||
codec: wm5102@1a {
|
||||
|
|
|
|||
|
|
@ -13,6 +13,14 @@ Required properties:
|
|||
The second cell is the flags, encoded as the trigger masks from binding document
|
||||
interrupts.txt, using dt-bindings/irq.
|
||||
|
||||
Optional properties:
|
||||
--------------------
|
||||
- ams,enable-internal-int-pullup: Boolean property, to enable internal pullup on
|
||||
interrupt pin. Missing this will disable internal pullup on INT pin.
|
||||
- ams,enable-internal-i2c-pullup: Boolean property, to enable internal pullup on
|
||||
i2c scl/sda pins. Missing this will disable internal pullup on i2c
|
||||
scl/sda lines.
|
||||
|
||||
Optional submodule and their properties:
|
||||
=======================================
|
||||
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@ twl6037 (palmas)
|
|||
tps65913 (palmas)
|
||||
tps65914 (palmas)
|
||||
tps659038
|
||||
tps65917
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be from the list
|
||||
|
|
@ -16,6 +17,7 @@ Required properties:
|
|||
ti,tps65914
|
||||
ti,tps80036
|
||||
ti,tps659038
|
||||
ti,tps65917
|
||||
and also the generic series names
|
||||
ti,palmas
|
||||
- interrupt-controller : palmas has its own internal IRQs
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
|
||||
* Samsung S2MPS11 and S2MPS14 Voltage and Current Regulator
|
||||
* Samsung S2MPS11, S2MPS14 and S2MPU02 Voltage and Current Regulator
|
||||
|
||||
The Samsung S2MPS11 is a multi-function device which includes voltage and
|
||||
current regulators, RTC, charger controller and other sub-blocks. It is
|
||||
|
|
@ -7,7 +7,8 @@ interfaced to the host controller using an I2C interface. Each sub-block is
|
|||
addressed by the host system using different I2C slave addresses.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "samsung,s2mps11-pmic" or "samsung,s2mps14-pmic".
|
||||
- compatible: Should be "samsung,s2mps11-pmic" or "samsung,s2mps14-pmic"
|
||||
or "samsung,s2mpu02-pmic".
|
||||
- reg: Specifies the I2C slave address of the pmic block. It should be 0x66.
|
||||
|
||||
Optional properties:
|
||||
|
|
@ -81,11 +82,13 @@ as per the datasheet of s2mps11.
|
|||
- valid values for n are:
|
||||
- S2MPS11: 1 to 38
|
||||
- S2MPS14: 1 to 25
|
||||
- Example: LDO1, LD02, LDO28
|
||||
- S2MPU02: 1 to 28
|
||||
- Example: LDO1, LDO2, LDO28
|
||||
- BUCKn
|
||||
- valid values for n are:
|
||||
- S2MPS11: 1 to 10
|
||||
- S2MPS14: 1 to 5
|
||||
- S2MPU02: 1 to 7
|
||||
- Example: BUCK1, BUCK2, BUCK9
|
||||
|
||||
Example:
|
||||
|
|
@ -96,7 +99,7 @@ Example:
|
|||
|
||||
s2m_osc: clocks {
|
||||
compatible = "samsung,s2mps11-clk";
|
||||
#clock-cells = 1;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "xx", "yy", "zz";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ PRCM is an MFD device exposing several Power Management related devices
|
|||
(like clks and reset controllers).
|
||||
|
||||
Required properties:
|
||||
- compatible: "allwinner,sun6i-a31-prcm"
|
||||
- compatible: "allwinner,sun6i-a31-prcm" or "allwinner,sun8i-a23-prcm"
|
||||
- reg: The PRCM registers range
|
||||
|
||||
The prcm node may contain several subdevices definitions:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,13 @@
|
|||
NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 apbmisc block
|
||||
|
||||
Required properties:
|
||||
- compatible : should be:
|
||||
"nvidia,tegra20-apbmisc"
|
||||
"nvidia,tegra30-apbmisc"
|
||||
"nvidia,tegra114-apbmisc"
|
||||
"nvidia,tegra124-apbmisc"
|
||||
- reg: Should contain 2 entries: the first entry gives the physical address
|
||||
and length of the registers which contain revision and debug features.
|
||||
The second entry gives the physical address and length of the
|
||||
registers indicating the strapping options.
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue