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Fix bug in the SDRAM initialization code for canmb, IceCube and 

PM520 boards.

Fix PHY address for canmb board.
This commit is contained in:
wdenk 2005-04-21 21:10:22 +00:00
parent 7cc1438d43
commit a63109281a
7 changed files with 32 additions and 20 deletions
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4
CHANGELOG
View File

@ -2,6 +2,10 @@
Changes for U-Boot 1.1.3:
======================================================================
* Fix bug in the SDRAM initialization code for canmb, IceCube and
PM520 boards.
Fix PHY address for canmb board.
* Cleanup serial console baudrate calculation on AT91RM9200;
get rid of obsolete CFG_AT91C_BRGR_DIVISOR definition

11
board/canmb/canmb.c
View File

@ -133,10 +133,13 @@ long int initdram (int board_type)
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
/* find RAM size using SDRAM CS1 only */
sdram_start(0);
test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
sdram_start(1);
test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
if (!dramsize)
sdram_start(0);
test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
if (!dramsize) {
sdram_start(1);
test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
}
if (test1 > test2) {
sdram_start(0);
dramsize2 = test1;

11
board/icecube/icecube.c
View File

@ -133,10 +133,13 @@ long int initdram (int board_type)
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
/* find RAM size using SDRAM CS1 only */
sdram_start(0);
test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
sdram_start(1);
test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
if (!dramsize)
sdram_start(0);
test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
if (!dramsize) {
sdram_start(1);
test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
}
if (test1 > test2) {
sdram_start(0);
dramsize2 = test1;

11
board/pm520/pm520.c
View File

@ -133,10 +133,13 @@ long int initdram (int board_type)
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
/* find RAM size using SDRAM CS1 only */
sdram_start(0);
test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
sdram_start(1);
test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
if (!dramsize)
sdram_start(0);
test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
if (!dramsize) {
sdram_start(1);
test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
}
if (test1 > test2) {
sdram_start(0);
dramsize2 = test1;

4
cpu/mpc85xx/ether_fcc.c
View File

@ -157,7 +157,7 @@ static int fec_send(struct eth_device* dev, volatile void *packet, int length)
rtx.txbd[txIdx].cbd_bufaddr = (uint)packet;
rtx.txbd[txIdx].cbd_datlen = length;
rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | \
BD_ENET_TX_TC );
BD_ENET_TX_TC | BD_ENET_TX_PAD);
for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
if (i >= TOUT_LOOP) {
@ -414,7 +414,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
immr->im_cpm.im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
}
return 0;
return 1;
}
static void fec_halt(struct eth_device* dev)

9
include/configs/TQM8560.h
View File

@ -279,18 +279,17 @@
#define TSEC2_PHY_ADDR 1
#define TSEC2_PHYIDX 0
#endif /* CONFIG_TSEC_ENET */
#define CONFIG_ETHER_ON_FCC
#define CONFIG_ETHER_ON_FCC3
#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
#define CFG_CMXFCR_VALUE3 (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14)
#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
#define CFG_CPMFCR_RAMTYPE 0
#define CFG_FCC_PSMR (FCC_PSMR_FDE)
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
#define CONFIG_ETHPRIME "ENET1"
#endif /* CONFIG_TSEC_ENET */
/*
* Environment
*/

2
include/configs/canmb.h
View File

@ -167,7 +167,7 @@
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
#define CONFIG_PHY_ADDR 0x1
#define CONFIG_PHY_ADDR 0x0
/*
* GPIO configuration:
* PSC1,2,3 predefined as UART