boards: Add phytec-phyflex-am335x
Add support for PHYTEC's phyFLEX-AM335x. Signed-off-by: Stefan Müller-Klieser <s.mueller-klieser@phytec.de> [clean ups] Signed-off-by: Teresa Gámez <t.gamez@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Stefan Müller-Klieser
Sascha Hauer
parent
83620fb6eb
commit
a6b696108c
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@ -79,6 +79,7 @@ obj-$(CONFIG_MACH_PCM038) += phytec-phycore-imx27/
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obj-$(CONFIG_MACH_PCM043) += phytec-phycore-imx35/
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obj-$(CONFIG_MACH_PCM049) += phytec-phycore-omap4460/
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obj-$(CONFIG_MACH_PCM051) += phytec-phycore-am335x/
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obj-$(CONFIG_MACH_PFLA03) += phytec-phyflex-am335x/
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obj-$(CONFIG_MACH_PHYTEC_PFLA02) += phytec-phyflex-imx6/
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obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += plathome-openblocks-ax3/
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obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += plathome-openblocks-a6/
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@ -0,0 +1,3 @@
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lwl-y += lowlevel.o
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obj-y += board.o
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bbenv-y += defaultenv-phyflex-am335x
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@ -0,0 +1,100 @@
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/*
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* pfla03 - phyFLEX-AM335x Board Initalization Code
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*
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* Copyright (C) 2014 Stefan Müller-Klieser, Phytec Messtechnik GmbH
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*
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* Based on arch/arm/boards/omap/board-beagle.c
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <bootsource.h>
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#include <common.h>
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#include <nand.h>
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#include <init.h>
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#include <io.h>
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#include <sizes.h>
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#include <envfs.h>
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#include <asm/armlinux.h>
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#include <generated/mach-types.h>
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#include <linux/phy.h>
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#include <linux/micrel_phy.h>
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#include <mach/am33xx-generic.h>
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#include <mach/am33xx-silicon.h>
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#include <mach/bbu.h>
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static int ksz9031rn_phy_fixup(struct phy_device *dev)
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{
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phy_write_mmd_indirect(dev, 6, 2, 0);
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phy_write_mmd_indirect(dev, 8, 2, 0x003ff);
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return 0;
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}
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static int pfla03_coredevice_init(void)
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{
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if (!of_machine_is_compatible("phytec,phyflex-am335x-som"))
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return 0;
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phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
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ksz9031rn_phy_fixup);
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am33xx_register_ethaddr(0, 0);
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am33xx_register_ethaddr(1, 1);
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return 0;
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}
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coredevice_initcall(pfla03_coredevice_init);
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static struct omap_barebox_part pfla03_barebox_part = {
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.nand_offset = SZ_512K,
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.nand_size = SZ_512K,
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.nor_offset = SZ_128K,
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.nor_size = SZ_512K,
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};
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static char *xloadslots[] = {
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"/dev/nand0.xload.bb",
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"/dev/nand0.xload_backup1.bb",
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"/dev/nand0.xload_backup2.bb",
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"/dev/nand0.xload_backup3.bb"
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};
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static int pfla03_devices_init(void)
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{
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if (!of_machine_is_compatible("phytec,phyflex-am335x-som"))
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return 0;
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switch (bootsource_get()) {
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case BOOTSOURCE_SPI:
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of_device_enable_path("/chosen/environment-spi");
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break;
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case BOOTSOURCE_MMC:
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omap_set_bootmmc_devname("mmc0");
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break;
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default:
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of_device_enable_path("/chosen/environment-nand");
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break;
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}
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omap_set_barebox_part(&pfla03_barebox_part);
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armlinux_set_architecture(MACH_TYPE_PFLA03);
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defaultenv_append_directory(defaultenv_phyflex_am335x);
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am33xx_bbu_spi_nor_mlo_register_handler("MLO.spi", "/dev/m25p0.xload");
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am33xx_bbu_spi_nor_register_handler("spi", "/dev/m25p0.barebox");
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am33xx_bbu_nand_xloadslots_register_handler("MLO.nand",
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xloadslots, ARRAY_SIZE(xloadslots));
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am33xx_bbu_nand_register_handler("nand", "/dev/nand0.barebox.bb");
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return 0;
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}
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device_initcall(pfla03_devices_init);
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@ -0,0 +1,8 @@
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#!/bin/sh
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global.bootm.image=/boot/linuximage
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#global.bootm.oftree=/boot/oftree
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bootargs-ip
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global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootfstype=ext3 rw rootwait"
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@ -0,0 +1,8 @@
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#!/bin/sh
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global.bootm.image="/dev/nand0.kernel.bb"
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#global.bootm.oftree="/env/oftree"
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bootargs-ip
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global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root,2048 rw rootfstype=ubifs"
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@ -0,0 +1,8 @@
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#!/bin/sh
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global.bootm.image="/dev/m25p0.kernel"
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bootargs-ip
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# Use rootfs form NAND for now as rootfs partition < 4MB
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global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root,2048 rw rootfstype=ubifs"
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@ -0,0 +1,17 @@
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#!/bin/sh
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# board defaults, do not change in running system. Change /env/config
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# instead
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global.hostname=pfla03
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global.linux.bootargs.base="console=ttyO0,115200"
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if [ $bootsource = mmc ]; then
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global.boot.default="mmc nand spi net"
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elif [ $boosource = nand ]; then
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global.boot.default="nand spi mmc net"
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elif [ $boosource = spi ]; then
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global.boot.default="spi nand mmc net"
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elif [ $boosource = net ]; then
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global.boot.default="net nand spi mmc"
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fi
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@ -0,0 +1,180 @@
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/*
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* pfla03 - phyFLEX-AM335x lowlevel code
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*
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* Copyright (C) 2014 Stefan Müller-Klieser, Phytec Messtechnik GmbH
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*
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* Based on arch/arm/boards/omap/board-beagle.c
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <sizes.h>
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#include <io.h>
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#include <init.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/barebox-arm.h>
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#include <mach/am33xx-silicon.h>
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#include <mach/am33xx-clock.h>
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#include <mach/generic.h>
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#include <mach/sdrc.h>
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#include <mach/sys_info.h>
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#include <mach/syslib.h>
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#include <mach/am33xx-mux.h>
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#include <mach/am33xx-generic.h>
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#include <mach/wdt.h>
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#include <debug_ll.h>
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#define CLK_M_OSC_MHZ 25
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#define DDR_IOCTRL 0x18B
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static const struct am33xx_cmd_control pfla03_cmd = {
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.slave_ratio0 = 0x80,
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.dll_lock_diff0 = 0x0,
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.invert_clkout0 = 0x0,
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.slave_ratio1 = 0x80,
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.dll_lock_diff1 = 0x0,
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.invert_clkout1 = 0x0,
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.slave_ratio2 = 0x80,
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.dll_lock_diff2 = 0x0,
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.invert_clkout2 = 0x0,
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};
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struct pfla03_sdram_timings {
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struct am33xx_emif_regs regs;
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struct am33xx_ddr_data data;
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};
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enum {
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MT41K128M16JT_256MB,
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MT41K256M16HA_512MB,
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};
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struct pfla03_sdram_timings pfla03_timings[] = {
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/* 256 MB */
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[MT41K128M16JT_256MB] = {
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.regs = {
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.emif_read_latency = 0x7,
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.emif_tim1 = 0x0AAAD4DB,
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.emif_tim2 = 0x26437FDA,
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.emif_tim3 = 0x501F83FF,
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.sdram_config = 0x61C052B2,
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.zq_config = 0x50074BE4,
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.sdram_ref_ctrl = 0x00000C30,
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},
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.data = {
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.rd_slave_ratio0 = 0x34,
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.wr_dqs_slave_ratio0 = 0x47,
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.fifo_we_slave_ratio0 = 0x9a,
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.wr_slave_ratio0 = 0x7e,
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.use_rank0_delay = 0x0,
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.dll_lock_diff0 = 0x0,
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},
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},
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/* 512 MB */
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[MT41K256M16HA_512MB] = {
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.regs = {
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.emif_read_latency = 0x7,
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.emif_tim1 = 0x0AAAE4DB,
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.emif_tim2 = 0x266B7FDA,
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.emif_tim3 = 0x501F867F,
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.sdram_config = 0x61C05332,
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.zq_config = 0x50074BE4,
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.sdram_ref_ctrl = 0x00000C30,
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},
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.data = {
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.rd_slave_ratio0 = 0x36,
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.wr_dqs_slave_ratio0 = 0x47,
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.fifo_we_slave_ratio0 = 0x95,
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.wr_slave_ratio0 = 0x7f,
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.use_rank0_delay = 0x0,
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.dll_lock_diff0 = 0x0,
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},
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},
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};
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extern char __dtb_am335x_phytec_phyflex_start[];
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/**
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* @brief The basic entry point for board initialization.
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*
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* This is called as part of machine init (after arch init).
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* This is again called with stack in SRAM, so not too many
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* constructs possible here.
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*
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* @return void
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*/
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static noinline void pfla03_board_init(int sdram)
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{
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void *fdt;
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struct pfla03_sdram_timings *timing = &pfla03_timings[sdram];
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/*
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* WDT1 is already running when the bootloader gets control
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* Disable it to avoid "random" resets
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*/
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writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
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while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
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writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
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while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
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am33xx_pll_init(MPUPLL_M_600, CLK_M_OSC_MHZ, DDRPLL_M_400);
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am335x_sdram_init(DDR_IOCTRL, &pfla03_cmd,
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&timing->regs,
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&timing->data);
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am33xx_uart_soft_reset((void *)AM33XX_UART0_BASE);
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am33xx_enable_uart0_pin_mux();
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omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE);
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putc_ll('>');
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fdt = __dtb_am335x_phytec_phyflex_start - get_runtime_offset();
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am335x_barebox_entry(fdt);
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}
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static noinline void pfla03_board_entry(unsigned long bootinfo, int sdram)
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{
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am33xx_save_bootinfo((void *)bootinfo);
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arm_cpu_lowlevel_init();
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/*
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* Setup C environment, the board init code uses global variables.
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* Stackpointer has already been initialized by the ROM code.
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*/
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relocate_to_current_adr();
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setup_c();
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pfla03_board_init(sdram);
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}
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ENTRY_FUNCTION(start_am33xx_phytec_phyflex_sram_256mb, bootinfo, r1, r2)
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{
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pfla03_board_entry(bootinfo, MT41K128M16JT_256MB);
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}
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ENTRY_FUNCTION(start_am33xx_phytec_phyflex_sram_512mb, bootinfo, r1, r2)
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{
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pfla03_board_entry(bootinfo, MT41K256M16HA_512MB);
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}
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ENTRY_FUNCTION(start_am33xx_phytec_phyflex_sdram, r0, r1, r2)
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{
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void *fdt;
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fdt = __dtb_am335x_phytec_phyflex_start - get_runtime_offset();
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am335x_barebox_entry(fdt);
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}
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@ -27,6 +27,7 @@ pbl-dtb-$(CONFIG_MACH_PCA100) += imx27-phytec-phycard-s-rdk-bb.dtb.o
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pbl-dtb-$(CONFIG_MACH_PCAAXL3) += imx6q-phytec-pbaa03.dtb.o
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pbl-dtb-$(CONFIG_MACH_PCM038) += imx27-phytec-phycore-rdk.dtb.o
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pbl-dtb-$(CONFIG_MACH_PCM051) += am335x-phytec-phycore.dtb.o
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pbl-dtb-$(CONFIG_MACH_PFLA03) += am335x-phytec-phyflex.dtb.o
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pbl-dtb-$(CONFIG_MACH_PHYTEC_PFLA02) += imx6s-phytec-pbab01.dtb.o imx6dl-phytec-pbab01.dtb.o imx6q-phytec-pbab01.dtb.o
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pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o
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pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o
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@ -0,0 +1,356 @@
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/dts-v1/;
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#include "am33xx.dtsi"
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/ {
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model = "Phytec phyFLEX AM335x";
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compatible = "phytec,phyflex-am335x-som", "ti,am33xx";
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chosen {
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linux,stdout-path = &uart0;
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environment-spi {
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compatible = "barebox,environment";
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device-path = &flash, "partname:bareboxenv";
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status = "disabled";
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};
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environment-nand {
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compatible = "barebox,environment";
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device-path = &nand, "partname:bareboxenv";
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status = "disabled";
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};
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};
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vcc5v: fixedregulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-boot-on;
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};
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vcc3v3: fixedregulator@1 {
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compatible = "regulator-fixed";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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};
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&am33xx_pinmux {
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i2c0_pins: pinmux_i2c0_pins {
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pinctrl-single,pins = <
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0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda */
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0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl */
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>;
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};
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spi0_pins: pinmux_spi0_pins {
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pinctrl-single,pins = <
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0x150 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */
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0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */
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0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
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0x15c (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
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>;
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};
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uart0_pins: pinmux_uart0_pins {
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pinctrl-single,pins = <
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0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd */
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0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd */
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>;
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};
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mmc1_pins: pinmux_mmc1_pins {
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pinctrl-single,pins = <
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0x0f0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */
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0x0f4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */
|
||||
0x0f8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */
|
||||
0x0fc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */
|
||||
0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */
|
||||
0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */
|
||||
>;
|
||||
};
|
||||
|
||||
emac_rgmii1_pins: pinmux_emac_rgmii1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_tx_en.rgmii1_tctl */
|
||||
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rx_dv.rgmii1_rctl */
|
||||
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
|
||||
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
|
||||
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
|
||||
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
|
||||
0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_tx_clk.rgmii1_tclk */
|
||||
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rx_clk.rgmii1_rclk */
|
||||
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
|
||||
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
|
||||
>;
|
||||
};
|
||||
|
||||
emac_rmii2_pins: pinmux_emac_rmii2_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x040 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a0.rmii2_txen */
|
||||
0x050 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a4.rmii2_txd1 */
|
||||
0x054 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a5.rmii2_txd0 */
|
||||
0x068 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* gpmc_a10.rmii2_rxd1 */
|
||||
0x06c (PIN_INPUT_PULLDOWN | MUX_MODE3) /* gpmc_a11.rmii2_rxd0 */
|
||||
0x074 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wpn.rmii2_rxer */
|
||||
0x108 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_col.rmii2_refclk */
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_default: davinci_mdio_default {
|
||||
pinctrl-single,pins = <
|
||||
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data */
|
||||
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk */
|
||||
>;
|
||||
};
|
||||
|
||||
nandflash_pins_s0: nandflash_pins_s0 {
|
||||
pinctrl-single,pins = <
|
||||
0x000 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0 */
|
||||
0x004 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1 */
|
||||
0x008 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2 */
|
||||
0x00c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3 */
|
||||
0x010 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4 */
|
||||
0x014 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5 */
|
||||
0x018 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6 */
|
||||
0x01c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7 */
|
||||
0x070 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
|
||||
0x07c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_csn0 */
|
||||
0x090 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_advn_ale */
|
||||
0x094 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_oen_ren */
|
||||
0x098 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_wen */
|
||||
0x09c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_be0n_cle */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps: pmic@2d {
|
||||
reg = <0x2d>;
|
||||
};
|
||||
|
||||
at24c32: eeprom@52 {
|
||||
compatible = "atmel,24c32";
|
||||
byte_len = <4096>;
|
||||
pagesize = <32>;
|
||||
reg = <0x52>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
status = "okay";
|
||||
flash: m25p80 {
|
||||
compatible = "m25p80";
|
||||
spi-max-frequency = <48000000>;
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
m25p,fast-read;
|
||||
|
||||
partition@0 {
|
||||
label = "xload";
|
||||
reg = <0x0 0x20000>;
|
||||
};
|
||||
|
||||
partition@1 {
|
||||
label = "barebox";
|
||||
reg = <0x20000 0x80000>;
|
||||
};
|
||||
|
||||
partition@2 {
|
||||
label = "bareboxenv";
|
||||
reg = <0xa0000 0x20000>;
|
||||
};
|
||||
|
||||
partition@3 {
|
||||
label = "oftree";
|
||||
reg = <0xc0000 0x20000>;
|
||||
};
|
||||
|
||||
partition@4 {
|
||||
label = "kernel";
|
||||
reg = <0xe0000 0x400000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&davinci_mdio_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&phy_sel {
|
||||
rmii-clock-ext;
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <1>;
|
||||
phy-mode = "rgmii";
|
||||
dual_emac_res_vlan = <1>;
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
phy_id = <&davinci_mdio>, <2>;
|
||||
phy-mode = "rmii";
|
||||
dual_emac_res_vlan = <2>;
|
||||
};
|
||||
|
||||
&mac {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emac_rgmii1_pins &emac_rmii2_pins>;
|
||||
dual_emac;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&elm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nandflash_pins_s0>;
|
||||
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
|
||||
nand: nand@0,0 {
|
||||
reg = <0 0 0>; /* CS0, offset 0 */
|
||||
nand-bus-width = <8>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
gpmc,device-nand = "true";
|
||||
gpmc,device-width = <1>;
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <30>;
|
||||
gpmc,cs-wr-off-ns = <30>;
|
||||
gpmc,adv-on-ns = <0>;
|
||||
gpmc,adv-rd-off-ns = <30>;
|
||||
gpmc,adv-wr-off-ns = <30>;
|
||||
gpmc,we-on-ns = <0>;
|
||||
gpmc,we-off-ns = <20>;
|
||||
gpmc,oe-on-ns = <10>;
|
||||
gpmc,oe-off-ns = <30>;
|
||||
gpmc,access-ns = <30>;
|
||||
gpmc,rd-cycle-ns = <30>;
|
||||
gpmc,wr-cycle-ns = <30>;
|
||||
gpmc,wait-pin = <1>;
|
||||
gpmc,wait-on-read = "true";
|
||||
gpmc,wait-on-write = "true";
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <50>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-access-ns = <0>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
elm_id = <&elm>;
|
||||
|
||||
partition@0 {
|
||||
label = "xload";
|
||||
reg = <0x0 0x20000>;
|
||||
};
|
||||
|
||||
partition@1 {
|
||||
label = "xload_backup1";
|
||||
reg = <0x20000 0x20000>;
|
||||
};
|
||||
|
||||
partition@2 {
|
||||
label = "xload_backup2";
|
||||
reg = <0x40000 0x20000>;
|
||||
};
|
||||
|
||||
partition@3 {
|
||||
label = "xload_backup3";
|
||||
reg = <0x60000 0x20000>;
|
||||
};
|
||||
|
||||
partition@4 {
|
||||
label = "barebox";
|
||||
reg = <0x80000 0x80000>;
|
||||
};
|
||||
|
||||
partition@5 {
|
||||
label = "bareboxenv";
|
||||
reg = <0x100000 0x20000>;
|
||||
};
|
||||
|
||||
partition@6 {
|
||||
label = "oftree";
|
||||
reg = <0x120000 0x20000>;
|
||||
};
|
||||
|
||||
partition@7 {
|
||||
label = "kernel";
|
||||
reg = <0x140000 0x800000>;
|
||||
};
|
||||
|
||||
partition@8 {
|
||||
label = "root";
|
||||
reg = <0x940000 0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "tps65217.dtsi"
|
||||
&tps {
|
||||
vcc1-supply = <&vcc5v>;
|
||||
vcc2-supply = <&vcc5v>;
|
||||
vcc3-supply = <&vcc5v>;
|
||||
vcc4-supply = <&vcc5v>;
|
||||
vcc5-supply = <&vcc5v>;
|
||||
vcc6-supply = <&vcc5v>;
|
||||
vcc7-supply = <&vcc5v>;
|
||||
vccio-supply = <&vcc5v>;
|
||||
|
||||
regulators {
|
||||
vdd1_reg: regulator@2 {
|
||||
/* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <912500>;
|
||||
regulator-max-microvolt = <1378000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd2_reg: regulator@3 {
|
||||
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <912500>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vmmc_reg: regulator@12 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
|
@ -143,6 +143,11 @@ config MACH_PCM051
|
|||
help
|
||||
Say Y here if you are using Phytecs phyCORE pcm051 board
|
||||
|
||||
config MACH_PFLA03
|
||||
bool "Phytec phyFLEX am335x pfla03"
|
||||
select ARCH_AM33XX
|
||||
help
|
||||
Say Y here if you are using Phytecs phyFLEX pfla03 board
|
||||
endif
|
||||
|
||||
choice
|
||||
|
|
|
|||
|
|
@ -35,6 +35,18 @@ pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_2x512mb
|
|||
FILE_barebox-am33xx-phytec-phycore-mlo-2x512mb.img = start_am33xx_phytec_phycore_sram_2x512mb.pblx.mlo
|
||||
am33xx-mlo-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore-mlo-2x512mb.img
|
||||
|
||||
pblx-$(CONFIG_MACH_PFLA03) += start_am33xx_phytec_phyflex_sdram
|
||||
FILE_barebox-am33xx-phytec-phyflex.img = start_am33xx_phytec_phyflex_sdram.pblx
|
||||
am33xx-barebox-$(CONFIG_MACH_PFLA03) += barebox-am33xx-phytec-phyflex.img
|
||||
|
||||
pblx-$(CONFIG_MACH_PFLA03) += start_am33xx_phytec_phyflex_sram_256mb
|
||||
FILE_barebox-am33xx-phytec-phyflex-mlo-256mb.img = start_am33xx_phytec_phyflex_sram_256mb.pblx.mlo
|
||||
am33xx-mlo-$(CONFIG_MACH_PFLA03) += barebox-am33xx-phytec-phyflex-mlo-256mb.img
|
||||
|
||||
pblx-$(CONFIG_MACH_PFLA03) += start_am33xx_phytec_phyflex_sram_512mb
|
||||
FILE_barebox-am33xx-phytec-phyflex-mlo-512mb.img = start_am33xx_phytec_phyflex_sram_512mb.pblx.mlo
|
||||
am33xx-mlo-$(CONFIG_MACH_PFLA03) += barebox-am33xx-phytec-phyflex-mlo-512mb.img
|
||||
|
||||
pblx-$(CONFIG_MACH_BEAGLEBONE) += start_am33xx_beaglebone_sdram
|
||||
FILE_barebox-am33xx-beaglebone.img = start_am33xx_beaglebone_sdram.pblx
|
||||
am33xx-barebox-$(CONFIG_MACH_BEAGLEBONE) += barebox-am33xx-beaglebone.img
|
||||
|
|
|
|||
Loading…
Reference in New Issue