Merge branch 'for-next/pxa'
This commit is contained in:
Sascha Hauer
commit
a76a6bc8fd
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@ -58,6 +58,7 @@ obj-$(CONFIG_MACH_IMX21ADS) += freescale-mx21-ads/
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obj-$(CONFIG_MACH_IMX233_OLINUXINO) += imx233-olinuxino/
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obj-$(CONFIG_MACH_IMX27ADS) += freescale-mx27-ads/
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obj-$(CONFIG_MACH_LUBBOCK) += lubbock/
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obj-$(CONFIG_MACH_MAINSTONE) += mainstone/
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obj-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += marvell-armada-xp-gp/
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obj-$(CONFIG_MACH_MB7707) += module-mb7707/
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obj-$(CONFIG_MACH_MIOA701) += mioa701/
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@ -0,0 +1,2 @@
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obj-y += board.o
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lwl-y += lowlevel.o
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@ -0,0 +1,134 @@
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/*
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* (C) 2015 Robert Jarzmik <robert.jarzmik@free.fr>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <driver.h>
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#include <environment.h>
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#include <fs.h>
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#include <init.h>
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#include <partition.h>
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#include <led.h>
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#include <gpio.h>
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#include <pwm.h>
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#include <linux/sizes.h>
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#include <mach/devices.h>
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#include <mach/mfp-pxa27x.h>
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#include <mach/pxa-regs.h>
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#include <mach/udc_pxa2xx.h>
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#include <mach/mci_pxa2xx.h>
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#include <net/smc91111.h>
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#include <asm/armlinux.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <generated/mach-types.h>
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static struct smc91c111_pdata smsc91x_pdata = {
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.word_aligned_short_writes = true,
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};
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static unsigned long mainstone_pin_config[] = {
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GPIO15_nCS_1, /* CS1 - Flash */
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GPIO78_nCS_2, /* CS2 - Baseboard FGPA + SRAM */
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GPIO80_nCS_4, /* CS4 - SMC ethernet */
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/* Ethernet: static memory VLIO */
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GPIO18_RDY,
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/* PC Card */
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GPIO48_nPOE,
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GPIO49_nPWE,
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GPIO50_nPIOR,
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GPIO51_nPIOW,
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GPIO85_nPCE_1,
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GPIO54_nPCE_2,
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GPIO79_PSKTSEL,
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GPIO55_nPREG,
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GPIO56_nPWAIT,
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GPIO57_nIOIS16,
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/* MMC */
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GPIO32_MMC_CLK,
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GPIO112_MMC_CMD,
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GPIO92_MMC_DAT_0,
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GPIO109_MMC_DAT_1,
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GPIO110_MMC_DAT_2,
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GPIO111_MMC_DAT_3,
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/* LCD - 16bpp DSTN */
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GPIOxx_LCD_TFT_16BPP,
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/* Backlight */
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GPIO16_PWM0_OUT,
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/* FFUART */
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GPIO34_FFUART_RXD,
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GPIO35_FFUART_CTS,
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GPIO36_FFUART_DCD,
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GPIO37_FFUART_DSR,
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GPIO38_FFUART_RI,
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GPIO39_FFUART_TXD,
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GPIO40_FFUART_DTR,
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GPIO41_FFUART_RTS,
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};
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static int mainstone_devices_init(void)
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{
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void *nor0_iospace;
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armlinux_set_architecture(MACH_TYPE_MAINSTONE);
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pxa_add_uart((void *)0x40100000, 0);
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pxa_add_pwm((void *)0x40b00000, 0);
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nor0_iospace = map_io_sections(0x0, (void *)0xe0000000, SZ_64M);
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add_cfi_flash_device(0, (ulong)nor0_iospace, SZ_64M, 0);
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add_cfi_flash_device(1, 0x04000000, SZ_64M, 0);
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devfs_add_partition("nor0", SZ_2M, SZ_256K, DEVFS_PARTITION_FIXED,
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"env0");
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add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL,
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0x10000300, 0xff4000, IORESOURCE_MEM,
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&smsc91x_pdata);
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return 0;
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}
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device_initcall(mainstone_devices_init);
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static int mainstone_coredevice_init(void)
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{
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/*
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* Put the board in superspeed (520 MHz) to speed-up logo/OS loading.
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*/
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CCCR = CCCR_A | 0x20290;
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barebox_set_model("Mainstone PXA27x");
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barebox_set_hostname("mainstone");
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pxa2xx_mfp_config(ARRAY_AND_SIZE(mainstone_pin_config));
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return 0;
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}
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coredevice_initcall(mainstone_coredevice_init);
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static int mainstone_mem_init(void)
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{
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arm_add_mem_device("ram0", 0xa0000000, SZ_64M);
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add_mem_device("sram0", 0x0a000000, SZ_1M, IORESOURCE_MEM_WRITEABLE);
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return 0;
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}
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mem_initcall(mainstone_mem_init);
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@ -0,0 +1,5 @@
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#!/bin/sh
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global.bootm.image="/dev/nor0.kernel"
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#global.bootm.oftree="/env/oftree"
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global.linux.bootargs.dyn.root="root=ubi0:linux_root ubi.mtd=nor0.root rootfstype=ubifs"
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@ -0,0 +1,11 @@
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#!/bin/sh
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if [ "$1" = menu ]; then
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init-menu-add-entry "$0" "NOR partitions"
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exit
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fi
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mtdparts="2048k@0(nor0.barebox)ro,256k(nor0.barebox-env),256k(nor0.barebox-logo),256k(nor0.barebox-logo2),5120k(nor0.kernel),-(nor0.root)"
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kernelname="application-flash"
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mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts}
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@ -0,0 +1 @@
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console=ttyS0,115200
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@ -0,0 +1,264 @@
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/barebox-arm.h>
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#include <linux/sizes.h>
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#include <mach/pxa-regs.h>
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#include <mach/regs-ost.h>
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/*
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* Memory settings
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*/
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#define DEFAULT_MSC0_VAL 0x23F2B8F2
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#define DEFAULT_MSC1_VAL 0x7ff0fff1
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/*
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* MSC2: static partitions 4 and 5
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*
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* [31] 0 - RBUFF5
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* [30:28] 111 - RRR5
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* [27:24] 1111- RDN5
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* [23:20] 1111- RDF5
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* [19] 0 - RBW5
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* [18:16] 000 - RT5
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* [15] 0 - RBUFF4: Slow device (don't wait for data return)
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* [14:12] 111 - RRR4: Toff=(2*RRR + 1)*CLK_MEM (from nCS=1 to next nCS=0)
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* [11:8] 1111- RDN4: T=2*RDN*CLK_MEM (from nOE=1 to addr hold)
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* [7:4] 1111- RDF4: T=RDF*CLK_MEM of hold nOE/nPWE for read/write
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* [3] 0 - RBW4: Bus width is 32 bits
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* [2:0] 000 - RT4: Partition is VLIO
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*/
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#define DEFAULT_MSC2_VAL 0x7ff0fff4
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/*
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* MDCNFG: SDRAM Configuration Register
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*
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* [31] 0 - Memory map 0/1 uses normal 256 MBytes
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* [30] 0 - dcacx2: no extra column addressing
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* [29] 0 - reserved
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* [28] 0 - SA1111 compatiblity mode
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* [27] 0 - latch return data with return clock
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* [26] 0 - alternate addressing for pair 2/3
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* [25:24] 00 - timings
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* [23] 0 - internal banks in lower partition 2/3 (not used)
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* [22:21] 00 - row address bits for partition 2/3 (not used)
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* [20:19] 00 - column address bits for partition 2/3 (not used)
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* [18] 0 - SDRAM partition 2/3 width is 32 bit
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* [17] 0 - SDRAM partition 3 disabled
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* [16] 0 - SDRAM partition 2 disabled
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* [15] 0 - Stack1 : see stack0
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* [14] 0 - dcacx0 : no extra column addressing
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* [13] 0 - stack0 : stack = 0b00 => SDRAM address placed on MA<24:10>
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* [12] 0 - SA1110 compatiblity mode
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* [11] 1 - always 1
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* [10] 0 - no alternate addressing for pair 0/1
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* [09:08] 10 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=7*MemClk tRC=11*MemClk
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* [7] 1 - 4 internal banks in partitions 0/1
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* [06:05] 10 - drac0: 13 row address bits for partition 0/1
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* [04:03] 01 - dcac0: 9 column address bits for partition 0/1
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* [02] 0 - SDRAM partition 0/1 width is 32 bit
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* [01] 1 - enable SDRAM partition 1
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* [00] 1 - enable SDRAM partition 0
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*
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* Configuration is for 1 bank of 64MBytes (13 rows * 9 cols)
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* in bank0, of width 32 bits, with 4 internal banks.
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* Timings (in times of SDCLK<1>): tRP = 3clk, CL=3, rRCD=3clk,
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* tRAS=7clk, tRC=11clk
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*/
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#define DEFAULT_MDCNFG_VAL 0x00000acb
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/*
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* MDREFR: SDRAM Configuration Register
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*
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* [25] 0 - K2FREE=0
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* [24] 0 - K1FREE=0
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* [23] 0 - K0FREE=0
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* [22] 0 - SLFRSH=0
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* [21]
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* [20] 0 - APD
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* [19] 0 - K2DB2=0
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* [18] 0 - K2RUN=0
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* [17] 1 - K1DB2=1
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* [16] 1 - K1RUN=1
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* [15] 0 - EP1IN
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* [14] 1 - K0DB2=1
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* [13] 1 - K0RUN=1
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* [12]
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* [11..0] 17 - DRI=17
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*/
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#define DEFAULT_MDREFR_VAL 0x00036017
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#define DEFAULT_MDMRS_VAL 0x00320032
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#define DEFAULT_FLYCNFG_VAL 0x00000000
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#define DEFAULT_SXCNFG_VAL 0x40044004
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/*
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* PCMCIA and CF Interfaces
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*/
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#define DEFAULT_MECR_VAL 0x00000001
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#define DEFAULT_MCMEM0_VAL 0x00014307
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#define DEFAULT_MCMEM1_VAL 0x00014307
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#define DEFAULT_MCATT0_VAL 0x0001c787
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#define DEFAULT_MCATT1_VAL 0x0001c787
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#define DEFAULT_MCIO0_VAL 0x0001430f
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#define DEFAULT_MCIO1_VAL 0x0001430f
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static inline void writelrb(uint32_t val, volatile u32 __iomem *addr)
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{
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writel(val, addr);
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barrier();
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readl(addr);
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barrier();
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}
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static inline void pxa_wait_ticks(int ticks)
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{
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writel(0, &OSCR);
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while (readl(&OSCR) < ticks)
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barrier();
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}
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static inline void pxa2xx_dram_init(void)
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{
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uint32_t tmp, mask;
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int i;
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/*
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* 1) Initialize Asynchronous static memory controller
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||||
*/
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writelrb(DEFAULT_MSC1_VAL, &MSC1);
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writelrb(DEFAULT_MSC2_VAL, &MSC2);
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||||
/*
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* 2) Initialize Card Interface
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||||
*/
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||||
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||||
/* MECR: Memory Expansion Card Register */
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||||
writelrb(DEFAULT_MECR_VAL, &MECR);
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||||
/* MCMEM0: Card Interface slot 0 timing */
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||||
writelrb(DEFAULT_MCMEM0_VAL, &MCMEM0);
|
||||
/* MCMEM1: Card Interface slot 1 timing */
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||||
writelrb(DEFAULT_MCMEM1_VAL, &MCMEM1);
|
||||
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
|
||||
writelrb(DEFAULT_MCATT0_VAL, &MCATT0);
|
||||
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
|
||||
writelrb(DEFAULT_MCATT1_VAL, &MCATT1);
|
||||
/* MCIO0: Card Interface I/O Space Timing, slot 0 */
|
||||
writelrb(DEFAULT_MCIO0_VAL, &MCIO0);
|
||||
/* MCIO1: Card Interface I/O Space Timing, slot 1 */
|
||||
writelrb(DEFAULT_MCIO1_VAL, &MCIO1);
|
||||
|
||||
/*
|
||||
* 3) Configure Fly-By DMA register
|
||||
*/
|
||||
|
||||
writelrb(DEFAULT_FLYCNFG_VAL, &FLYCNFG);
|
||||
|
||||
/*
|
||||
* 4) Initialize Timing for Sync Memory (SDCLK0)
|
||||
*/
|
||||
|
||||
/*
|
||||
* Before accessing MDREFR we need a valid DRI field, so we set
|
||||
* this to power on defaults + DRI field.
|
||||
*/
|
||||
|
||||
/* Read current MDREFR config and zero out DRI */
|
||||
tmp = readl(&MDREFR) & ~0xfff;
|
||||
tmp |= DEFAULT_MDREFR_VAL & 0xfff;
|
||||
writelrb(tmp, &MDREFR);
|
||||
|
||||
/* clear the free-running clock bits (clear K0Free, K1Free, K2Free) */
|
||||
mask = MDREFR_K0FREE | MDREFR_K1FREE | MDREFR_K2FREE |
|
||||
MDREFR_K0DB2 | MDREFR_K0DB4 | MDREFR_K1DB2 | MDREFR_K2DB2 |
|
||||
MDREFR_K0RUN | MDREFR_K1RUN | MDREFR_K2RUN;
|
||||
tmp &= ~mask;
|
||||
tmp |= (DEFAULT_MDREFR_VAL & mask);
|
||||
writelrb(tmp, &MDREFR);
|
||||
|
||||
/*
|
||||
* 5) Initialize Synchronous Static Memory (Flash/Peripherals)
|
||||
*/
|
||||
|
||||
/* Initialize SXCNFG register. Assert the enable bits.
|
||||
*
|
||||
* Write SXMRS to cause an MRS command to all enabled banks of
|
||||
* synchronous static memory. Note that SXLCR need not be written
|
||||
* at this time.
|
||||
*/
|
||||
writelrb(DEFAULT_SXCNFG_VAL, &SXCNFG);
|
||||
|
||||
/*
|
||||
* 6) Initialize SDRAM
|
||||
*/
|
||||
|
||||
tmp &= ~MDREFR_SLFRSH;
|
||||
writelrb(tmp, &MDREFR);
|
||||
tmp |= MDREFR_E1PIN;
|
||||
writelrb(tmp, &MDREFR);
|
||||
|
||||
/*
|
||||
* 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
|
||||
* but not enable each SDRAM partition pair.
|
||||
*/
|
||||
|
||||
mask = MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3;
|
||||
writelrb(DEFAULT_MDCNFG_VAL & ~mask, &MDCNFG);
|
||||
|
||||
/* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
|
||||
pxa_wait_ticks(0x300);
|
||||
|
||||
/*
|
||||
* 8) Trigger a number (usually 8) refresh cycles by attempting
|
||||
* non-burst read or write accesses to disabled SDRAM, as commonly
|
||||
* specified in the power up sequence documented in SDRAM data
|
||||
* sheets. The address(es) used for this purpose must not be
|
||||
* cacheable.
|
||||
*/
|
||||
for (i = 9; i >= 0; i--) {
|
||||
readl(0xa0000000);
|
||||
barrier();
|
||||
}
|
||||
/*
|
||||
* 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
|
||||
*/
|
||||
|
||||
tmp = (readl(&MDCNFG) & ~mask) | (DEFAULT_MDCNFG_VAL & mask);
|
||||
writelrb(tmp, &MDCNFG);
|
||||
|
||||
/*
|
||||
* 10) Write MDMRS.
|
||||
*/
|
||||
writelrb(DEFAULT_MDMRS_VAL, &MDMRS);
|
||||
|
||||
/*
|
||||
* 11) Enable APD
|
||||
*/
|
||||
if (DEFAULT_MDREFR_VAL & MDREFR_APD) {
|
||||
tmp = readl(&MDREFR);
|
||||
tmp |= MDREFR_APD;
|
||||
writelrb(tmp, &MDREFR);
|
||||
}
|
||||
}
|
||||
|
||||
void __bare_init __naked barebox_arm_reset_vector(void)
|
||||
{
|
||||
unsigned long pssr = PSSR;
|
||||
unsigned long pc = get_pc();
|
||||
|
||||
arm_cpu_lowlevel_init();
|
||||
CKEN |= CKEN_OSTIMER | CKEN_MEMC | CKEN_FFUART;
|
||||
|
||||
/*
|
||||
* When not running from SDRAM, get it out of self refresh, and/or
|
||||
* initialize it.
|
||||
*/
|
||||
if (!(pc >= 0xa0000000 && pc < 0xb0000000))
|
||||
pxa2xx_dram_init();
|
||||
|
||||
if ((pssr >= 0xa0000000 && pssr < 0xb0000000) ||
|
||||
(pssr >= 0x04000000 && pssr < 0x10000000))
|
||||
asm("mov pc, %0" : : "r"(pssr) : );
|
||||
|
||||
barebox_arm_entry(0xa0000000, SZ_64M, 0);
|
||||
}
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
CONFIG_ARCH_PXA=y
|
||||
CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x100000
|
||||
CONFIG_ARCH_PXA27X=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_ARM_BOARD_APPEND_ATAG=y
|
||||
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
|
||||
CONFIG_ARM_UNWIND=y
|
||||
# CONFIG_BANNER is not set
|
||||
CONFIG_MMU=y
|
||||
CONFIG_TEXT_BASE=0xa3d00000
|
||||
CONFIG_BAREBOX_MAX_BARE_INIT_SIZE=0x80000
|
||||
CONFIG_MALLOC_SIZE=0x1000000
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_KALLSYMS=y
|
||||
CONFIG_PROMPT="mainstone-barebox:"
|
||||
CONFIG_HUSH_FANCY_PROMPT=y
|
||||
CONFIG_CMDLINE_EDITING=y
|
||||
CONFIG_AUTO_COMPLETE=y
|
||||
CONFIG_MENU=y
|
||||
CONFIG_CONSOLE_ACTIVATE_ALL=y
|
||||
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
|
||||
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/mainstone/env"
|
||||
CONFIG_RESET_SOURCE=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_CMD_DMESG=y
|
||||
CONFIG_LONGHELP=y
|
||||
CONFIG_CMD_IOMEM=y
|
||||
CONFIG_CMD_MEMINFO=y
|
||||
CONFIG_CMD_BOOTM_SHOW_TYPE=y
|
||||
CONFIG_CMD_BOOTM_VERBOSE=y
|
||||
CONFIG_CMD_BOOTM_INITRD=y
|
||||
CONFIG_CMD_BOOTM_OFTREE=y
|
||||
CONFIG_CMD_GO=y
|
||||
CONFIG_CMD_LOADB=y
|
||||
CONFIG_CMD_LOADS=y
|
||||
CONFIG_CMD_LOADY=y
|
||||
CONFIG_CMD_RESET=y
|
||||
CONFIG_CMD_SAVES=y
|
||||
CONFIG_CMD_PARTITION=y
|
||||
CONFIG_CMD_UBIFORMAT=y
|
||||
CONFIG_CMD_EXPORT=y
|
||||
CONFIG_CMD_LOADENV=y
|
||||
CONFIG_CMD_PRINTENV=y
|
||||
CONFIG_CMD_MAGICVAR=y
|
||||
CONFIG_CMD_MAGICVAR_HELP=y
|
||||
CONFIG_CMD_SAVEENV=y
|
||||
CONFIG_CMD_FILETYPE=y
|
||||
CONFIG_CMD_LN=y
|
||||
CONFIG_CMD_UNCOMPRESS=y
|
||||
CONFIG_CMD_LET=y
|
||||
CONFIG_CMD_MSLEEP=y
|
||||
CONFIG_CMD_SLEEP=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_HOST=y
|
||||
CONFIG_CMD_MIITOOL=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_TFTP=y
|
||||
CONFIG_CMD_ECHO_E=y
|
||||
CONFIG_CMD_EDIT=y
|
||||
CONFIG_CMD_MENU=y
|
||||
CONFIG_CMD_MENU_MANAGEMENT=y
|
||||
CONFIG_CMD_SPLASH=y
|
||||
CONFIG_CMD_READLINE=y
|
||||
CONFIG_CMD_TIMEOUT=y
|
||||
CONFIG_CMD_CRC=y
|
||||
CONFIG_CMD_CRC_CMP=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_MM=y
|
||||
CONFIG_CMD_DETECT=y
|
||||
CONFIG_CMD_FLASH=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_LED=y
|
||||
CONFIG_CMD_POWEROFF=y
|
||||
CONFIG_CMD_LSMOD=y
|
||||
CONFIG_CMD_OF_NODE=y
|
||||
CONFIG_CMD_OF_PROPERTY=y
|
||||
CONFIG_CMD_OFTREE=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_NET_NETCONSOLE=y
|
||||
CONFIG_OFDEVICE=y
|
||||
CONFIG_OF_BAREBOX_DRIVERS=y
|
||||
CONFIG_DRIVER_SERIAL_PXA=y
|
||||
CONFIG_DRIVER_NET_SMC91111=y
|
||||
# CONFIG_SPI is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_DRIVER_CFI=y
|
||||
# CONFIG_DRIVER_CFI_AMD is not set
|
||||
CONFIG_CFI_BUFFER_WRITE=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MCI=y
|
||||
CONFIG_MCI_PXA=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_KEYBOARD_GPIO=y
|
||||
CONFIG_GENERIC_PHY=y
|
||||
CONFIG_FS_CRAMFS=y
|
||||
CONFIG_FS_EXT4=y
|
||||
CONFIG_FS_TFTP=y
|
||||
CONFIG_FS_FAT=y
|
||||
CONFIG_FS_FAT_WRITE=y
|
||||
CONFIG_FS_FAT_LFN=y
|
||||
CONFIG_FS_UBIFS=y
|
||||
CONFIG_FS_UBIFS_COMPRESSION_LZO=y
|
||||
CONFIG_FS_UBIFS_COMPRESSION_ZLIB=y
|
||||
CONFIG_BZLIB=y
|
||||
CONFIG_BMP=y
|
||||
CONFIG_PNG=y
|
||||
|
|
@ -60,6 +60,11 @@ choice
|
|||
prompt "PXA27x Board Type"
|
||||
bool
|
||||
|
||||
config MACH_MAINSTONE
|
||||
bool "Mainstone board"
|
||||
select PWM
|
||||
help
|
||||
Say Y here if you are using a Mainstone board
|
||||
config MACH_MIOA701
|
||||
bool "Mitac Mio A701"
|
||||
select BCH_CONST_PARAMS
|
||||
|
|
|
|||
|
|
@ -560,6 +560,20 @@ static inline void a32_insl(void __iomem *base, unsigned int offset, void *data,
|
|||
readsl(base + (offset << shift), data, count);
|
||||
}
|
||||
|
||||
static void a16_outw_algn4(unsigned value, void __iomem *base,
|
||||
unsigned int offset, unsigned shift)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
if ((offset << shift) & 2) {
|
||||
v = value << 16;
|
||||
v |= (a32_inl(base, offset & ~2, shift) & 0xffff);
|
||||
a32_outl(v, base, offset & ~2, shift);
|
||||
} else {
|
||||
writew(value, base + (offset << shift));
|
||||
}
|
||||
}
|
||||
|
||||
static const struct accessors access_via_16bit = {
|
||||
.ob = a8_outb,
|
||||
.ow = a16_outw,
|
||||
|
|
@ -583,6 +597,18 @@ static const struct accessors access_via_32bit = {
|
|||
.isl = a32_insl,
|
||||
};
|
||||
|
||||
/* access happens via a 32 bit bus, writes must by word aligned */
|
||||
static const struct accessors access_via_32bit_aligned_short_writes = {
|
||||
.ob = a8_outb,
|
||||
.ow = a16_outw_algn4,
|
||||
.ol = a32_outl,
|
||||
.osl = a32_outsl,
|
||||
.ib = a8_inb,
|
||||
.iw = a16_inw,
|
||||
.il = a32_inl,
|
||||
.isl = a32_insl,
|
||||
};
|
||||
|
||||
/* ------------------------------------------------------------------------ */
|
||||
|
||||
static unsigned last_bank;
|
||||
|
|
@ -1435,6 +1461,9 @@ static int smc91c111_probe(struct device_d *dev)
|
|||
priv->shift = pdata->addr_shift;
|
||||
if (pdata->bus_width == 16)
|
||||
priv->a = access_via_16bit;
|
||||
if (((pdata->bus_width == 0) || (pdata->bus_width == 32)) &&
|
||||
(pdata->word_aligned_short_writes))
|
||||
priv->a = access_via_32bit_aligned_short_writes;
|
||||
priv->config_setup = pdata->config_setup;
|
||||
priv->control_setup = pdata->control_setup;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@ struct smc91c111_pdata {
|
|||
int qemu_fixup;
|
||||
int addr_shift;
|
||||
int bus_width;
|
||||
bool word_aligned_short_writes;
|
||||
int config_setup;
|
||||
int control_setup;
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue