ARM mxs: ssp move to common register layout
This patch moves the register defines and bit definitions into one include file. As the defines are common for ssp and mci devices they can be shared. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Michael Grzeschik
Sascha Hauer
parent
650e2daa9f
commit
a90c32c861
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/*
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* Freescale MXS SSP
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*
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* Copyright (C) 2013 Michael Grzeschik <mgr@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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*/
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#ifndef __SSP_H__
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#define __SSP_H__
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#ifdef CONFIG_ARCH_IMX23
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# define HW_SSP_CTRL0 0x000
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# define HW_SSP_CMD0 0x010
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# define HW_SSP_CMD1 0x020
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# define HW_SSP_COMPREF 0x030
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# define HW_SSP_COMPMASK 0x040
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# define HW_SSP_TIMING 0x050
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# define HW_SSP_CTRL1 0x060
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# define HW_SSP_DATA 0x070
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# define HW_SSP_SDRESP0 0x080
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# define HW_SSP_SDRESP1 0x090
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# define HW_SSP_SDRESP2 0x0A0
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# define HW_SSP_SDRESP3 0x0B0
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# define HW_SSP_STATUS 0x0C0
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# define HW_SSP_DEBUG 0x100
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# define HW_SSP_VERSION 0x110
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#endif
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#ifdef CONFIG_ARCH_IMX28
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# define HW_SSP_CTRL0 0x000
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# define HW_SSP_CMD0 0x010
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# define HW_SSP_CMD1 0x020
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# define HW_SSP_XFER_COUNT 0x030
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# define HW_SSP_BLOCK_SIZE 0x040
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# define HW_SSP_COMPREF 0x050
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# define HW_SSP_COMPMASK 0x060
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# define HW_SSP_TIMING 0x070
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# define HW_SSP_CTRL1 0x080
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# define HW_SSP_DATA 0x090
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# define HW_SSP_SDRESP0 0x0A0
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# define HW_SSP_SDRESP1 0x0B0
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# define HW_SSP_SDRESP2 0x0C0
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# define HW_SSP_SDRESP3 0x0D0
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# define HW_SSP_DDR_CTRL 0x0E0
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# define HW_SSP_DLL_CTRL 0x0F0
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# define HW_SSP_STATUS 0x100
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# define HW_SSP_DLL_STS 0x110
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# define HW_SSP_DEBUG 0x120
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# define HW_SSP_VERSION 0x130
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#endif
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#define SSP_CTRL0_SFTRST (1 << 31)
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#define SSP_CTRL0_CLKGATE (1 << 30)
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#define SSP_CTRL0_RUN (1 << 29)
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#define SSP_CTRL0_LOCK_CS (1 << 27)
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#define SSP_CTRL0_READ (1 << 25)
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#define SSP_CTRL0_IGNORE_CRC (1 << 26)
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#define SSP_CTRL0_DATA_XFER (1 << 24)
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#define SSP_CTRL0_BUS_WIDTH(x) (((x) & 0x3) << 22)
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#define SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
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#define SSP_CTRL0_WAIT_FOR_CMD (1 << 20)
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#define SSP_CTRL0_LONG_RESP (1 << 19)
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#define SSP_CTRL0_GET_RESP (1 << 17)
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#define SSP_CTRL0_ENABLE (1 << 16)
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#define SSP_CMD0_SLOW_CLK (1 << 22)
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#define SSP_CMD0_CONT_CLK (1 << 21)
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#define SSP_CMD0_APPEND_8CYC (1 << 20)
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#ifdef CONFIG_ARCH_IMX23
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# define SSP_CTRL0_XFER_COUNT(x) ((x) & 0xffff)
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# define SSP_CMD0_BLOCK_SIZE(x) (((x) & 0xf) << 16)
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# define SSP_CMD0_BLOCK_COUNT(x) (((x) & 0xff) << 8)
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#endif
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#define SSP_CMD0_CMD(x) ((x) & 0xff)
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#ifdef CONFIG_ARCH_IMX28
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# define SSP_BLOCK_SIZE(x) ((x) & 0xf)
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# define SSP_BLOCK_COUNT(x) (((x) & 0xffffff) << 4)
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#endif
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/* bit definition for register HW_SSP_TIMING */
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#define SSP_TIMING_TIMEOUT_MASK (0xffff0000)
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#define SSP_TIMING_TIMEOUT(x) ((x) << 16)
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#define SSP_TIMING_CLOCK_DIVIDE(x) (((x) & 0xff) << 8)
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#define SSP_TIMING_CLOCK_RATE(x) ((x) & 0xff)
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/* bit definition for register HW_SSP_CTRL1 */
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#define SSP_CTRL1_POLARITY (1 << 9)
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#define SSP_CTRL1_PHASE (1 << 10)
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#define SSP_CTRL1_WORD_LENGTH(x) (((x) & 0xf) << 4)
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#define SSP_CTRL1_SSP_MODE(x) ((x) & 0xf)
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/* bit definition for register HW_SSP_STATUS */
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# define SSP_STATUS_PRESENT (1 << 31)
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# define SSP_STATUS_SD_PRESENT (1 << 29)
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# define SSP_STATUS_CARD_DETECT (1 << 28)
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# define SSP_STATUS_RESP_CRC_ERR (1 << 16)
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# define SSP_STATUS_RESP_ERR (1 << 15)
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# define SSP_STATUS_RESP_TIMEOUT (1 << 14)
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# define SSP_STATUS_DATA_CRC_ERR (1 << 13)
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# define SSP_STATUS_TIMEOUT (1 << 12)
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# define SSP_STATUS_FIFO_OVRFLW (1 << 9)
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# define SSP_STATUS_FIFO_FULL (1 << 8)
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# define SSP_STATUS_FIFO_EMPTY (1 << 5)
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# define SSP_STATUS_FIFO_UNDRFLW (1 << 4)
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# define SSP_STATUS_CMD_BUSY (1 << 3)
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# define SSP_STATUS_DATA_BUSY (1 << 2)
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# define SSP_STATUS_BUSY (1 << 0)
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# define SSP_STATUS_ERROR (SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW | \
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SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR | \
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SSP_STATUS_RESP_TIMEOUT | SSP_STATUS_DATA_CRC_ERR | SSP_STATUS_TIMEOUT)
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#endif /* __SSP_H__ */
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@ -40,127 +40,11 @@
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#include <mach/imx-regs.h>
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#include <mach/mci.h>
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#include <mach/clock.h>
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#include <mach/ssp.h>
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#define CLOCKRATE_MIN (1 * 1000 * 1000)
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#define CLOCKRATE_MAX (480 * 1000 * 1000)
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#define HW_SSP_CTRL0 0x000
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# define SSP_CTRL0_SFTRST (1 << 31)
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# define SSP_CTRL0_CLKGATE (1 << 30)
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# define SSP_CTRL0_RUN (1 << 29)
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# define SSP_CTRL0_LOCK_CS (1 << 27)
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# define SSP_CTRL0_READ (1 << 25)
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# define SSP_CTRL0_IGNORE_CRC (1 << 26)
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# define SSP_CTRL0_DATA_XFER (1 << 24)
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# define SSP_CTRL0_BUS_WIDTH(x) (((x) & 0x3) << 22)
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# define SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
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# define SSP_CTRL0_LONG_RESP (1 << 19)
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# define SSP_CTRL0_GET_RESP (1 << 17)
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# define SSP_CTRL0_ENABLE (1 << 16)
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#ifdef CONFIG_ARCH_IMX23
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# define SSP_CTRL0_XFER_COUNT(x) ((x) & 0xffff)
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#endif
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#define HW_SSP_CMD0 0x010
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# define SSP_CMD0_SLOW_CLK (1 << 22)
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# define SSP_CMD0_CONT_CLK (1 << 21)
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# define SSP_CMD0_APPEND_8CYC (1 << 20)
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#ifdef CONFIG_ARCH_IMX23
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# define SSP_CMD0_BLOCK_SIZE(x) (((x) & 0xf) << 16)
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# define SSP_CMD0_BLOCK_COUNT(x) (((x) & 0xff) << 8)
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#endif
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# define SSP_CMD0_CMD(x) ((x) & 0xff)
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#define HW_SSP_CMD1 0x020
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#ifdef CONFIG_ARCH_IMX23
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# define HW_SSP_COMPREF 0x030
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# define HW_SSP_COMPMASK 0x040
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# define HW_SSP_TIMING 0x050
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# define HW_SSP_CTRL1 0x060
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# define HW_SSP_DATA 0x070
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#endif
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#ifdef CONFIG_ARCH_IMX28
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# define HW_SSP_XFER_COUNT 0x30
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# define HW_SSP_BLOCK_SIZE 0x40
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# define SSP_BLOCK_SIZE(x) ((x) & 0xf)
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# define SSP_BLOCK_COUNT(x) (((x) & 0xffffff) << 4)
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# define HW_SSP_COMPREF 0x050
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# define HW_SSP_COMPMASK 0x060
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# define HW_SSP_TIMING 0x070
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# define HW_SSP_CTRL1 0x080
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# define HW_SSP_DATA 0x090
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#endif
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/* bit definition for register HW_SSP_TIMING */
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# define SSP_TIMING_TIMEOUT_MASK (0xffff0000)
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# define SSP_TIMING_TIMEOUT(x) ((x) << 16)
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# define SSP_TIMING_CLOCK_DIVIDE(x) (((x) & 0xff) << 8)
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# define SSP_TIMING_CLOCK_RATE(x) ((x) & 0xff)
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/* bit definition for register HW_SSP_CTRL1 */
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# define SSP_CTRL1_POLARITY (1 << 9)
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# define SSP_CTRL1_WORD_LENGTH(x) (((x) & 0xf) << 4)
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# define SSP_CTRL1_SSP_MODE(x) ((x) & 0xf)
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#ifdef CONFIG_ARCH_IMX23
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# define HW_SSP_SDRESP0 0x080
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# define HW_SSP_SDRESP1 0x090
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# define HW_SSP_SDRESP2 0x0A0
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# define HW_SSP_SDRESP3 0x0B0
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#endif
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#ifdef CONFIG_ARCH_IMX28
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# define HW_SSP_SDRESP0 0x0A0
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# define HW_SSP_SDRESP1 0x0B0
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# define HW_SSP_SDRESP2 0x0C0
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# define HW_SSP_SDRESP3 0x0D0
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#endif
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#ifdef CONFIG_ARCH_IMX28
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# define HW_SSP_DDR_CTRL 0x0E0
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# define HW_SSP_DLL_CTRL 0x0F0
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#endif
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#ifdef CONFIG_ARCH_IMX23
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# define HW_SSP_STATUS 0x0C0
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#endif
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#ifdef CONFIG_ARCH_IMX28
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# define HW_SSP_STATUS 0x100
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#endif
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/* bit definition for register HW_SSP_STATUS */
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# define SSP_STATUS_PRESENT (1 << 31)
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# define SSP_STATUS_SD_PRESENT (1 << 29)
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# define SSP_STATUS_CARD_DETECT (1 << 28)
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# define SSP_STATUS_RESP_CRC_ERR (1 << 16)
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# define SSP_STATUS_RESP_ERR (1 << 15)
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# define SSP_STATUS_RESP_TIMEOUT (1 << 14)
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# define SSP_STATUS_DATA_CRC_ERR (1 << 13)
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# define SSP_STATUS_TIMEOUT (1 << 12)
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# define SSP_STATUS_FIFO_OVRFLW (1 << 9)
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# define SSP_STATUS_FIFO_FULL (1 << 8)
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# define SSP_STATUS_FIFO_EMPTY (1 << 5)
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# define SSP_STATUS_FIFO_UNDRFLW (1 << 4)
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# define SSP_STATUS_CMD_BUSY (1 << 3)
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# define SSP_STATUS_DATA_BUSY (1 << 2)
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# define SSP_STATUS_BUSY (1 << 0)
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# define SSP_STATUS_ERROR (SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW | \
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SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR | \
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SSP_STATUS_RESP_TIMEOUT | SSP_STATUS_DATA_CRC_ERR | SSP_STATUS_TIMEOUT)
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#ifdef CONFIG_ARCH_IMX28
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# define HW_SSP_DLL_STS 0x110
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#endif
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#ifdef CONFIG_ARCH_IMX23
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# define HW_SSP_DEBUG 0x100
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# define HW_SSP_VERSION 0x110
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#endif
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#ifdef CONFIG_ARCH_IMX28
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# define HW_SSP_DEBUG 0x120
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# define HW_SSP_VERSION 0x130
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#endif
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struct mxs_mci_host {
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struct mci_host host;
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void __iomem *regs;
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