Fix genphy_restart_aneg() for Micrel's ksz9031.
Commit da89ee8f2e
("Center FLP timing at 16ms") breaks
genphy_restart_aneg() for Micrel's ksz9031. According to the
datasheet, the ksz9031 requires a wait of 1ms after clearing
the PDOWN bit and before read/write access to any PHY registers.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -561,7 +561,7 @@ int phy_wait_aneg_done(struct phy_device *phydev)
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*/
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*/
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int genphy_restart_aneg(struct phy_device *phydev)
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int genphy_restart_aneg(struct phy_device *phydev)
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{
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{
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int ctl;
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int ctl, pdown;
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ctl = phy_read(phydev, MII_BMCR);
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ctl = phy_read(phydev, MII_BMCR);
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@ -574,6 +574,7 @@ int genphy_restart_aneg(struct phy_device *phydev)
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ctl &= ~(BMCR_ISOLATE);
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ctl &= ~(BMCR_ISOLATE);
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/* Clear powerdown bit which eventually is set on some phys */
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/* Clear powerdown bit which eventually is set on some phys */
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pdown = ctl & BMCR_PDOWN;
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ctl &= ~BMCR_PDOWN;
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ctl &= ~BMCR_PDOWN;
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ctl = phy_write(phydev, MII_BMCR, ctl);
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ctl = phy_write(phydev, MII_BMCR, ctl);
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@ -581,6 +582,12 @@ int genphy_restart_aneg(struct phy_device *phydev)
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if (ctl < 0)
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if (ctl < 0)
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return ctl;
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return ctl;
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/* Micrel's ksz9031 (and perhaps others?): Changing the PDOWN bit
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* from '1' to '0' generates an internal reset. Must wait a minimum
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* of 1ms before read/write access to the PHY registers. */
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if (pdown)
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mdelay(1);
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return 0;
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return 0;
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}
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}
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