Add support for Baltos systems
OnRISC Baltos devices are based on a am335x SoC and can be booted either from MMC or NAND. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Yegor Yefremov
Sascha Hauer
parent
c9dbd886ef
commit
aadf261cd6
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@ -137,4 +137,5 @@ obj-$(CONFIG_MACH_VIRT2REAL) += virt2real/
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obj-$(CONFIG_MACH_ZEDBOARD) += avnet-zedboard/
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obj-$(CONFIG_MACH_ZYLONITE) += zylonite/
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obj-$(CONFIG_MACH_VARISCITE_MX6) += variscite-mx6/
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obj-$(CONFIG_MACH_VSCOM_BALTOS) += vscom-baltos/
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obj-$(CONFIG_MACH_QEMU_VIRT64) += qemu-virt64/
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@ -0,0 +1,2 @@
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lwl-y += lowlevel.o
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obj-y += board.o
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@ -0,0 +1,132 @@
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/*
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* (C) Copyright 2008
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* Texas Instruments, <www.ti.com>
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* Raghavendra KH <r-khandenahally@ti.com>
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*
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* Copyright (C) 2012 Jan Luebbe <j.luebbe@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/**
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* @file
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* @brief OnRISC Baltos Specific Board Initialization routines
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*/
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#include <common.h>
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#include <init.h>
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#include <driver.h>
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#include <envfs.h>
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#include <environment.h>
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#include <globalvar.h>
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#include <linux/sizes.h>
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#include <net.h>
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#include <envfs.h>
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#include <bootsource.h>
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#include <asm/armlinux.h>
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#include <generated/mach-types.h>
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#include <mach/am33xx-generic.h>
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#include <mach/am33xx-silicon.h>
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#include <mach/sys_info.h>
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#include <mach/syslib.h>
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#include <mach/gpmc.h>
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#include <linux/err.h>
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#include <mach/bbu.h>
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#include <libfile.h>
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static struct omap_barebox_part baltos_barebox_part = {
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.nand_offset = SZ_512K,
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.nand_size = 0x1e0000,
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};
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struct bsp_vs_hwparam {
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uint32_t Magic;
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uint32_t HwRev;
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uint32_t SerialNumber;
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char PrdDate[11];
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uint16_t SystemId;
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uint8_t MAC1[6];
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uint8_t MAC2[6];
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uint8_t MAC3[6];
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} __attribute__ ((packed));
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static int baltos_read_eeprom(void)
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{
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struct bsp_vs_hwparam hw_param;
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size_t size;
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char *buf, var_buf[32];
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int rc;
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unsigned char mac_addr[6];
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rc = read_file_2("/dev/eeprom0",
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&size,
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(void *)&buf,
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sizeof(hw_param));
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if (rc && rc != -EFBIG)
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return rc;
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memcpy(&hw_param, buf, sizeof(hw_param));
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free(buf);
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if (hw_param.Magic == 0xDEADBEEF) {
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/* setup MAC1 */
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mac_addr[0] = hw_param.MAC1[0];
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mac_addr[1] = hw_param.MAC1[1];
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mac_addr[2] = hw_param.MAC1[2];
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mac_addr[3] = hw_param.MAC1[3];
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mac_addr[4] = hw_param.MAC1[4];
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mac_addr[5] = hw_param.MAC1[5];
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eth_register_ethaddr(0, mac_addr);
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/* setup MAC2 */
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mac_addr[0] = hw_param.MAC2[0];
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mac_addr[1] = hw_param.MAC2[1];
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mac_addr[2] = hw_param.MAC2[2];
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mac_addr[3] = hw_param.MAC2[3];
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mac_addr[4] = hw_param.MAC2[4];
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mac_addr[5] = hw_param.MAC2[5];
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eth_register_ethaddr(1, mac_addr);
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} else {
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printf("Baltos: incorrect magic number (0x%x) "
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"in EEPROM\n",
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hw_param.Magic);
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hw_param.SystemId = 0;
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}
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sprintf(var_buf, "%d", hw_param.SystemId);
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globalvar_add_simple("board.id", var_buf);
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return 0;
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}
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environment_initcall(baltos_read_eeprom);
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static int baltos_devices_init(void)
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{
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if (!of_machine_is_compatible("vscom,onrisc"))
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return 0;
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globalvar_add_simple("board.variant", "baltos");
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if (bootsource_get() == BOOTSOURCE_MMC)
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omap_set_bootmmc_devname("mmc0");
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omap_set_barebox_part(&baltos_barebox_part);
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if (IS_ENABLED(CONFIG_SHELL_NONE))
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return am33xx_of_register_bootdevice();
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return 0;
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}
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coredevice_initcall(baltos_devices_init);
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@ -0,0 +1,134 @@
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#include <common.h>
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#include <init.h>
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#include <linux/sizes.h>
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#include <io.h>
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#include <linux/string.h>
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#include <debug_ll.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/barebox-arm.h>
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#include <mach/am33xx-silicon.h>
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#include <mach/am33xx-clock.h>
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#include <mach/generic.h>
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#include <mach/sdrc.h>
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#include <mach/sys_info.h>
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#include <mach/syslib.h>
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#include <mach/am33xx-mux.h>
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#include <mach/am33xx-generic.h>
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#include <mach/wdt.h>
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static const struct am33xx_ddr_data ddr3_data = {
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.rd_slave_ratio0 = 0x38,
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.wr_dqs_slave_ratio0 = 0x44,
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.fifo_we_slave_ratio0 = 0x94,
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.wr_slave_ratio0 = 0x7D,
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.use_rank0_delay = 0x01,
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.dll_lock_diff0 = 0x0,
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};
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static const struct am33xx_cmd_control ddr3_cmd_ctrl = {
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.slave_ratio0 = 0x80,
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.dll_lock_diff0 = 0x1,
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.invert_clkout0 = 0x0,
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.slave_ratio1 = 0x80,
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.dll_lock_diff1 = 0x1,
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.invert_clkout1 = 0x0,
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.slave_ratio2 = 0x80,
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.dll_lock_diff2 = 0x1,
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.invert_clkout2 = 0x0,
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};
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static const struct am33xx_emif_regs ddr3_regs = {
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.emif_read_latency = 0x100007,
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.emif_tim1 = 0x0AAAD4DB,
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.emif_tim2 = 0x266B7FDA,
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.emif_tim3 = 0x501F867F,
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.zq_config = 0x50074BE4,
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.sdram_config = 0x61C05332,
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.sdram_config2 = 0x0,
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.sdram_ref_ctrl = 0xC30,
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};
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static const struct am33xx_ddr_data ddr3_data_256mb = {
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.rd_slave_ratio0 = 0x36,
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.wr_dqs_slave_ratio0 = 0x38,
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.fifo_we_slave_ratio0 = 0x99,
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.wr_slave_ratio0 = 0x73,
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};
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static const struct am33xx_emif_regs ddr3_regs_256mb = {
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.emif_read_latency = 0x7,
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.emif_tim1 = 0x0AAAD4DB,
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.emif_tim2 = 0x26437FDA,
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.emif_tim3 = 0x501F83FF,
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.sdram_config = 0x61C052B2,
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.zq_config = 0x50074BE4,
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.sdram_ref_ctrl = 0x00000C30,
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};
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extern char __dtb_am335x_baltos_minimal_start[];
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/**
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* @brief The basic entry point for board initialization.
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*
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* This is called as part of machine init (after arch init).
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* This is again called with stack in SRAM, so not too many
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* constructs possible here.
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*
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* @return void
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*/
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static noinline int baltos_sram_init(void)
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{
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uint32_t sdram_size;
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void *fdt;
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fdt = __dtb_am335x_baltos_minimal_start;
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/* WDT1 is already running when the bootloader gets control
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* Disable it to avoid "random" resets
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*/
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__raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
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while (__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
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__raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
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while (__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
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/* Setup the PLLs and the clocks for the peripherals */
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am33xx_pll_init(MPUPLL_M_500, DDRPLL_M_400);
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am335x_sdram_init(0x18B, &ddr3_cmd_ctrl, &ddr3_regs, &ddr3_data);
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sdram_size = get_ram_size((void *)0x80000000, (1024 << 20));
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if (sdram_size == SZ_256M)
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am335x_sdram_init(0x18B, &ddr3_cmd_ctrl, &ddr3_regs_256mb,
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&ddr3_data_256mb);
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am33xx_uart_soft_reset((void *)AM33XX_UART0_BASE);
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am33xx_enable_uart0_pin_mux();
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omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE);
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putc_ll('>');
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am335x_barebox_entry(fdt);
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}
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ENTRY_FUNCTION(start_am33xx_baltos_sram, bootinfo, r1, r2)
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{
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am33xx_save_bootinfo((void *)bootinfo);
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/*
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* Setup C environment, the board init code uses global variables.
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* Stackpointer has already been initialized by the ROM code.
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*/
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relocate_to_current_adr();
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setup_c();
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baltos_sram_init();
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}
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ENTRY_FUNCTION(start_am33xx_baltos_sdram, r0, r1, r2)
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{
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void *fdt;
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fdt = __dtb_am335x_baltos_minimal_start;
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fdt -= get_runtime_offset();
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am335x_barebox_entry(fdt);
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}
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@ -76,5 +76,6 @@ pbl-dtb-$(CONFIG_MACH_TX6X) += imx6q-tx6q.dtb.o
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pbl-dtb-$(CONFIG_MACH_UDOO) += imx6q-udoo.dtb.o
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pbl-dtb-$(CONFIG_MACH_USI_TOPKICK) += kirkwood-topkick-bb.dtb.o
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pbl-dtb-$(CONFIG_MACH_VARISCITE_MX6) += imx6q-var-custom.dtb.o
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pbl-dtb-$(CONFIG_MACH_VSCOM_BALTOS) += am335x-baltos-minimal.dtb.o
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clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.lzo
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@ -0,0 +1,439 @@
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/*
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* VScom OnRISC
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* http://www.vscom.de
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*/
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/dts-v1/;
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#include "am33xx.dtsi"
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#include <dt-bindings/pwm/pwm.h>
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/ {
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model = "OnRISC Baltos";
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compatible = "vscom,onrisc", "ti,am33xx";
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chosen {
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linux,stdout-path = &uart0;
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};
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cpus {
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cpu@0 {
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cpu0-supply = <&vdd1_reg>;
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};
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};
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vbat: fixedregulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "vbat";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-boot-on;
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};
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};
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&am33xx_pinmux {
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mmc1_pins: pinmux_mmc1_pins {
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pinctrl-single,pins = <
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0xf0 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat3.mmc0_dat3 */
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0xf4 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat2.mmc0_dat2 */
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0xf8 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat1.mmc0_dat1 */
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0xfc (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat0.mmc0_dat0 */
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0x100 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_clk.mmc0_clk */
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0x104 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_cmd.mmc0_cmd */
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>;
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};
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i2c1_pins: pinmux_i2c1_pins {
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pinctrl-single,pins = <
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0x158 0x2a /* spi0_d1.i2c1_sda_mux3, INPUT | MODE2 */
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0x15c 0x2a /* spi0_cs0.i2c1_scl_mux3, INPUT | MODE2 */
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>;
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};
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tps65910_pins: pinmux_tps65910_pins {
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pinctrl-single,pins = <
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0x078 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28] */
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>;
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};
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tca6416_pins: pinmux_tca6416_pins {
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pinctrl-single,pins = <
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AM33XX_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */
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>;
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};
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uart0_pins: pinmux_uart0_pins {
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pinctrl-single,pins = <
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0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
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0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
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>;
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};
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cpsw_default: cpsw_default {
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pinctrl-single,pins = <
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/* Slave 1 */
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0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
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0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen */
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0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
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0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
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0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
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0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
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0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */
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/* Slave 2 */
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0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
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0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
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0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
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0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
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0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
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0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
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0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
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0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
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0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
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0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
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0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
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0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
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>;
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};
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cpsw_sleep: cpsw_sleep {
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pinctrl-single,pins = <
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/* Slave 1 reset value */
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0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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|
||||
/* Slave 2 reset value*/
|
||||
0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_default: davinci_mdio_default {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO */
|
||||
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
|
||||
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_sleep: davinci_mdio_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO reset value */
|
||||
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
nandflash_pins_s0: nandflash_pins_s0 {
|
||||
pinctrl-single,pins = <
|
||||
0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
|
||||
0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
|
||||
0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
|
||||
0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
|
||||
0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
|
||||
0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
|
||||
0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
|
||||
0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
|
||||
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
|
||||
0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
|
||||
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
|
||||
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
|
||||
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
|
||||
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
|
||||
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&elm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nandflash_pins_s0>;
|
||||
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
|
||||
status = "okay";
|
||||
|
||||
nand@0,0 {
|
||||
reg = <0 0 0>; /* CS0, offset 0 */
|
||||
nand-bus-width = <8>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
ti,nand-xfer-type = "polled";
|
||||
|
||||
gpmc,device-nand = "true";
|
||||
gpmc,device-width = <1>;
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <44>;
|
||||
gpmc,cs-wr-off-ns = <44>;
|
||||
gpmc,adv-on-ns = <6>;
|
||||
gpmc,adv-rd-off-ns = <34>;
|
||||
gpmc,adv-wr-off-ns = <44>;
|
||||
gpmc,we-on-ns = <0>;
|
||||
gpmc,we-off-ns = <40>;
|
||||
gpmc,oe-on-ns = <0>;
|
||||
gpmc,oe-off-ns = <54>;
|
||||
gpmc,access-ns = <64>;
|
||||
gpmc,rd-cycle-ns = <82>;
|
||||
gpmc,wr-cycle-ns = <82>;
|
||||
gpmc,wait-on-read = "true";
|
||||
gpmc,wait-on-write = "true";
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
elm_id = <&elm>;
|
||||
|
||||
boot@0 {
|
||||
label = "SPL";
|
||||
reg = <0x0 0x20000>;
|
||||
};
|
||||
boot@20000{
|
||||
label = "SPL.backup1";
|
||||
reg = <0x20000 0x20000>;
|
||||
};
|
||||
boot@40000 {
|
||||
label = "SPL.backup2";
|
||||
reg = <0x40000 0x20000>;
|
||||
};
|
||||
boot@60000 {
|
||||
label = "SPL.backup3";
|
||||
reg = <0x60000 0x20000>;
|
||||
};
|
||||
boot@80000 {
|
||||
label = "u-boot";
|
||||
reg = <0x80000 0x1e0000>;
|
||||
};
|
||||
boot@260000 {
|
||||
label = "UBI";
|
||||
reg = <0x260000 0xfda0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <1000>;
|
||||
|
||||
tps: tps@2d {
|
||||
reg = <0x2d>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <28 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&tps65910_pins>;
|
||||
};
|
||||
|
||||
at24@50 {
|
||||
compatible = "at24,24c02";
|
||||
pagesize = <8>;
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
tca6416: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <20 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&tca6416_pins>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_ctrl_mod {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&cppi41dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/include/ "tps65910.dtsi"
|
||||
|
||||
&tps {
|
||||
vcc1-supply = <&vbat>;
|
||||
vcc2-supply = <&vbat>;
|
||||
vcc3-supply = <&vbat>;
|
||||
vcc4-supply = <&vbat>;
|
||||
vcc5-supply = <&vbat>;
|
||||
vcc6-supply = <&vbat>;
|
||||
vcc7-supply = <&vbat>;
|
||||
vccio-supply = <&vbat>;
|
||||
|
||||
ti,en-ck32k-xtal = <1>;
|
||||
|
||||
regulators {
|
||||
vrtc_reg: regulator@0 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vio_reg: regulator@1 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd1_reg: regulator@2 {
|
||||
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <912500>;
|
||||
regulator-max-microvolt = <1312500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd2_reg: regulator@3 {
|
||||
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <912500>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd3_reg: regulator@4 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdig1_reg: regulator@5 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdig2_reg: regulator@6 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vpll_reg: regulator@7 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdac_reg: regulator@8 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux1_reg: regulator@9 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux2_reg: regulator@10 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux33_reg: regulator@11 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vmmc_reg: regulator@12 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mac {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cpsw_default>;
|
||||
pinctrl-1 = <&cpsw_sleep>;
|
||||
dual_emac = <1>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&davinci_mdio_default>;
|
||||
pinctrl-1 = <&davinci_mdio_sleep>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <0>;
|
||||
phy-mode = "rmii";
|
||||
dual_emac_res_vlan = <1>;
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
phy_id = <&davinci_mdio>, <7>;
|
||||
phy-mode = "rgmii-txid";
|
||||
dual_emac_res_vlan = <2>;
|
||||
};
|
||||
|
||||
&phy_sel {
|
||||
rmii-clock-ext = <1>;
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins>;
|
||||
vmmc-supply = <&vmmc_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
ti,no-reset-on-init;
|
||||
};
|
||||
|
|
@ -184,6 +184,13 @@ config MACH_PHYTEC_SOM_AM335X
|
|||
select ARCH_AM33XX
|
||||
help
|
||||
Say Y here if you are using a am335x based Phytecs SOM
|
||||
|
||||
config MACH_VSCOM_BALTOS
|
||||
bool "VScom Baltos Devices"
|
||||
select ARCH_AM33XX
|
||||
help
|
||||
Say Y here if you are using a am335x based VScom Baltos devices
|
||||
|
||||
endif
|
||||
|
||||
choice
|
||||
|
|
|
|||
|
|
@ -135,6 +135,14 @@ pblx-$(CONFIG_MACH_BEAGLEBONE) += start_am33xx_beaglebone_sram
|
|||
FILE_barebox-am33xx-beaglebone-mlo.img = start_am33xx_beaglebone_sram.pblx.mlo
|
||||
am33xx-mlo-$(CONFIG_MACH_BEAGLEBONE) += barebox-am33xx-beaglebone-mlo.img
|
||||
|
||||
pblx-$(CONFIG_MACH_VSCOM_BALTOS) += start_am33xx_baltos_sdram
|
||||
FILE_barebox-am33xx-baltos.img = start_am33xx_baltos_sdram.pblx
|
||||
am33xx-barebox-$(CONFIG_MACH_VSCOM_BALTOS) += barebox-am33xx-baltos.img
|
||||
|
||||
pblx-$(CONFIG_MACH_VSCOM_BALTOS) += start_am33xx_baltos_sram
|
||||
FILE_barebox-am33xx-baltos-mlo.img = start_am33xx_baltos_sram.pblx.mlo
|
||||
am33xx-mlo-$(CONFIG_MACH_VSCOM_BALTOS) += barebox-am33xx-baltos-mlo.img
|
||||
|
||||
ifdef CONFIG_OMAP_BUILD_IFT
|
||||
image-y += $(am33xx-mlo-y)
|
||||
else
|
||||
|
|
|
|||
Loading…
Reference in New Issue