ARM i.MX31: give register base addresses a proper MX31_ prefix
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
638e059aba
commit
ad09b59f8b
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@ -46,13 +46,12 @@ reset:
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common_reset r0
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writel(IPU_CONF_DI_EN, IPU_CONF)
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writel(0x074B0BF5, IMX_CCM_BASE + CCM_CCMR)
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writel(0x074B0BF5, MX31_CCM_BASE_ADDR + CCM_CCMR)
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DELAY 0x40000
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writel(0x074B0BF5 | CCMR_MPE, IMX_CCM_BASE + CCM_CCMR)
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writel((0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS, IMX_CCM_BASE + CCM_CCMR)
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writel(0x074B0BF5 | CCMR_MPE, MX31_CCM_BASE_ADDR + CCM_CCMR)
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writel((0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS, MX31_CCM_BASE_ADDR + CCM_CCMR)
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writel(PDR0_CSI_PODF(0xff1) | \
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PDR0_PER_PODF(7) | \
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@ -61,10 +60,10 @@ reset:
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PDR0_IPG_PODF(1) | \
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PDR0_MAX_PODF(3) | \
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PDR0_MCU_PODF(0), \
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IMX_CCM_BASE + CCM_PDR0)
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MX31_CCM_BASE_ADDR + CCM_PDR0)
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writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), IMX_CCM_BASE + CCM_MPCTL)
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writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | IMX_PLL_MFN(1), IMX_CCM_BASE + CCM_SPCTL)
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writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), MX31_CCM_BASE_ADDR + CCM_MPCTL)
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writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR + CCM_SPCTL)
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/* Configure IOMUXC
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* Clears 0x43fa_c26c - 0x43fa_c2dc with 0, except 0x43fa_c278 (untouched), 0x43fa_c27c (set to 0x1000) and 0x43fa_c280 (untouched)
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@ -100,15 +99,15 @@ clear_iomux:
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writel(0x00000004, ESDMISC)
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writel(0x006ac73a, ESDCFG0)
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writel(0x90100000 | ROWS0, ESDCTL0)
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writel(0x12344321, IMX_SDRAM_CS0 + 0xf00)
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writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00)
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writel(0xa0100000 | ROWS0, ESDCTL0)
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writel(0x12344321, IMX_SDRAM_CS0)
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writel(0x12344321, IMX_SDRAM_CS0)
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writel(0x12344321, MX31_CSD0_BASE_ADDR)
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writel(0x12344321, MX31_CSD0_BASE_ADDR)
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writel(0xb0100000 | ROWS0, ESDCTL0)
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writeb(0xda, IMX_SDRAM_CS0 + 0x33)
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writeb(0xff, IMX_SDRAM_CS0 + 0x01000000)
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writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33)
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writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000)
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writel(0x80226080 | ROWS0, ESDCTL0)
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writel(0xDEADBEEF, IMX_SDRAM_CS0)
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writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR)
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writel(0x0000000c, ESDMISC)
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#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
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@ -119,23 +118,23 @@ clear_iomux:
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#endif
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writel(0x006ac73a, ESDCFG1)
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writel(0x90100000 | ROWS1, ESDCTL1)
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writel(0x12344321, IMX_SDRAM_CS1 + 0xf00)
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writel(0x12344321, MX31_CSD1_BASE_ADDR + 0xf00)
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writel(0xa0100000 | ROWS1, ESDCTL1)
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writel(0x12344321, IMX_SDRAM_CS1)
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writel(0x12344321, IMX_SDRAM_CS1)
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writel(0x12344321, MX31_CSD1_BASE_ADDR)
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writel(0x12344321, MX31_CSD1_BASE_ADDR)
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writel(0xb0100000 | ROWS1, ESDCTL1)
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writeb(0xda, IMX_SDRAM_CS1 + 0x33)
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writeb(0xff, IMX_SDRAM_CS1 + 0x01000000)
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writeb(0xda, MX31_CSD1_BASE_ADDR + 0x33)
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writeb(0xff, MX31_CSD1_BASE_ADDR + 0x01000000)
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writel(0x80226080 | ROWS1, ESDCTL1)
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writel(0xDEADBEEF, IMX_SDRAM_CS1)
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writel(0xDEADBEEF, MX31_CSD1_BASE_ADDR)
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writel(0x0000000c, ESDMISC)
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#endif
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#ifdef CONFIG_NAND_IMX_BOOT
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ldr sp, =0x80f00000 /* Setup a temporary stack in SDRAM */
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ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */
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ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */
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ldr r0, =MX31_NFC_BASE_ADDR /* start of NFC SRAM */
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ldr r2, =MX31_NFC_BASE_ADDR + 0x1000 /* end of NFC SRAM */
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/* skip NAND boot if not running from NFC space */
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cmp pc, r0
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@ -66,15 +66,15 @@ static void pcm037_usb_init(void)
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writel(tmp, 0x53f80000);
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/* Host 1 */
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tmp = readl(IMX_OTG_BASE + 0x600);
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tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x600);
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tmp &= ~((3 << 21) | 1);
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tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 11) | (1 << 20);
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writel(tmp, IMX_OTG_BASE + 0x600);
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writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x600);
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tmp = readl(IMX_OTG_BASE + 0x184);
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tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x184);
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tmp &= ~(3 << 30);
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tmp |= 2 << 30;
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writel(tmp, IMX_OTG_BASE + 0x184);
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writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x184);
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imx_iomux_mode(MX31_PIN_USBOTG_DATA0__USBOTG_DATA0);
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imx_iomux_mode(MX31_PIN_USBOTG_DATA1__USBOTG_DATA1);
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@ -90,10 +90,10 @@ static void pcm037_usb_init(void)
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imx_iomux_mode(MX31_PIN_USBOTG_STP__USBOTG_STP);
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mdelay(50);
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ulpi_setup((void *)(IMX_OTG_BASE + 0x170), 1);
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ulpi_setup((void *)(MX31_USB_OTG_BASE_ADDR + 0x170), 1);
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/* Host 2 */
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tmp = readl(IOMUXC_BASE + 0x8);
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tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x8);
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tmp |= 1 << 11;
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writel(tmp, IOMUXC_BASE + 0x8);
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@ -124,31 +124,31 @@ static void pcm037_usb_init(void)
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imx_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
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imx_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
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tmp = readl(IMX_OTG_BASE + 0x600);
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tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x600);
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tmp &= ~((3 << 21) | 1);
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tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20);
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writel(tmp, IMX_OTG_BASE + 0x600);
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writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x600);
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tmp = readl(IMX_OTG_BASE + 0x584);
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tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x584);
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tmp &= ~(3 << 30);
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tmp |= 2 << 30;
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writel(tmp, IMX_OTG_BASE + 0x584);
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writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x584);
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mdelay(50);
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ulpi_setup((void *)(IMX_OTG_BASE + 0x570), 1);
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ulpi_setup((void *)(MX31_USB_OTG_BASE_ADDR + 0x570), 1);
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/* Set to Host mode */
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tmp = readl(IMX_OTG_BASE + 0x1a8);
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writel(tmp | 0x3, IMX_OTG_BASE + 0x1a8);
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tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x1a8);
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writel(tmp | 0x3, MX31_USB_OTG_BASE_ADDR + 0x1a8);
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}
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#endif
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static int pcm037_mem_init(void)
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{
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arm_add_mem_device("ram0", IMX_SDRAM_CS0, SDRAM0 * 1024 * 1024);
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arm_add_mem_device("ram0", MX31_CSD0_BASE_ADDR, SDRAM0 * 1024 * 1024);
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#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
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arm_add_mem_device("ram1", IMX_SDRAM_CS1, SDRAM1 * 1024 * 1024);
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arm_add_mem_device("ram1", MX31_CSD1_BASE_ADDR, SDRAM1 * 1024 * 1024);
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#endif
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return 0;
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@ -185,7 +185,7 @@ static int imx31_devices_init(void)
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* Up to 32MiB NOR type flash, connected to
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* CS line 0, data width is 16 bit
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*/
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add_cfi_flash_device(DEVICE_ID_DYNAMIC, IMX_CS0_BASE, 32 * 1024 * 1024, 0);
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add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX31_CS0_BASE_ADDR, 32 * 1024 * 1024, 0);
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/*
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* Create partitions that should be
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@ -200,7 +200,7 @@ static int imx31_devices_init(void)
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* up to 2MiB static RAM type memory, connected
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* to CS4, data width is 16 bit
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*/
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add_mem_device("sram0", IMX_CS4_BASE, IMX_CS4_RANGE, /* area size */
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add_mem_device("sram0", MX31_CS4_BASE_ADDR, MX31_CS4_SIZE, /* area size */
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IORESOURCE_MEM_WRITEABLE);
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imx31_add_nand(&nand_info);
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@ -209,13 +209,13 @@ static int imx31_devices_init(void)
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* connected to CS line 1 and interrupt line
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* GPIO3, data width is 16 bit
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*/
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add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, IMX_CS1_BASE,
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IMX_CS1_RANGE, IORESOURCE_MEM, NULL);
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add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, MX31_CS1_BASE_ADDR,
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MX31_CS1_SIZE, IORESOURCE_MEM, NULL);
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#ifdef CONFIG_USB
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pcm037_usb_init();
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add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE, NULL);
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add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL);
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add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX31_USB_OTG_BASE_ADDR, NULL);
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add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX31_USB_HS2_BASE_ADDR, NULL);
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#endif
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armlinux_set_bootparams((void *)0x80000100);
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@ -18,13 +18,13 @@
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static int imx31_init(void)
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{
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add_generic_device("imx_iim", 0, NULL, IMX_IIM_BASE, SZ_4K,
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add_generic_device("imx_iim", 0, NULL, MX31_IIM_BASE_ADDR, SZ_4K,
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IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpt", 0, NULL, 0x53f90000, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 0, NULL, 0x53fcc000, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 1, NULL, 0x53fd0000, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 2, NULL, 0x53fa4000, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpt", 0, NULL, MX31_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx-gpio", 0, NULL, MX31_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx-gpio", 1, NULL, MX31_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx-gpio", 2, NULL, MX31_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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return 0;
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}
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@ -2,34 +2,52 @@
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#include <mach/imx-regs.h>
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#include <mach/devices.h>
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#if 0
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static inline struct device_d *imx31_add_spi0(struct spi_imx_master *pdata)
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{
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return imx_add_spi((void *)IMX_SPI1_BASE, 0, pdata);
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return imx_add_spi((void *)MX31_CSPI1_BASE_ADDR, 0, pdata);
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}
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static inline struct device_d *imx31_add_spi1(struct spi_imx_master *pdata)
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{
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return imx_add_spi((void *)IMX_SPI2_BASE, 1, pdata);
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return imx_add_spi((void *)MX31_CSPI2_BASE_ADDR, 1, pdata);
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}
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static inline struct device_d *imx31_add_spi2(struct spi_imx_master *pdata)
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{
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return imx_add_spi((void *)MX31_CSPI3_BASE_ADDR, 2, pdata);
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}
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#endif
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static inline struct device_d *imx31_add_uart0(void)
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{
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return imx_add_uart((void *)IMX_UART1_BASE, 0);
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return imx_add_uart((void *)MX31_UART1_BASE_ADDR, 0);
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}
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static inline struct device_d *imx31_add_uart1(void)
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{
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return imx_add_uart((void *)IMX_UART2_BASE, 1);
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return imx_add_uart((void *)MX31_UART2_BASE_ADDR, 1);
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}
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static inline struct device_d *imx31_add_uart2(void)
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{
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return imx_add_uart((void *)MX31_UART3_BASE_ADDR, 2);
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}
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static inline struct device_d *imx31_add_uart3(void)
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{
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return imx_add_uart((void *)MX31_UART4_BASE_ADDR, 3);
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}
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static inline struct device_d *imx31_add_uart4(void)
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{
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return imx_add_uart((void *)MX31_UART5_BASE_ADDR, 4);
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}
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static inline struct device_d *imx31_add_nand(struct imx_nand_platform_data *pdata)
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{
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return imx_add_nand((void *)0xb8000000, pdata);
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return imx_add_nand((void *)MX31_NFC_BASE_ADDR, pdata);
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}
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static inline struct device_d *imx31_add_fb(struct imx_ipu_fb_platform_data *pdata)
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{
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return imx_add_ipufb((void *)IPU_BASE, pdata);
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return imx_add_ipufb((void *)MX31_IPU_CTRL_BASE_ADDR, pdata);
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}
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@ -19,6 +19,8 @@
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#ifndef __ASM_ARCH_MX31_REGS_H
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#define __ASM_ARCH_MX31_REGS_H
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#include <sizes.h>
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/*
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* sanity check
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*/
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@ -26,72 +28,125 @@
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# error "Please do not include directly. Use imx-regs.h instead."
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#endif
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#define IMX_OTG_BASE 0x43F88000
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#define IMX_UART1_BASE 0x43F90000
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#define IMX_UART2_BASE 0x43F94000
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#define IMX_WDT_BASE 0x53FDC000
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#define IMX_RTC_BASE 0x53FD8000
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#define IMX_TIM1_BASE 0x53F90000
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#define IMX_IIM_BASE 0x5001C000
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#define MX31_AIPS1_BASE_ADDR 0x43f00000
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#define MX31_AIPS1_SIZE SZ_1M
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#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000)
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#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000)
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#define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000)
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#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000)
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#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000)
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#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000)
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#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000)
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#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000)
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#define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
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#define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000)
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#define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200)
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#define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400)
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#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000)
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#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000)
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#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000)
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#define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000)
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#define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000)
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#define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000)
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#define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000)
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#define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000)
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#define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000)
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#define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000)
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#define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000)
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#define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000)
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#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000)
|
||||
|
||||
#define IMX_SDRAM_CS0 0x80000000
|
||||
#define IMX_SDRAM_CS1 0x90000000
|
||||
#define MX31_SPBA0_BASE_ADDR 0x50000000
|
||||
#define MX31_SPBA0_SIZE SZ_1M
|
||||
#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000)
|
||||
#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000)
|
||||
#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000)
|
||||
#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000)
|
||||
#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000)
|
||||
#define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000)
|
||||
#define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000)
|
||||
#define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000)
|
||||
#define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000)
|
||||
#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000)
|
||||
|
||||
/*
|
||||
* Adresses and ranges of the external chip select lines
|
||||
*/
|
||||
#define IMX_CS0_BASE 0xA0000000
|
||||
#define IMX_CS0_RANGE (128 * 1024 * 1024)
|
||||
#define IMX_CS1_BASE 0xA8000000
|
||||
#define IMX_CS1_RANGE (128 * 1024 * 1024)
|
||||
#define IMX_CS2_BASE 0xB0000000
|
||||
#define IMX_CS2_RANGE (32 * 1024 * 1024)
|
||||
#define IMX_CS3_BASE 0xB2000000
|
||||
#define IMX_CS3_RANGE (32 * 1024 * 1024)
|
||||
#define IMX_CS4_BASE 0xB4000000
|
||||
#define IMX_CS4_RANGE (32 * 1024 * 1024)
|
||||
#define IMX_CS5_BASE 0xB6000000
|
||||
#define IMX_CS5_RANGE (32 * 1024 * 1024)
|
||||
#define MX31_AIPS2_BASE_ADDR 0x53f00000
|
||||
#define MX31_AIPS2_SIZE SZ_1M
|
||||
#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000)
|
||||
#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000)
|
||||
#define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000)
|
||||
#define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000)
|
||||
#define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000)
|
||||
#define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000)
|
||||
#define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000)
|
||||
#define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000)
|
||||
#define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000)
|
||||
#define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000)
|
||||
#define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000)
|
||||
#define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000)
|
||||
#define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000)
|
||||
#define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000)
|
||||
#define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000)
|
||||
#define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000)
|
||||
#define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000)
|
||||
#define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000)
|
||||
#define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000)
|
||||
#define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000)
|
||||
#define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000)
|
||||
|
||||
#if 0
|
||||
#define IMX_IO_BASE 0x00200000
|
||||
#define MX31_ROMP_BASE_ADDR 0x60000000
|
||||
#define MX31_ROMP_SIZE SZ_1M
|
||||
|
||||
/*
|
||||
* Register BASEs, based on OFFSETs
|
||||
*/
|
||||
#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
|
||||
#define (0x01000 + IMX_IO_BASE)
|
||||
(0x02000 + IMX_IO_BASE)
|
||||
#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE)
|
||||
(0x04000 + IMX_IO_BASE)
|
||||
#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE)
|
||||
#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE)
|
||||
#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE)
|
||||
#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE)
|
||||
#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE)
|
||||
#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE)
|
||||
#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE)
|
||||
#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE)
|
||||
#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE)
|
||||
#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE)
|
||||
#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE)
|
||||
#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE)
|
||||
#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE)
|
||||
#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE)
|
||||
#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE)
|
||||
#define IMX_SYSCTRL_BASE (0x1B800 + IMX_IO_BASE)
|
||||
#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE)
|
||||
#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE)
|
||||
#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE)
|
||||
#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE)
|
||||
#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE)
|
||||
#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE)
|
||||
#endif
|
||||
#define MX31_AVIC_BASE_ADDR 0x68000000
|
||||
#define MX31_AVIC_SIZE SZ_1M
|
||||
|
||||
#define MX31_IPU_MEM_BASE_ADDR 0x70000000
|
||||
#define MX31_CSD0_BASE_ADDR 0x80000000
|
||||
#define MX31_CSD1_BASE_ADDR 0x90000000
|
||||
|
||||
#define MX31_CS0_BASE_ADDR 0xa0000000
|
||||
#define MX31_CS0_SIZE SZ_128M
|
||||
|
||||
#define MX31_CS1_BASE_ADDR 0xa8000000
|
||||
#define MX31_CS1_SIZE SZ_128M
|
||||
|
||||
#define MX31_CS2_BASE_ADDR 0xb0000000
|
||||
#define MX31_CS2_SIZE SZ_32M
|
||||
|
||||
#define MX31_CS3_BASE_ADDR 0xb2000000
|
||||
#define MX31_CS3_SIZE SZ_32M
|
||||
|
||||
#define MX31_CS4_BASE_ADDR 0xb4000000
|
||||
#define MX31_CS4_SIZE SZ_32M
|
||||
|
||||
#define MX31_CS5_BASE_ADDR 0xb6000000
|
||||
#define MX31_CS5_SIZE SZ_32M
|
||||
|
||||
#define MX31_X_MEMC_BASE_ADDR 0xb8000000
|
||||
#define MX31_X_MEMC_SIZE SZ_64K
|
||||
#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000)
|
||||
#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000)
|
||||
#define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000)
|
||||
#define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000)
|
||||
#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000)
|
||||
#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR
|
||||
|
||||
#define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10)
|
||||
#define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs))
|
||||
#define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
|
||||
#define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
|
||||
|
||||
#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
|
||||
|
||||
/* FIXME: Get rid of these */
|
||||
#define IMX_TIM1_BASE MX31_GPT1_BASE_ADDR
|
||||
#define IMX_WDT_BASE MX31_WDOG_BASE_ADDR
|
||||
#define IMX_ESD_BASE MX31_ESDCTL_BASE_ADDR
|
||||
#define IMX_NFC_BASE MX31_NFC_BASE_ADDR
|
||||
#define IOMUXC_BASE MX31_IOMUXC_BASE_ADDR
|
||||
|
||||
/*
|
||||
* Clock Controller Module (CCM)
|
||||
*/
|
||||
#define IMX_CCM_BASE 0x53f80000
|
||||
#define CCM_CCMR 0x00
|
||||
#define CCM_PDR0 0x04
|
||||
#define CCM_PDR1 0x08
|
||||
|
|
@ -124,14 +179,8 @@
|
|||
#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
|
||||
#define PDR0_MCU_PODF(x) ((x) & 0x7)
|
||||
|
||||
#define IMX_ESD_BASE 0xb8001000
|
||||
#include "esdctl.h"
|
||||
|
||||
/*
|
||||
* NFC Registers
|
||||
*/
|
||||
#define IMX_NFC_BASE (0xb8000000)
|
||||
|
||||
/*
|
||||
* Chip Select Registers
|
||||
*/
|
||||
|
|
@ -143,26 +192,10 @@
|
|||
/*
|
||||
* ???????????
|
||||
*/
|
||||
#define IOMUXC_BASE 0x43FAC000
|
||||
#define IOMUXC_GPR (IOMUXC_BASE + 0x8)
|
||||
#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
|
||||
#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)
|
||||
|
||||
#define IPU_BASE 0x53fc0000
|
||||
#define IPU_CONF IPU_BASE
|
||||
|
||||
#define IPU_CONF_PXL_ENDIAN (1<<8)
|
||||
#define IPU_CONF_DU_EN (1<<7)
|
||||
#define IPU_CONF_DI_EN (1<<6)
|
||||
#define IPU_CONF_ADC_EN (1<<5)
|
||||
#define IPU_CONF_SDC_EN (1<<4)
|
||||
#define IPU_CONF_PF_EN (1<<3)
|
||||
#define IPU_CONF_ROT_EN (1<<2)
|
||||
#define IPU_CONF_IC_EN (1<<1)
|
||||
#define IPU_CONF_SCI_EN (1<<0)
|
||||
|
||||
#define WDOG_BASE 0x53FDC000
|
||||
|
||||
/*
|
||||
* Signal Multiplexing (IOMUX)
|
||||
*/
|
||||
|
|
@ -214,4 +247,3 @@
|
|||
#define MUX_CSPI2_MISO_I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO)
|
||||
|
||||
#endif /* __ASM_ARCH_MX31_REGS_H */
|
||||
|
||||
|
|
|
|||
|
|
@ -21,12 +21,12 @@ ulong imx_get_mpl_dpdgck_clk(void)
|
|||
{
|
||||
ulong infreq;
|
||||
|
||||
if ((readl(IMX_CCM_BASE + CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
|
||||
if ((readl(MX31_CCM_BASE_ADDR + CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
|
||||
infreq = CONFIG_MX31_CLK32 * 1024;
|
||||
else
|
||||
infreq = CONFIG_MX31_HCLK_FREQ;
|
||||
|
||||
return imx_decode_pll(readl(IMX_CCM_BASE + CCM_MPCTL), infreq);
|
||||
return imx_decode_pll(readl(MX31_CCM_BASE_ADDR + CCM_MPCTL), infreq);
|
||||
}
|
||||
|
||||
ulong imx_get_mcu_main_clk(void)
|
||||
|
|
@ -43,7 +43,7 @@ ulong imx_get_mcu_main_clk(void)
|
|||
*/
|
||||
ulong imx_get_lcdclk(void)
|
||||
{
|
||||
ulong hsp_podf = (readl(IMX_CCM_BASE + CCM_PDR0) >> 11) & 0x03;
|
||||
ulong hsp_podf = (readl(MX31_CCM_BASE_ADDR + CCM_PDR0) >> 11) & 0x03;
|
||||
ulong base_clk = imx_get_mcu_main_clk();
|
||||
|
||||
return base_clk / (hsp_podf + 1);
|
||||
|
|
@ -52,7 +52,7 @@ ulong imx_get_lcdclk(void)
|
|||
ulong imx_get_perclk1(void)
|
||||
{
|
||||
u32 freq = imx_get_mcu_main_clk();
|
||||
u32 pdr0 = readl(IMX_CCM_BASE + CCM_PDR0);
|
||||
u32 pdr0 = readl(MX31_CCM_BASE_ADDR + CCM_PDR0);
|
||||
|
||||
freq /= ((pdr0 >> 3) & 0x7) + 1;
|
||||
freq /= ((pdr0 >> 6) & 0x3) + 1;
|
||||
|
|
|
|||
Loading…
Reference in New Issue