ARM i.MX: Add Ka-Ro TX53 board support
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
526a745f68
commit
ae50b6287a
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@ -141,6 +141,7 @@ board-$(CONFIG_MACH_TOSHIBA_AC100) := toshiba-ac100
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board-$(CONFIG_MACH_CCMX51) := ccxmx51
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board-$(CONFIG_MACH_TINY210) := friendlyarm-tiny210
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board-$(CONFIG_MACH_SABRELITE) := freescale-mx6-sabrelite
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board-$(CONFIG_MACH_TX53) := karo-tx53
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machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
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@ -0,0 +1,2 @@
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obj-y += board.o
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obj-y += flash_header.o
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@ -0,0 +1,240 @@
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/*
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* Copyright (C) 2012 Sascha Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <environment.h>
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#include <fcntl.h>
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#include <fec.h>
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#include <fs.h>
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#include <init.h>
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#include <nand.h>
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#include <net.h>
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#include <partition.h>
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#include <sizes.h>
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#include <generated/mach-types.h>
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#include <mach/imx-regs.h>
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#include <mach/iomux-mx53.h>
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#include <mach/devices-imx53.h>
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#include <mach/generic.h>
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#include <mach/gpio.h>
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#include <mach/imx-nand.h>
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#include <mach/iim.h>
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#include <mach/imx5.h>
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#include <asm/armlinux.h>
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#include <io.h>
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#include <asm/mmu.h>
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static struct fec_platform_data fec_info = {
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.xcv_type = RMII,
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};
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static iomux_v3_cfg_t tx53_pads[] = {
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/* UART1 */
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MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
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MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
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MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
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MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
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MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
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MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
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/* setup FEC PHY pins for GPIO function */
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MX53_PAD_FEC_REF_CLK__GPIO1_23,
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MX53_PAD_FEC_MDC__GPIO1_31,
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MX53_PAD_FEC_MDIO__GPIO1_22,
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MX53_PAD_FEC_RXD0__GPIO1_27,
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MX53_PAD_FEC_RXD1__GPIO1_26,
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MX53_PAD_FEC_RX_ER__GPIO1_24,
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MX53_PAD_FEC_TX_EN__GPIO1_28,
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MX53_PAD_FEC_TXD0__GPIO1_30,
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MX53_PAD_FEC_TXD1__GPIO1_29,
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MX53_PAD_FEC_CRS_DV__GPIO1_25,
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/* FEC PHY reset */
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MX53_PAD_PATA_DA_0__GPIO7_6,
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/* FEC PHY power */
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MX53_PAD_EIM_D20__GPIO3_20,
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/* SD1 */
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MX53_PAD_SD1_CMD__ESDHC1_CMD,
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MX53_PAD_SD1_CLK__ESDHC1_CLK,
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MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
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MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
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MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
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MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
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/* SD1_CD */
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MX53_PAD_EIM_D24__GPIO3_24,
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MX53_PAD_GPIO_3__I2C3_SCL,
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MX53_PAD_GPIO_6__I2C3_SDA,
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MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12,
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MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13,
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MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14,
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MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15,
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MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16,
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MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17,
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MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18,
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MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19,
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MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC,
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MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC,
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MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK,
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};
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static int tx53_mem_init(void)
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{
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arm_add_mem_device("ram0", 0x70000000, SZ_1G);
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return 0;
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}
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mem_initcall(tx53_mem_init);
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#define TX53_SD1_CD IMX_GPIO_NR(3, 24)
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static struct esdhc_platform_data tx53_sd1_data = {
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.cd_gpio = TX53_SD1_CD,
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.cd_type = ESDHC_CD_GPIO,
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.wp_type = ESDHC_WP_NONE,
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};
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struct imx_nand_platform_data nand_info = {
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.width = 1,
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.hw_ecc = 1,
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.flash_bbt = 1,
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};
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#define FEC_POWER_GPIO IMX_GPIO_NR(3, 20)
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#define FEC_RESET_GPIO IMX_GPIO_NR(7, 6)
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static struct tx53_fec_gpio_setup {
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iomux_v3_cfg_t pad;
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unsigned gpio:9,
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dir:1,
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level:1;
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} tx53_fec_gpios[] = {
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{ MX53_PAD_PATA_DA_0__GPIO7_6, FEC_RESET_GPIO, 1, 0, }, /* PHY reset */
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{ MX53_PAD_EIM_D20__GPIO3_20, FEC_POWER_GPIO, 1, 1, }, /* PHY power enable */
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{ MX53_PAD_FEC_REF_CLK__GPIO1_23, IMX_GPIO_NR(1, 23), 0, }, /* ENET_CLK */
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{ MX53_PAD_FEC_MDC__GPIO1_31, IMX_GPIO_NR(1, 31), 1, 0, }, /* MDC */
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{ MX53_PAD_FEC_MDIO__GPIO1_22, IMX_GPIO_NR(1, 22), 1, 0, }, /* MDIO */
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{ MX53_PAD_FEC_RXD0__GPIO1_27, IMX_GPIO_NR(1, 27), 1, 1, }, /* Mode0/RXD0 */
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{ MX53_PAD_FEC_RXD1__GPIO1_26, IMX_GPIO_NR(1, 26), 1, 1, }, /* Mode1/RXD1 */
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{ MX53_PAD_FEC_RX_ER__GPIO1_24, IMX_GPIO_NR(1, 24), 0, }, /* RX_ER */
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{ MX53_PAD_FEC_TX_EN__GPIO1_28, IMX_GPIO_NR(1, 28), 1, 0, }, /* TX_EN */
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{ MX53_PAD_FEC_TXD0__GPIO1_30, IMX_GPIO_NR(1, 30), 1, 0, }, /* TXD0 */
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{ MX53_PAD_FEC_TXD1__GPIO1_29, IMX_GPIO_NR(1, 29), 1, 0, }, /* TXD1 */
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{ MX53_PAD_FEC_CRS_DV__GPIO1_25, IMX_GPIO_NR(1, 25), 1, 1, }, /* Mode2/CRS_DV */
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};
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static iomux_v3_cfg_t tx53_fec_pads[] = {
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MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
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MX53_PAD_FEC_MDC__FEC_MDC,
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MX53_PAD_FEC_MDIO__FEC_MDIO,
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MX53_PAD_FEC_RXD0__FEC_RDATA_0,
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MX53_PAD_FEC_RXD1__FEC_RDATA_1,
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MX53_PAD_FEC_RX_ER__FEC_RX_ER,
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MX53_PAD_FEC_TX_EN__FEC_TX_EN,
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MX53_PAD_FEC_TXD0__FEC_TDATA_0,
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MX53_PAD_FEC_TXD1__FEC_TDATA_1,
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MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
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};
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static inline void tx53_fec_init(void)
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{
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int i;
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/* Configure LAN8700 pads as GPIO and set up
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* necessary strap options for PHY
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*/
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for (i = 0; i < ARRAY_SIZE(tx53_fec_gpios); i++) {
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struct tx53_fec_gpio_setup *gs = &tx53_fec_gpios[i];
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if (gs->dir)
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gpio_direction_output(gs->gpio, gs->level);
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else
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gpio_direction_input(gs->gpio);
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mxc_iomux_v3_setup_pad(gs->pad);
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}
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/*
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*Turn on phy power, leave in reset state
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*/
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gpio_set_value(FEC_POWER_GPIO, 1);
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/*
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* Wait some time to let the phy activate the internal regulator
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*/
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mdelay(10);
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/*
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* Deassert reset, phy latches the rest of bootstrap pins
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*/
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gpio_set_value(FEC_RESET_GPIO, 1);
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/* LAN7800 has an internal Power On Reset (POR) signal (OR'ed with
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* the external RESET signal) which is deactivated 21ms after
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* power on and latches the strap options.
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* Delay for 22ms to ensure, that the internal POR is inactive
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* before reconfiguring the strap pins.
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*/
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mdelay(22);
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/*
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* The phy is ready, now configure imx51 pads for fec operation
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*/
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mxc_iomux_v3_setup_multiple_pads(tx53_fec_pads,
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ARRAY_SIZE(tx53_fec_pads));
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}
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static int tx53_devices_init(void)
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{
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imx53_iim_register_fec_ethaddr();
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tx53_fec_init();
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imx53_add_fec(&fec_info);
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imx53_add_mmc0(&tx53_sd1_data);
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imx53_add_nand(&nand_info);
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armlinux_set_bootparams((void *)0x70000100);
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armlinux_set_architecture(MACH_TYPE_TX53);
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return 0;
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}
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device_initcall(tx53_devices_init);
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static int tx53_part_init(void)
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{
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devfs_add_partition("disk0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self0");
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devfs_add_partition("disk0", SZ_512K, SZ_1M, DEVFS_PARTITION_FIXED, "env0");
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return 0;
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}
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late_initcall(tx53_part_init);
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static int tx53_console_init(void)
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{
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mxc_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
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imx53_init_lowlevel(1000);
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imx53_add_uart0();
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return 0;
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}
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console_initcall(tx53_console_init);
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@ -0,0 +1,24 @@
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/**
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* @file
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* @brief Global defintions for the ARM i.MX51 based babbage board
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#endif /* __CONFIG_H */
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@ -0,0 +1,8 @@
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#!/bin/sh
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if [ "$1" = menu ]; then
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init-menu-add-entry "$0" "Base bootargs"
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exit
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fi
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global.linux.bootargs.base="console=ttymxc0,115200"
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@ -0,0 +1,8 @@
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#!/bin/sh
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if [ "$1" = menu ]; then
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init-menu-add-entry "$0" "hostname"
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exit
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fi
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global.hostname=tx53
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@ -0,0 +1,147 @@
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/*
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* Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <asm/byteorder.h>
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#include <mach/imx-flash-header.h>
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#include <asm/barebox-arm-head.h>
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void __naked __flash_header_start go(void)
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{
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barebox_arm_head();
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}
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/*
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* FIXME: These are the dcd values for a Ka-Ro TX53 1011 which
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* is not in production. It has 1GB DDR2 memory.
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*/
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struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
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{ .addr = cpu_to_be32(0x53fd406c), .val = cpu_to_be32(0xffffffff), },
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{ .addr = cpu_to_be32(0x53fd4070), .val = cpu_to_be32(0xffffffff), },
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{ .addr = cpu_to_be32(0x53fd4074), .val = cpu_to_be32(0xffffffff), },
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{ .addr = cpu_to_be32(0x53fd4078), .val = cpu_to_be32(0xffffffff), },
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{ .addr = cpu_to_be32(0x53fd407c), .val = cpu_to_be32(0xffffffff), },
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{ .addr = cpu_to_be32(0x53fd4080), .val = cpu_to_be32(0xffffffff), },
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{ .addr = cpu_to_be32(0x53fd4088), .val = cpu_to_be32(0xffffffff), },
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{ .addr = cpu_to_be32(0x53fa8174), .val = cpu_to_be32(0x00000011), },
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{ .addr = cpu_to_be32(0x63fd800c), .val = cpu_to_be32(0x00000000), },
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{ .addr = cpu_to_be32(0x53fa8554), .val = cpu_to_be32(0x00200000), },
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{ .addr = cpu_to_be32(0x53fa8560), .val = cpu_to_be32(0x00200000), },
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{ .addr = cpu_to_be32(0x53fa8594), .val = cpu_to_be32(0x00200000), },
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{ .addr = cpu_to_be32(0x53fa8584), .val = cpu_to_be32(0x00200000), },
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{ .addr = cpu_to_be32(0x53fa8558), .val = cpu_to_be32(0x00200040), },
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{ .addr = cpu_to_be32(0x53fa8568), .val = cpu_to_be32(0x00200040), },
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{ .addr = cpu_to_be32(0x53fa8590), .val = cpu_to_be32(0x00200040), },
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{ .addr = cpu_to_be32(0x53fa857c), .val = cpu_to_be32(0x00200040), },
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{ .addr = cpu_to_be32(0x53fa8564), .val = cpu_to_be32(0x00200040), },
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{ .addr = cpu_to_be32(0x53fa8580), .val = cpu_to_be32(0x00200040), },
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{ .addr = cpu_to_be32(0x53fa8570), .val = cpu_to_be32(0x00200000), },
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{ .addr = cpu_to_be32(0x53fa8578), .val = cpu_to_be32(0x00200000), },
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{ .addr = cpu_to_be32(0x53fa872c), .val = cpu_to_be32(0x00200000), },
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{ .addr = cpu_to_be32(0x53fa8728), .val = cpu_to_be32(0x00200000), },
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{ .addr = cpu_to_be32(0x53fa871c), .val = cpu_to_be32(0x00200000), },
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{ .addr = cpu_to_be32(0x53fa8718), .val = cpu_to_be32(0x00200000), },
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{ .addr = cpu_to_be32(0x53fa8574), .val = cpu_to_be32(0x00280000), },
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{ .addr = cpu_to_be32(0x53fa8588), .val = cpu_to_be32(0x00280000), },
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{ .addr = cpu_to_be32(0x53fa86f0), .val = cpu_to_be32(0x00280000), },
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{ .addr = cpu_to_be32(0x53fa8720), .val = cpu_to_be32(0x00280000), },
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{ .addr = cpu_to_be32(0x53fa86fc), .val = cpu_to_be32(0x00000000), },
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{ .addr = cpu_to_be32(0x53fa86f4), .val = cpu_to_be32(0x00000200), },
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{ .addr = cpu_to_be32(0x53fa8714), .val = cpu_to_be32(0x00000000), },
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{ .addr = cpu_to_be32(0x53fa8724), .val = cpu_to_be32(0x06000000), },
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{ .addr = cpu_to_be32(0x63fd9088), .val = cpu_to_be32(0x36353b38), },
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{ .addr = cpu_to_be32(0x63fd9090), .val = cpu_to_be32(0x49434942), },
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{ .addr = cpu_to_be32(0x63fd90f8), .val = cpu_to_be32(0x00000800), },
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{ .addr = cpu_to_be32(0x63fd907c), .val = cpu_to_be32(0x01350138), },
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{ .addr = cpu_to_be32(0x63fd9080), .val = cpu_to_be32(0x01380139), },
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{ .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00001710), },
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{ .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0x84110000), },
|
||||
{ .addr = cpu_to_be32(0x63fd900c), .val = cpu_to_be32(0x4d5122d2), },
|
||||
{ .addr = cpu_to_be32(0x63fd9010), .val = cpu_to_be32(0xb6f18a22), },
|
||||
{ .addr = cpu_to_be32(0x63fd9014), .val = cpu_to_be32(0x00c700db), },
|
||||
{ .addr = cpu_to_be32(0x63fd902c), .val = cpu_to_be32(0x000026d2), },
|
||||
{ .addr = cpu_to_be32(0x63fd9030), .val = cpu_to_be32(0x009f000e), },
|
||||
{ .addr = cpu_to_be32(0x63fd9008), .val = cpu_to_be32(0x12272000), },
|
||||
{ .addr = cpu_to_be32(0x63fd9004), .val = cpu_to_be32(0x00030012), },
|
||||
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008010), },
|
||||
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008020), },
|
||||
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008020), },
|
||||
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0a528030), },
|
||||
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x03868031), },
|
||||
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00068031), },
|
||||
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), },
|
||||
{ .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00005800), },
|
||||
{ .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00033332), },
|
||||
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), },
|
||||
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00448031), },
|
||||
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008018), },
|
||||
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), },
|
||||
{ .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x04b80003), },
|
||||
{ .addr = cpu_to_be32(0x53fa8004), .val = cpu_to_be32(0x00194005), },
|
||||
{ .addr = cpu_to_be32(0x53fa819c), .val = cpu_to_be32(0x00000000), },
|
||||
{ .addr = cpu_to_be32(0x53fa81a0), .val = cpu_to_be32(0x00000000), },
|
||||
{ .addr = cpu_to_be32(0x53fa81a4), .val = cpu_to_be32(0x00000000), },
|
||||
{ .addr = cpu_to_be32(0x53fa81a8), .val = cpu_to_be32(0x00000000), },
|
||||
{ .addr = cpu_to_be32(0x53fa81ac), .val = cpu_to_be32(0x00000000), },
|
||||
{ .addr = cpu_to_be32(0x53fa81b0), .val = cpu_to_be32(0x00000000), },
|
||||
{ .addr = cpu_to_be32(0x53fa81b4), .val = cpu_to_be32(0x00000000), },
|
||||
{ .addr = cpu_to_be32(0x53fa81b8), .val = cpu_to_be32(0x00000000), },
|
||||
{ .addr = cpu_to_be32(0x53fa81dc), .val = cpu_to_be32(0x00000000), },
|
||||
{ .addr = cpu_to_be32(0x53fa81e0), .val = cpu_to_be32(0x00000000), },
|
||||
{ .addr = cpu_to_be32(0x53fa8228), .val = cpu_to_be32(0x00000000), },
|
||||
{ .addr = cpu_to_be32(0x53fa822c), .val = cpu_to_be32(0x00000000), },
|
||||
{ .addr = cpu_to_be32(0x53fa8230), .val = cpu_to_be32(0x00000000), },
|
||||
{ .addr = cpu_to_be32(0x53fa8234), .val = cpu_to_be32(0x00000000), },
|
||||
{ .addr = cpu_to_be32(0x53fa8238), .val = cpu_to_be32(0x00000000), },
|
||||
{ .addr = cpu_to_be32(0x53fa84ec), .val = cpu_to_be32(0x000000e4), },
|
||||
{ .addr = cpu_to_be32(0x53fa84f0), .val = cpu_to_be32(0x000000e4), },
|
||||
{ .addr = cpu_to_be32(0x53fa84f4), .val = cpu_to_be32(0x000000e4), },
|
||||
{ .addr = cpu_to_be32(0x53fa84f8), .val = cpu_to_be32(0x000000e4), },
|
||||
{ .addr = cpu_to_be32(0x53fa84fc), .val = cpu_to_be32(0x000000e4), },
|
||||
{ .addr = cpu_to_be32(0x53fa8500), .val = cpu_to_be32(0x000000e4), },
|
||||
{ .addr = cpu_to_be32(0x53fa8504), .val = cpu_to_be32(0x000000e4), },
|
||||
{ .addr = cpu_to_be32(0x53fa8508), .val = cpu_to_be32(0x000000e4), },
|
||||
{ .addr = cpu_to_be32(0x53fa852c), .val = cpu_to_be32(0x00000004), },
|
||||
{ .addr = cpu_to_be32(0x53fa8530), .val = cpu_to_be32(0x00000004), },
|
||||
{ .addr = cpu_to_be32(0x53fa85a0), .val = cpu_to_be32(0x00000004), },
|
||||
{ .addr = cpu_to_be32(0x53fa85a4), .val = cpu_to_be32(0x00000004), },
|
||||
{ .addr = cpu_to_be32(0x53fa85a8), .val = cpu_to_be32(0x000000e4), },
|
||||
{ .addr = cpu_to_be32(0x53fa85ac), .val = cpu_to_be32(0x000000e4), },
|
||||
{ .addr = cpu_to_be32(0x53fa85b0), .val = cpu_to_be32(0x00000004), },
|
||||
};
|
||||
|
||||
#define APP_DEST 0x70000000
|
||||
|
||||
struct imx_flash_header_v2 __flash_header_section flash_header = {
|
||||
.header.tag = IVT_HEADER_TAG,
|
||||
.header.length = cpu_to_be16(32),
|
||||
.header.version = IVT_VERSION,
|
||||
|
||||
.entry = APP_DEST + 0x1000,
|
||||
.dcd_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, dcd),
|
||||
.boot_data_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, boot_data),
|
||||
.self = APP_DEST + 0x400,
|
||||
|
||||
.boot_data.start = APP_DEST,
|
||||
.boot_data.size = DCD_BAREBOX_SIZE,
|
||||
|
||||
.dcd.header.tag = DCD_HEADER_TAG,
|
||||
.dcd.header.length = cpu_to_be16(sizeof(struct imx_dcd) + sizeof(dcd_entry)),
|
||||
.dcd.header.version = DCD_VERSION,
|
||||
|
||||
.dcd.command.tag = DCD_COMMAND_WRITE_TAG,
|
||||
.dcd.command.length = cpu_to_be16(sizeof(struct imx_dcd_command) + sizeof(dcd_entry)),
|
||||
.dcd.command.param = DCD_COMMAND_WRITE_PARAM,
|
||||
};
|
||||
|
|
@ -27,6 +27,7 @@ config ARCH_TEXT_BASE
|
|||
default 0x4fc00000 if MACH_MX6Q_ARM2
|
||||
default 0x97f00000 if MACH_CCMX51
|
||||
default 0x4fc00000 if MACH_SABRELITE
|
||||
default 0x7fe00000 if MACH_TX53
|
||||
|
||||
config BOARDINFO
|
||||
default "Eukrea CPUIMX25" if MACH_EUKREA_CPUIMX25
|
||||
|
|
@ -53,6 +54,7 @@ config BOARDINFO
|
|||
default "Freescale i.MX6q armadillo2" if MACH_MX6Q_ARM2
|
||||
default "ConnectCore i.MX51" if MACH_CCMX51
|
||||
default "Sabre Lite" if MACH_SABRELITE
|
||||
default "Ka-Ro tx53" if MACH_TX53
|
||||
|
||||
choice
|
||||
prompt "Select boot mode"
|
||||
|
|
@ -459,6 +461,12 @@ config MACH_TQMA53_1GB_RAM
|
|||
help
|
||||
use 1GiB of SDRAM (512MiB otherwise)
|
||||
|
||||
config MACH_TX53
|
||||
bool "Ka-Ro TX53"
|
||||
select HAVE_DEFAULT_ENVIRONMENT_NEW
|
||||
help
|
||||
Say Y here if you are using the Ka-Ro tx53 board
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue