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S3C24xx/NFC: Setup ECC handling in accordance to the kernel 

Do the same ECC handling and ECC size in barebox than the kernel does.
Currently its done for S3C2440 based systems only, as I have no idea how to
manage it on a S3C2410 based system.

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Juergen Beisert 2011-03-12 20:14:56 +01:00 committed by Sascha Hauer
parent e0965c4d56
commit b31dd110aa
1 changed files with 17 additions and 4 deletions
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21
drivers/mtd/nand/nand_s3c2410.c
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@ -450,11 +450,24 @@ static int s3c24x0_nand_probe(struct device_d *dev)
chip->ecc.correct = s3c2410_nand_correct_data;
chip->ecc.hwctl = s3c2410_nand_enable_hwecc;
/* our hardware capabilities */
/*
* Setup ECC handling in accordance to the kernel
* - 1 times 512 bytes with 24 bit ECC for small page
* - 8 times 256 bytes with 24 bit ECC each for large page
*/
chip->ecc.mode = NAND_ECC_HW;
chip->ecc.size = 512;
chip->ecc.bytes = 3;
chip->ecc.layout = &nand_hw_eccoob;
chip->ecc.bytes = 3; /* always 24 bit ECC per turn */
#ifdef CONFIG_CPU_S3C2440
if (readl(host->base) & 0x8) {
/* large page (2048 bytes per page) */
chip->ecc.size = 256;
} else
#endif
{
/* small page (512 bytes per page) */
chip->ecc.size = 512;
chip->ecc.layout = &nand_hw_eccoob;
}
if (pdata->flash_bbt) {
/* use a flash based bbt */