diff --git a/CHANGELOG b/CHANGELOG index 2c8c336e2..32d6c6208 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,15 @@ Changes since U-Boot 1.0.0: ====================================================================== +* Patch by Denis Peter, 8 Dec 2003 + - add support for the PATI board (MPC555) + - add SPI support for the MPC5xx + +* Patch by Anders Larsen, 08 Dec 2003: + add configuration options CONFIG_SERIAL_TAG and CONFIG_REVISION_TAG + to pass ATAG_SERIAL and ATAG_REVISION, resp., to the ARM target; + cleanup some redundand #defines + * Patch by André Schwarz, 8 Dec 2003: fixes for Davicom DM9102A Ethernet Chip (#define CONFIG_TULIP_FIX_DAVICOM): - TX and RX deskriptors must be quad-word aligned diff --git a/Makefile b/Makefile index bb62b0e25..36cc08907 100644 --- a/Makefile +++ b/Makefile @@ -198,6 +198,9 @@ unconfig: cmi_mpc5xx_config: unconfig @./mkconfig $(@:_config=) ppc mpc5xx cmi +PATI_config:unconfig + @./mkconfig $(@:_config=) ppc mpc5xx pati mpl + ######################################################################### ## MPC5xxx Systems ######################################################################### diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c index 9c98c93b5..511739401 100644 --- a/board/mpl/common/common_util.c +++ b/board/mpl/common/common_util.c @@ -42,6 +42,9 @@ #include "../mip405/mip405.h" #include <405gp_pci.h> #endif +#if defined(CONFIG_PATI) +#define FIRM_START 0xFFF00000 +#endif extern int gunzip(void *, int, uchar *, int *); extern int mem_test(ulong start, ulong ramsize, int quiet); @@ -60,14 +63,17 @@ mpl_prg(uchar *src, ulong size) ulong start; flash_info_t *info; int i, rc; -#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) +#if defined(CONFIG_PATI) + int start_sect; +#endif +#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) || defined(CONFIG_PATI) char *copystr = (char *)src; ulong *magic = (ulong *)src; #endif info = &flash_info[0]; -#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) +#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) || defined(CONFIG_PATI) if (ntohl(magic[0]) != IH_MAGIC) { puts("Bad Magic number\n"); return -1; @@ -90,6 +96,7 @@ mpl_prg(uchar *src, ulong size) printf("Wrong Firmware Image: %s\n", ©str[i]); return -1; } +#if !defined(CONFIG_PATI) start = 0 - size; for (i = info->sector_count-1; i > 0; i--) { info->protect[i] = 0; /* unprotect this sector */ @@ -106,6 +113,36 @@ mpl_prg(uchar *src, ulong size) return (1); } +#else /* #if !defined(CONFIG_PATI */ + start = FIRM_START; + start_sect = -1; + for (i = 0; i < info->sector_count; i++) { + if (start < info->start[i]) { + start_sect = i - 1; + break; + } + } + + info->protect[i - 1] = 0; /* unprotect this sector */ + for (; i < info->sector_count; i++) { + if ((start + size) < info->start[i]) + break; + info->protect[i] = 0; /* unprotect this sector */ + } + + i--; + /* set-up flash location */ + /* now erase flash */ + printf ("Erasing at %lx to %lx (sector %d to %d) (%lx to %lx)\n", + start, start + size, start_sect, i, + info->start[start_sect], info->start[i]); + if ((rc = flash_erase (info, start_sect, i)) != 0) { + puts ("ERROR "); + flash_perror (rc); + return (1); + } +#endif /* defined(CONFIG_PATI) */ + #elif defined(CONFIG_VCMA9) start = 0; for (i = 0; i sector_count; i++) { @@ -227,7 +264,7 @@ mpl_prg_image(uchar *ld_addr) return(rc); } - +#if !defined(CONFIG_PATI) void get_backup_values(backup_t *buf) { i2c_read(CFG_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)buf,sizeof(backup_t)); @@ -417,14 +454,17 @@ void show_stdio_dev(void) } } +#endif /* #if !defined(CONFIG_PATI) */ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { ulong size,src,ld_addr; int result; +#if !defined(CONFIG_PATI) backup_t back; src = MULTI_PURPOSE_SOCKET_ADDR; size = IMAGE_SIZE; +#endif if (strcmp(argv[1], "flash") == 0) { @@ -460,11 +500,13 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) result=mpl_prg_image((uchar *)ld_addr); return result; } +#if !defined(CONFIG_PATI) if (strcmp(argv[2], "mps") == 0) { puts("\nupdating bootloader image from MPS\n"); result=mpl_prg((uchar *)src,size); return result; } +#endif /* #if !defined(CONFIG_PATI) */ } if (strcmp(argv[1], "mem") == 0) { @@ -490,6 +532,7 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) }while(result); return 0; } +#if !defined(CONFIG_PATI) if (strcmp(argv[1], "clearenvvalues") == 0) { if (strcmp(argv[2], "yes") == 0) @@ -512,6 +555,7 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) set_backup_values(1); return 0; } +#endif printf("Usage:\n%s\n", cmdtp->usage); return 1; } diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c index 5f50200b2..fd430083e 100644 --- a/board/mpl/common/flash.c +++ b/board/mpl/common/flash.c @@ -36,6 +36,8 @@ */ #include + +#if !defined(CONFIG_PATI) #include #include #include "common_util.h" @@ -46,6 +48,9 @@ #include "../pip405/pip405.h" #endif #include <405gp_pci.h> +#else /* defined(CONFIG_PATI) */ +#include +#endif flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- @@ -56,22 +61,15 @@ static int write_word (flash_info_t *info, ulong dest, ulong data); void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt); - -#ifdef CONFIG_PIP405 #define ADDR0 0x5555 #define ADDR1 0x2aaa #define FLASH_WORD_SIZE unsigned short -#endif - -#ifdef CONFIG_MIP405 -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned short -#endif #define FALSE 0 #define TRUE 1 +#if !defined(CONFIG_PATI) + /*----------------------------------------------------------------------- * Some CS switching routines: * @@ -151,11 +149,16 @@ void setup_cs_reloc(void) } } +#endif /* #if !defined(CONFIG_PATI) */ unsigned long flash_init (void) { - unsigned long size_b0, size_b1,flashcr, size_reg; - int mode, i; + unsigned long size_b0; + int i; + +#if !defined(CONFIG_PATI) + unsigned long size_b1,flashcr,size_reg; + int mode; extern char version_string; char *p=&version_string; @@ -169,6 +172,7 @@ unsigned long flash_init (void) else printf("(%s Boot) ",(mode & BOOT_MPS) ? "MPS" : "Flash"); +#endif /* #if !defined(CONFIG_PATI) */ /* Init: no FLASHes known */ for (i=0; i $@ + +-include .depend + +######################################################################### diff --git a/board/mpl/pati/cmd_pati.c b/board/mpl/pati/cmd_pati.c new file mode 100644 index 000000000..cdab28657 --- /dev/null +++ b/board/mpl/pati/cmd_pati.c @@ -0,0 +1,451 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Adapted for PATI + */ + +#include +#include +#define PLX9056_LOC +#include "plx9056.h" +#include "pati.h" +#include "pci_eeprom.h" + +extern void show_pld_regs(void); +extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +extern void user_led0(int led_on); +extern void user_led1(int led_on); + +/* ------------------------------------------------------------------------- */ +#if defined(CFG_PCI_CON_DEVICE) +extern void pci_con_disc(void); +extern void pci_con_connect(void); +#endif + +/****************************************************************************** + * Eeprom Support + ******************************************************************************/ +unsigned long get32(unsigned long addr) +{ + unsigned long *p=(unsigned long *)addr; + return *p; +} + +void set32(unsigned long addr,unsigned long data) +{ + unsigned long *p=(unsigned long *)addr; + *p=data; +} + +#define PCICFG_GET_REG(x) (get32((x) + PCI_CONFIG_BASE)) +#define PCICFG_SET_REG(x,y) (set32((x) + PCI_CONFIG_BASE,(y))) + + +/****************************************************************************** + * reload_pci_eeprom + ******************************************************************************/ + +static void reload_pci_eeprom(void) +{ + unsigned long reg; + /* Set Bit 29 and clear it again */ + reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); + udelay(1); + /* set it*/ + reg|=(1<<29); + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); + /* EECLK @ 33MHz = 125kHz + * -> extra long load = 32 * 16bit = 512Bit @ 125kHz = 4.1msec + * use 20msec + */ + udelay(20000); /* wait 20ms */ + reg &= ~(1<<29); /* set it low */ + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); + udelay(1); /* wait some time */ +} + +/****************************************************************************** + * clock_pci_eeprom + ******************************************************************************/ + +static void clock_pci_eeprom(void) +{ + unsigned long reg; + /* clock is low, data is valid */ + reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); + udelay(1); + /* set clck high */ + reg|=(1<<24); + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); + udelay(1); /* wait some time */ + reg &= ~(1<<24); /* set clock low */ + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); + udelay(1); /* wait some time */ +} + +/****************************************************************************** + * send_pci_eeprom_cmd + ******************************************************************************/ +static void send_pci_eeprom_cmd(unsigned long cmd, unsigned char len) +{ + unsigned long reg; + int i; + reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); + /* Clear all EEPROM bits */ + reg &= ~(0xF << 24); + /* Toggle EEPROM's Chip select to get it out of Shift Register Mode */ + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); + udelay(1); /* wait some time */ + /* Enable EEPROM Chip Select */ + reg |= (1 << 25); + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); + /* Send EEPROM command - one bit at a time */ + for (i = (int)(len-1); i >= 0; i--) { + /* Check if current bit is 0 or 1 */ + if (cmd & (1 << i)) + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26))); + else + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); + clock_pci_eeprom(); + } +} + +/****************************************************************************** + * write_pci_eeprom_offs + ******************************************************************************/ +static void write_pci_eeprom_offs(unsigned short offset, unsigned short value) +{ + unsigned long reg; + int bitpos, cmdshft, cmdlen, timeout; + /* we're using the Eeprom 93CS66 */ + cmdshft = 2; + cmdlen = EE66_CMD_LEN; + /* Send Write_Enable command to EEPROM */ + send_pci_eeprom_cmd((EE_WREN << cmdshft),cmdlen); + /* Send EEPROM Write command and offset to EEPROM */ + send_pci_eeprom_cmd((EE_WRITE << cmdshft) | (offset / 2),cmdlen); + reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); + /* Clear all EEPROM bits */ + reg &= ~(0xF << 24); + /* Make sure EEDO Input is disabled for some PLX chips */ + reg &= ~(1 << 31); + /* Enable EEPROM Chip Select */ + reg |= (1 << 25); + /* Write 16-bit value to EEPROM - one bit at a time */ + for (bitpos = 15; bitpos >= 0; bitpos--) { + /* Get bit value and shift into result */ + if (value & (1 << bitpos)) + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26))); + else + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg ); + clock_pci_eeprom(); + } /* for */ + /* Deselect Chip */ + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(1 << 25)); + /* Re-select Chip */ + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 25)); + /* A small delay is needed to let EEPROM complete */ + timeout = 0; + do { + udelay(10); + reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); + timeout++; + } while (((reg & (1 << 27)) == 0) && timeout < 20000); + /* Send Write_Disable command to EEPROM */ + send_pci_eeprom_cmd((EE_WDS << cmdshft),cmdlen); + /* Clear Chip Select and all other EEPROM bits */ + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24)); +} + + +/****************************************************************************** + * read_pci_eeprom_offs + ******************************************************************************/ +static void read_pci_eeprom_offs(unsigned short offset, unsigned short *pvalue) +{ + unsigned long reg; + int bitpos, cmdshft, cmdlen; + /* we're using the Eeprom 93CS66 */ + cmdshft = 2; + cmdlen = EE66_CMD_LEN; + /* Send EEPROM read command and offset to EEPROM */ + send_pci_eeprom_cmd((EE_READ << cmdshft) | (offset / 2),cmdlen); + /* Set EEPROM write output bit */ + reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); + /* Set EEDO Input enable */ + reg |= (1 << 31); + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 26)); + /* Get 16-bit value from EEPROM - one bit at a time */ + for (bitpos = 0; bitpos < 16; bitpos++) { + clock_pci_eeprom(); + udelay(10); + reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); + /* Get bit value and shift into result */ + if (reg & (1 << 27)) + *pvalue = (unsigned short)((*pvalue << 1) | 1); + else + *pvalue = (unsigned short)(*pvalue << 1); + } + /* Clear EEDO Input enable */ + reg &= ~(1 << 31); + /* Clear Chip Select and all other EEPROM bits */ + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24)); +} + + +/****************************************************************************** + * EEPROM read/writes +******************************************************************************/ + +#undef EEPROM_DBG +static int pati_pci_eeprom_erase(void) +{ + int i; + printf("Erasing EEPROM "); + for( i=0; i < PATI_EEPROM_LAST_OFFSET; i+=2) { + write_pci_eeprom_offs(i,0xffff); + if((i%0x10)) + printf("."); + } + printf("\nDone\n"); + return 0; +} + +static int pati_pci_eeprom_prg(void) +{ + int i; + i=0; + printf("Programming EEPROM "); + while(pati_eeprom[i].offset<0xffff) { + write_pci_eeprom_offs(pati_eeprom[i].offset,pati_eeprom[i].value); + #ifdef EEPROM_DBG + printf("0x%04X: 0x%04X\n",pati_eeprom[i].offset, pati_eeprom[i].value); + #else + if((i%0x10)) + printf("."); + #endif + i++; + } + printf("\nDone\n"); + return 0; +} + +static int pati_pci_eeprom_write(unsigned short offset, unsigned long addr, unsigned short size) +{ + int i; + unsigned short value; + unsigned short *buffer =(unsigned short *)addr; + if((offset + size) > PATI_EEPROM_LAST_OFFSET) { + size = PATI_EEPROM_LAST_OFFSET - offset; + } + printf("Write To EEPROM from 0x%lX to 0x%X 0x%X words\n", addr, offset, size/2); + for( i = offset; i< (offset + size); i+=2) { + value = *buffer++; + write_pci_eeprom_offs(i,value); + #ifdef EEPROM_DBG + printf("0x%04X: 0x%04X\n",i, value); + #else + if((i%0x10)) + printf("."); + #endif + } + printf("\nDone\n"); + return 0; +} + +static int pati_pci_eeprom_read(unsigned short offset, unsigned long addr, unsigned short size) +{ + int i; + unsigned short value; + unsigned short *buffer =(unsigned short *)addr; + if((offset + size) > PATI_EEPROM_LAST_OFFSET) { + size = PATI_EEPROM_LAST_OFFSET - offset; + } + printf("Read from EEPROM from 0x%X to 0x%lX 0x%X words\n", offset, addr, size/2); + for( i = offset; i< (offset + size); i+=2) { + read_pci_eeprom_offs(i,&value); + *buffer++=value; + #ifdef EEPROM_DBG + printf("0x%04X: 0x%04X\n",i, value); + #else + if((i%0x10)) + printf("."); + #endif + } + printf("\nDone\n"); + return 0; +} + + + +/****************************************************************************** + * PCI Bridge Registers Dump +*******************************************************************************/ +static void display_pci_regs(void) +{ + printf(" PCI9056_SPACE0_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_RANGE)); + printf(" PCI9056_SPACE0_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_REMAP)); + printf(" PCI9056_LOCAL_DMA_ARBIT %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_DMA_ARBIT)); + printf(" PCI9056_ENDIAN_DESC %08lX\n",PCICFG_GET_REG(PCI9056_ENDIAN_DESC)); + printf(" PCI9056_EXP_ROM_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_RANGE)); + printf(" PCI9056_EXP_ROM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_REMAP)); + printf(" PCI9056_SPACE0_ROM_DESC %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_ROM_DESC)); + printf(" PCI9056_DM_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_DM_RANGE)); + printf(" PCI9056_DM_MEM_BASE %08lX\n",PCICFG_GET_REG(PCI9056_DM_MEM_BASE)); + printf(" PCI9056_DM_IO_BASE %08lX\n",PCICFG_GET_REG(PCI9056_DM_IO_BASE)); + printf(" PCI9056_DM_PCI_MEM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_MEM_REMAP)); + printf(" PCI9056_DM_PCI_IO_CONFIG %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_IO_CONFIG)); + printf(" PCI9056_SPACE1_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_RANGE)); + printf(" PCI9056_SPACE1_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_REMAP)); + printf(" PCI9056_SPACE1_DESC %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_DESC)); + printf(" PCI9056_DM_DAC %08lX\n",PCICFG_GET_REG(PCI9056_DM_DAC)); + printf(" PCI9056_MAILBOX0 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX0)); + printf(" PCI9056_MAILBOX1 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX1)); + printf(" PCI9056_MAILBOX2 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX2)); + printf(" PCI9056_MAILBOX3 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX3)); + printf(" PCI9056_MAILBOX4 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX4)); + printf(" PCI9056_MAILBOX5 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX5)); + printf(" PCI9056_MAILBOX6 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX6)); + printf(" PCI9056_MAILBOX7 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX7)); + printf(" PCI9056_PCI_TO_LOC_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_PCI_TO_LOC_DBELL)); + printf(" PCI9056_LOC_TO_PCI_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_LOC_TO_PCI_DBELL)); + printf(" PCI9056_INT_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_INT_CTRL_STAT)); + printf(" PCI9056_EEPROM_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT)); + printf(" PCI9056_PERM_VENDOR_ID %08lX\n",PCICFG_GET_REG(PCI9056_PERM_VENDOR_ID)); + printf(" PCI9056_REVISION_ID %08lX\n",PCICFG_GET_REG(PCI9056_REVISION_ID)); + printf(" \n"); + printf(" PCI9056_VENDOR_ID %08lX\n",PCICFG_GET_REG(PCI9056_VENDOR_ID)); + printf(" PCI9056_COMMAND %08lX\n",PCICFG_GET_REG(PCI9056_COMMAND)); + printf(" PCI9056_REVISION %08lX\n",PCICFG_GET_REG(PCI9056_REVISION)); + printf(" PCI9056_CACHE_SIZE %08lX\n",PCICFG_GET_REG(PCI9056_CACHE_SIZE)); + printf(" PCI9056_RTR_BASE %08lX\n",PCICFG_GET_REG(PCI9056_RTR_BASE)); + printf(" PCI9056_RTR_IO_BASE %08lX\n",PCICFG_GET_REG(PCI9056_RTR_IO_BASE)); + printf(" PCI9056_LOCAL_BASE0 %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE0)); + printf(" PCI9056_LOCAL_BASE1 %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE1)); + printf(" PCI9056_UNUSED_BASE1 %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE1)); + printf(" PCI9056_UNUSED_BASE2 %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE2)); + printf(" PCI9056_CIS_PTR %08lX\n",PCICFG_GET_REG(PCI9056_CIS_PTR)); + printf(" PCI9056_SUB_ID %08lX\n",PCICFG_GET_REG(PCI9056_SUB_ID)); + printf(" PCI9056_EXP_ROM_BASE %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_BASE)); + printf(" PCI9056_CAP_PTR %08lX\n",PCICFG_GET_REG(PCI9056_CAP_PTR)); + printf(" PCI9056_INT_LINE %08lX\n",PCICFG_GET_REG(PCI9056_INT_LINE)); + printf(" PCI9056_PM_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_PM_CAP_ID)); + printf(" PCI9056_PM_CSR %08lX\n",PCICFG_GET_REG(PCI9056_PM_CSR)); + printf(" PCI9056_HS_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_HS_CAP_ID)); + printf(" PCI9056_VPD_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_VPD_CAP_ID)); + printf(" PCI9056_VPD_DATA %08lX\n",PCICFG_GET_REG(PCI9056_VPD_DATA)); +} + + +int do_pati(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (strcmp(argv[1], "info") == 0) + { + show_pld_regs(); + return 0; + } + if (strcmp(argv[1], "pci") == 0) + { + display_pci_regs(); + return 0; + } + if (strcmp(argv[1], "led") == 0) + { + int led_nr,led_on; + led_nr = (int)simple_strtoul(argv[2], NULL, 10); + led_on = (int)simple_strtoul(argv[3], NULL, 10); + if(!led_nr) + user_led0(led_on); + else + user_led1(led_on); + return 0; + } +#if defined(CFG_PCI_CON_DEVICE) + if (strcmp(argv[1], "con") == 0) { + pci_con_connect(); + return 0; + } + if (strcmp(argv[1], "disc") == 0) { + pci_con_disc(); + return 0; + } +#endif + if (strcmp(argv[1], "eeprom") == 0) { + unsigned long addr; + int size, offset; + offset = 0; + size = PATI_EEPROM_LAST_OFFSET; + if(argc>2) { + if(argc>3) { + addr = simple_strtoul(argv[3], NULL, 16); + if(argc>4) + offset = (int) simple_strtoul(argv[4], NULL, 16); + if(argc>5) + size = (int) simple_strtoul(argv[5], NULL, 16); + if (strcmp(argv[2], "read") == 0) { + return (pati_pci_eeprom_read(offset, addr, size)); + } + if (strcmp(argv[2], "write") == 0) { + return (pati_pci_eeprom_write(offset, addr, size)); + } + } + if (strcmp(argv[2], "prg") == 0) { + return (pati_pci_eeprom_prg()); + } + if (strcmp(argv[2], "era") == 0) { + return (pati_pci_eeprom_erase()); + } + if (strcmp(argv[2], "reload") == 0) { + reload_pci_eeprom(); + return 0; + } + + + } + } + + return (do_mplcommon(cmdtp, flag, argc, argv)); +} + +U_BOOT_CMD( + pati, 8, 1, do_pati, + "pati - PATI specific Cmds\n", + "info - displays board information\n" + "pati pci - displays PCI registers\n" + "pati led \n" + " - switch LED \n" + "pati flash mem [SrcAddr]\n" + " - updates U-Boot with image in memory\n" + "pati eeprom - PCI EEPROM sub-system\n" + " read \n" + " - read PCI EEPROM to from words\n" + " write \n" + " - write PCI EEPROM from to words\n" + " prg - programm PCI EEPROM with default values\n" + " era - erase PCI EEPROM (write all word to 0xffff)\n" + " reload- Reload PCI Bridge with EEPROM Values\n" + " NOTE: must start on word boundary\n" + " and must be even byte values\n" +); + +/* ------------------------------------------------------------------------- */ diff --git a/board/mpl/pati/config.mk b/board/mpl/pati/config.mk new file mode 100644 index 000000000..b8a098591 --- /dev/null +++ b/board/mpl/pati/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2003 +# Martin Winistoerfer, martinwinistoerfer@gmx.ch. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# EPQ Board Configuration +# + +# Boot from flash at location 0x00000000 +TEXT_BASE = 0xFFF00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c new file mode 100644 index 000000000..0355b65b8 --- /dev/null +++ b/board/mpl/pati/pati.c @@ -0,0 +1,618 @@ +/* + * (C) Copyright 2003 + * Martin Winistoerfer, martinwinistoerfer@gmx.ch. + * Atapted for PATI + * Denis Peter, d.peter@mpl.ch + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/*********************************************************************************** + * Bits for the SDRAM controller + * ----------------------------- + * + * CAL: CAS Latency. If cleared to 0 (default) the SDRAM controller asserts TA# on + * the 2nd Clock after ACTIVE command (CAS Latency = 2). If set to 1 the SDRAM + * controller asserts TA# on the 3rd Clock after ACTIVE command (CAS Latency = 3). + * RCD: RCD ACTIVE to READ or WRITE Delay (Ras to Cas Delay). If cleared 0 (default) + * tRCD of the SDRAM must equal or less 25ns. If set to 1 tRCD must be equal or less 50ns. + * WREC:Write Recovery. If cleared 0 (default) tWR of the SDRAM must equal or less 25ns. + * If set to 1 tWR must be equal or less 50ns. + * RP: Precharge Command Time. If cleared 0 (default) tRP of the SDRAM must equal or less + * 25ns. If set to 1 tRP must be equal or less 50ns. + * RC: Auto Refresh to Active Time. If cleared 0 (default) tRC of the SDRAM must equal + * or less 75ns. If set to 1 tRC must be equal or less 100ns. + * LMR: Bit to set the Mode Register of the SDRAM. If set, the next access to the SDRAM + * is the Load Mode Register Command. + * IIP: Init in progress. Set to 1 for starting the init sequence + * (Precharge All). As long this bit is set, the Precharge All is still in progress. + * After command has completed, wait at least for 8 refresh (200usec) before proceed. + **********************************************************************************/ + +#include +#include +#include +#include +#define PLX9056_LOC +#include "plx9056.h" +#include "pati.h" + +#if defined(__APPLE__) +/* Leading underscore on symbols */ +# define SYM_CHAR "_" +#else /* No leading character on symbols */ +# define SYM_CHAR +#endif + +#undef SDRAM_DEBUG +/* + * Macros to generate global absolutes. + */ +#define GEN_SYMNAME(str) SYM_CHAR #str +#define GEN_VALUE(str) #str +#define GEN_ABS(name, value) \ + asm (".globl " GEN_SYMNAME(name)); \ + asm (GEN_SYMNAME(name) " = " GEN_VALUE(value)) + + +/************************************************************************ + * Early debug routines + */ +void write_hex (unsigned char i) +{ + char cc; + + cc = i >> 4; + cc &= 0xf; + if (cc > 9) + serial_putc (cc + 55); + else + serial_putc (cc + 48); + cc = i & 0xf; + if (cc > 9) + serial_putc (cc + 55); + else + serial_putc (cc + 48); +} + +#if defined(SDRAM_DEBUG) + +void write_4hex (unsigned long val) +{ + write_hex ((unsigned char) (val >> 24)); + write_hex ((unsigned char) (val >> 16)); + write_hex ((unsigned char) (val >> 8)); + write_hex ((unsigned char) val); +} + +#endif + +unsigned long in32(unsigned long addr) +{ + unsigned long *p=(unsigned long *)addr; + return *p; +} + +void out32(unsigned long addr,unsigned long data) +{ + unsigned long *p=(unsigned long *)addr; + *p=data; +} + +typedef struct { + unsigned short boardtype; /* Board revision and Population Options */ + unsigned char cal; /* cas Latency 0:CAL=2 1:CAL=3 */ + unsigned char rcd; /* ras to cas delay 0:<25ns 1:<50ns*/ + unsigned char wrec; /* write recovery 0:<25ns 1:<50ns */ + unsigned char pr; /* Precharge Command Time 0:<25ns 1:<50ns */ + unsigned char rc; /* Auto Refresh to Active Time 0:<75ns 1:<100ns */ + unsigned char sz; /* log binary => Size = (4MByte< Size 2 = 16MByte, 1=8 */ + }, + { 0xffff, /* terminator */ + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff } +}; + + +extern int mem_test (unsigned long start, unsigned long ramsize, int quiet); +extern void mem_test_reloc(void); + +/* + * Get RAM size. + */ +long int initdram(int board_type) +{ + unsigned char board_rev; + unsigned long reg; + unsigned long lmr; + int i,timeout; + +#if defined(SDRAM_DEBUG) + reg=in32(PLD_CONFIG_BASE+PLD_PART_ID); + puts("\n\nSYSTEM part 0x"); write_4hex(SYSCNTR_PART(reg)); + puts(" Vers 0x"); write_4hex(SYSCNTR_ID(reg)); + puts("\nSDRAM part 0x"); write_4hex(SDRAM_PART(reg)); + puts(" Vers 0x"); write_4hex(SDRAM_ID(reg)); + reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); + puts("\nBoard rev. 0x"); write_4hex(SYSCNTR_BREV(reg)); + putc('\n'); +#endif + reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); + board_rev=(unsigned char)(SYSCNTR_BREV(reg)); + i=0; + while(1) { + if(sdram_table[i].boardtype==0xffff) { + puts("ERROR, found no table for Board 0x"); + write_hex(board_rev); + while(1); + } + if(sdram_table[i].boardtype==(unsigned char)board_rev) + break; + i++; + } + /* Set CAL, RCD, WREQ, PR and RC Bits */ +#if defined(SDRAM_DEBUG) + puts("Set CAL, RCD, WREQ, PR and RC Bits\n"); +#endif + /* mask bits */ + reg &= ~(SET_REG_BIT(1,SDRAM_CAL) | SET_REG_BIT(1,SDRAM_RCD) | SET_REG_BIT(1,SDRAM_WREQ) | + SET_REG_BIT(1,SDRAM_PR) | SET_REG_BIT(1,SDRAM_RC) | SET_REG_BIT(1,SDRAM_LMR) | + SET_REG_BIT(1,SDRAM_IIP) | SET_REG_BIT(1,SDRAM_RES0)); + /* set bits */ + reg |= (SET_REG_BIT(sdram_table[i].cal,SDRAM_CAL) | + SET_REG_BIT(sdram_table[i].rcd,SDRAM_RCD) | + SET_REG_BIT(sdram_table[i].wrec,SDRAM_WREQ) | + SET_REG_BIT(sdram_table[i].pr,SDRAM_PR) | + SET_REG_BIT(sdram_table[i].rc,SDRAM_RC)); + + out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg); + /* step 2 set IIP */ +#if defined(SDRAM_DEBUG) + puts("step 2 set IIP\n"); +#endif + /* step 2 set IIP */ + reg |= SET_REG_BIT(1,SDRAM_IIP); + timeout=0; + while (timeout!=0xffff) { + __asm__ volatile("eieio"); + reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); + if((reg & SET_REG_BIT(1,SDRAM_IIP))==0) + break; + timeout++; + udelay(1); + } + /* wait for at least 8 refresh */ + udelay(1000); + /* set LMR */ + reg |= SET_REG_BIT(1,SDRAM_LMR); + out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg); + __asm__ volatile("eieio"); + lmr=0x00000002; /* sequential burst 4 data */ + if(sdram_table[i].cal==1) + lmr|=0x00000030; /* cal = 3 */ + else + lmr|=0000000020; /* cal = 2 */ + /* rest standard operation programmed write burst length */ + /* we have a x32 bit bus to the SDRAM, so shift the addr with 2 */ + lmr<<=2; + in32(CFG_SDRAM_BASE + lmr); + /* ok, we're done, return SDRAM size */ + return ((0x400000 << sdram_table[i].sz)); /* log2 value of 4MByte */ +} + + +void set_flash_vpp(int ext_vpp, int ext_wp, int int_vpp) +{ + unsigned long reg; + reg=in32(PLD_CONF_REG2+PLD_CONFIG_BASE); + reg &= ~(SET_REG_BIT(1,SYSCNTR_CPU_VPP) | + SET_REG_BIT(1,SYSCNTR_FL_VPP) | + SET_REG_BIT(1,SYSCNTR_FL_WP)); + + reg |= (SET_REG_BIT(int_vpp,SYSCNTR_CPU_VPP) | + SET_REG_BIT(ext_vpp,SYSCNTR_FL_VPP) | + SET_REG_BIT(ext_wp,SYSCNTR_FL_WP)); + out32(PLD_CONF_REG2+PLD_CONFIG_BASE,reg); + udelay(100); +} + + +void show_pld_regs(void) +{ + unsigned long reg,reg1; + reg=in32(PLD_CONFIG_BASE+PLD_PART_ID); + printf("\nSYSTEM part %ld, Vers %ld\n",SYSCNTR_PART(reg),SYSCNTR_ID(reg)); + printf("SDRAM part %ld, Vers %ld\n",SDRAM_PART(reg),SDRAM_ID(reg)); + reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); + printf("Board rev. %c\n",(char) (SYSCNTR_BREV(reg)+'A')); + printf("Waitstates %ld\n",GET_SYSCNTR_FLWAIT(reg)); + printf("SDRAM: CAL=%ld RCD=%ld WREQ=%ld PR=%ld\n RC=%ld LMR=%ld IIP=%ld\n", + GET_REG_BIT(reg,SDRAM_CAL),GET_REG_BIT(reg,SDRAM_RCD), + GET_REG_BIT(reg,SDRAM_WREQ),GET_REG_BIT(reg,SDRAM_PR), + GET_REG_BIT(reg,SDRAM_RC),GET_REG_BIT(reg,SDRAM_LMR), + GET_REG_BIT(reg,SDRAM_IIP)); + reg=in32(PLD_CONFIG_BASE+PLD_CONF_REG1); + reg1=in32(PLD_CONFIG_BASE+PLD_CONF_REG2); + printf("HW Config: FLAG=%ld IP=%ld index=%ld PRPM=%ld\n ICW=%ld ISB=%ld BDIS=%ld PCIM=%ld\n", + GET_REG_BIT(reg,SYSCNTR_FLAG),GET_REG_BIT(reg,SYSCNTR_IP), + GET_SYSCNTR_BOOTIND(reg),GET_REG_BIT(reg,SYSCNTR_PRM), + GET_REG_BIT(reg,SYSCNTR_ICW),GET_SYSCNTR_ISB(reg), + GET_REG_BIT(reg1,SYSCNTR_BDIS),GET_REG_BIT(reg1,SYSCNTR_PCIM)); + printf("Switches: MUX=%ld PCI_DIS=%ld Boot_EN=%ld Config=%ld\n",GET_SDRAM_MUX(reg), + GET_REG_BIT(reg,SDRAM_PDIS),GET_REG_BIT(reg1,SYSCNTR_BOOTEN), + GET_SYSCNTR_CFG(reg1)); + printf("Misc: RIP=%ld CPU_VPP=%ld FLSH_VPP=%ld FLSH_WP=%ld\n\n", + GET_REG_BIT(reg,SDRAM_RIP),GET_REG_BIT(reg1,SYSCNTR_CPU_VPP), + GET_REG_BIT(reg1,SYSCNTR_FL_VPP),GET_REG_BIT(reg1,SYSCNTR_FL_WP)); +} + + +/**************************************************************** + * Setting IOs + * ----------- + * GPIO6 is User LED1 + * GPIO7 is Interrupt PLX (Output) + * GPIO5 is User LED0 + * GPIO2 is PLX USERi (Output) + * GPIO1 is PLX Interrupt (Input) + ****************************************************************/ + void init_ios(void) + { + volatile immap_t * immr = (immap_t *) CFG_IMMR; + volatile sysconf5xx_t *sysconf = &immr->im_siu_conf; + unsigned long reg; + reg=sysconf->sc_sgpiocr; /* Data direction register */ + reg &= ~0x67000000; + reg |= 0x27000000; /* set outpupts */ + sysconf->sc_sgpiocr=reg; /* Data direction register */ + reg=sysconf->sc_sgpiodt2; /* Data register */ + /* set output to 0 */ + reg &= ~0x27000000; + /* set IRQ and USERi to 1 */ + reg |= 0x28000000; + sysconf->sc_sgpiodt2=reg; /* Data register */ +} + +void user_led0(int led_on) +{ + volatile immap_t * immr = (immap_t *) CFG_IMMR; + volatile sysconf5xx_t *sysconf = &immr->im_siu_conf; + unsigned long reg; + reg=sysconf->sc_sgpiodt2; /* Data register */ + if(led_on) /* set output to 1 */ + reg |= 0x04000000; + else + reg &= ~0x04000000; + sysconf->sc_sgpiodt2=reg; /* Data register */ +} + +void user_led1(int led_on) +{ + volatile immap_t * immr = (immap_t *) CFG_IMMR; + volatile sysconf5xx_t *sysconf = &immr->im_siu_conf; + unsigned long reg; + reg=sysconf->sc_sgpiodt2; /* Data register */ + if(led_on) /* set output to 1 */ + reg |= 0x02000000; + else + reg &= ~0x02000000; + sysconf->sc_sgpiodt2=reg; /* Data register */ +} + + +/**************************************************************** + * Last Stage Init + ****************************************************************/ +int last_stage_init (void) +{ + mem_test_reloc(); + init_ios(); + return 0; +} + +/**************************************************************** + * Check the board + ****************************************************************/ + +#define BOARD_NAME "PATI" + +int checkboard (void) +{ + unsigned char s[50]; + unsigned long reg; + char rev; + int i; + + puts ("\nBoard: "); + reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); + rev=(char)(SYSCNTR_BREV(reg)+'A'); + i = getenv_r ("serial#", s, 32); + if ((i == -1)) { + puts ("### No HW ID - assuming " BOARD_NAME); + printf(" Rev. %c\n",rev); + } + else { + s[sizeof(BOARD_NAME)-1] = 0; + printf ("%s-1 Rev %c SN: %s\n", s,rev, + &s[sizeof(BOARD_NAME)]); + } + set_flash_vpp(1,0,0); /* set Flash VPP */ + return 0; +} + + +#ifdef CFG_PCI_CON_DEVICE +/************************************************************************ + * PCI Communication + * + * Alive (Pinging): + * ---------------- + * PCI Host sends message ALIVE, Local acknowledges with ALIVE + * + * PCI_CON console over PCI: + * ------------------------- + * Local side: + * - uses PCI9056_LOC_TO_PCI_DBELL register to signal that + * data is avaible (PCIMSG_CONN) + * - uses PCI9056_MAILBOX1 to send data + * - uses PCI9056_MAILBOX0 to receive data + * PCI side: + * - uses PCI9056_PCI_TO_LOC_DBELL register to signal that + * data is avaible (PCIMSG_CONN) + * - uses PCI9056_MAILBOX0 to send data + * - uses PCI9056_MAILBOX1 to receive data + * + * How it works: + * Send: + * - check if PCICON_TRANSMIT_REG is empty + * - write data or'ed with 0x80000000 into the PCICON_TRANSMIT_REG + * - write PCIMSG_CONN into the PCICON_DBELL_REG to signal a data + * is waiting + * Receive: + * - get an interrupt via the PCICON_ACK_REG register message + * PCIMSG_CONN + * - write the data from the PCICON_RECEIVE_REG into the receive + * buffer and if the receive buffer is not full, clear the + * PCICON_RECEIVE_REG (this allows the counterpart to write more data) + * - Clear the interrupt by writing 0xFFFFFFFF to the PCICON_ACK_REG + * + * The PCICON_RECEIVE_REG must be cleared by the routine which reads + * the receive buffer if the buffer is not full any more + * + */ + +#undef PCI_CON_DEBUG + +#ifdef PCI_CON_DEBUG +#define PCI_CON_PRINTF(fmt,args...) serial_printf (fmt ,##args) +#else +#define PCI_CON_PRINTF(fmt,args...) +#endif + + +/********************************************************* + * we work only with a receive buffer on eiter side. + * Transmit buffer is free, if mailbox is cleared. + * Transmit character is or'ed with 0x80000000 + * PATI receive register MAILBOX0 + * PATI transmit register MAILBOX1 + *********************************************************/ +#define PCICON_RECEIVE_REG PCI9056_MAILBOX0 +#define PCICON_TRANSMIT_REG PCI9056_MAILBOX1 +#define PCICON_DBELL_REG PCI9056_LOC_TO_PCI_DBELL +#define PCICON_ACK_REG PCI9056_PCI_TO_LOC_DBELL + + +#define PCIMSG_ALIVE 0x1 +#define PCIMSG_CONN 0x2 +#define PCIMSG_DISC 0x3 +#define PCIMSG_CON_DATA 0x5 + + +#define PCICON_GET_REG(x) (in32(x + PCI_CONFIG_BASE)) +#define PCICON_SET_REG(x,y) (out32(x + PCI_CONFIG_BASE,y)) +#define PCICON_TX_FLAG 0x80000000 + + +#define REC_BUFFER_SIZE 0x100 +int recbuf[REC_BUFFER_SIZE]; +static int r_ptr = 0; +int w_ptr; +device_t pci_con_dev; +int conn=0; +int buff_full=0; + +void pci_con_put_it(const char c) +{ + /* Test for completition */ + unsigned long reg; + do { + reg=PCICON_GET_REG(PCICON_TRANSMIT_REG); + }while(reg); + reg=PCICON_TX_FLAG + c; + PCICON_SET_REG(PCICON_TRANSMIT_REG,reg); + PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_CON_DATA); +} + +void pci_con_putc(const char c) +{ + pci_con_put_it(c); + if(c == '\n') + pci_con_put_it('\r'); +} + + +int pci_con_getc(void) +{ + int res; + int diff; + while(r_ptr==(volatile int)w_ptr); + res=recbuf[r_ptr++]; + if(r_ptr==REC_BUFFER_SIZE) + r_ptr=0; + if(w_ptr(REC_BUFFER_SIZE-4)) + buff_full=1; + else + /* clear Mail box */ + PCICON_SET_REG(PCICON_RECEIVE_REG,0L); + break; + default: + serial_printf(" PCI9056_PCI_TO_LOC_DBELL = %08lX\n",reg); + } + /* clear IRQ */ + PCICON_SET_REG(PCICON_ACK_REG,~0L); + } + return 0; +} + +void pci_con_connect(void) +{ + unsigned long reg; + conn=0; + reg=PCICON_GET_REG(PCI9056_INT_CTRL_STAT); + /* default 0x0f010180 */ + reg &= 0xff000000; + reg |= 0x00030000; /* enable local dorbell */ + reg |= 0x00000300; /* enable PCI dorbell */ + PCICON_SET_REG(PCI9056_INT_CTRL_STAT , reg); + irq_install_handler (0x2, (interrupt_handler_t *) pci_dorbell_irq,NULL); + memset (&pci_con_dev, 0, sizeof (pci_con_dev)); + strcpy (pci_con_dev.name, "pci_con"); + pci_con_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + pci_con_dev.putc = pci_con_putc; + pci_con_dev.puts = pci_con_puts; + pci_con_dev.getc = pci_con_getc; + pci_con_dev.tstc = pci_con_tstc; + device_register (&pci_con_dev); + printf("PATI ready for PCI connection, type ctrl-c for exit\n"); + do { + udelay(10); + if((volatile int)conn) + break; + if(ctrlc()) { + irq_free_handler(0x2); + return; + } + }while(1); + console_assign(stdin,"pci_con"); + console_assign(stderr,"pci_con"); + console_assign(stdout,"pci_con"); +} + +void pci_con_disc(void) +{ + console_assign(stdin,"serial"); + console_assign(stderr,"serial"); + console_assign(stdout,"serial"); + PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_DISC); + /* reconnection */ + irq_free_handler(0x02); + pci_con_connect(); +} +#endif /* #ifdef CFG_PCI_CON_DEVICE */ + +/* + * Absolute environment address for linker file. + */ +GEN_ABS(env_start, CFG_ENV_OFFSET + CFG_FLASH_BASE); diff --git a/board/mpl/pati/pati.h b/board/mpl/pati/pati.h new file mode 100644 index 000000000..d5217724d --- /dev/null +++ b/board/mpl/pati/pati.h @@ -0,0 +1,440 @@ +/* + * (C) Copyright 2003 + * Denis Peter, d.peter@mpl.ch + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/************************************************************************ + * MACROS and register definitions for PATI Registers + ************************************************************************/ +#ifndef __PATI_H_ +#define __PATI_H_ 1 + +#define PLD_PART_ID 0x0 +#define PLD_BOARD_TIMING 0x4 +#define PLD_CONF_REG1 0x8 +#define PLD_CONF_REG2 0xC +#define PLD_CONF_RES 0x10 + +#define SET_REG_BIT(y,x) (y<<(31-x)) +#define GET_REG_BIT(y,x) ((y>>(31-x)) & 0x1L) + +/* SDRAM Controller PLD_PART_ID */ +/* 9 10 11 12 13 14 19 31 */ +#define SDRAM_PART3 9 +#define SDRAM_PART2 10 +#define SDRAM_PART1 11 +#define SDRAM_PART0 12 +#define SDRAM_ID3 13 +#define SDRAM_ID2 14 +#define SDRAM_ID1 19 +#define SDRAM_ID0 31 + +#define SDRAM_PART(x) ( \ + (GET_REG_BIT(x,SDRAM_PART3)<<3) |\ + (GET_REG_BIT(x,SDRAM_PART2)<<2) |\ + (GET_REG_BIT(x,SDRAM_PART1)<<1) |\ + (GET_REG_BIT(x,SDRAM_PART0))) + +#define SDRAM_ID(x) ( \ + (GET_REG_BIT(x,SDRAM_ID3)<<3) |\ + (GET_REG_BIT(x,SDRAM_ID2)<<2) |\ + (GET_REG_BIT(x,SDRAM_ID1)<<1) |\ + (GET_REG_BIT(x,SDRAM_ID0))) + +/* System Controller */ +/* 0 1 3 4 5 16 20 28 29 30 */ +#define SYSCNTR_PART4 0 +#define SYSCNTR_PART3 1 +#define SYSCNTR_PART2 3 +#define SYSCNTR_PART1 4 +#define SYSCNTR_PART0 5 +#define SYSCNTR_ID4 16 +#define SYSCNTR_ID3 20 +#define SYSCNTR_ID2 28 +#define SYSCNTR_ID1 29 +#define SYSCNTR_ID0 30 + +#define SYSCNTR_PART(x) ( \ + (GET_REG_BIT(x,SYSCNTR_PART4)<<4) |\ + (GET_REG_BIT(x,SYSCNTR_PART3)<<3) |\ + (GET_REG_BIT(x,SYSCNTR_PART2)<<2) |\ + (GET_REG_BIT(x,SYSCNTR_PART1)<<1) |\ + (GET_REG_BIT(x,SYSCNTR_PART0))) + +#define SYSCNTR_ID(x) ( \ + (GET_REG_BIT(x,SYSCNTR_ID4)<<4) |\ + (GET_REG_BIT(x,SYSCNTR_ID3)<<3) |\ + (GET_REG_BIT(x,SYSCNTR_ID2)<<2) |\ + (GET_REG_BIT(x,SYSCNTR_ID1)<<1) |\ + (GET_REG_BIT(x,SYSCNTR_ID0))) + +/* SDRAM Controller PLD_BOARD_TIMING */ +/* 9 10 11 12 13 14 19 31 */ +#define SDRAM_CAL 9 +#define SDRAM_RCD 10 +#define SDRAM_WREQ 11 +#define SDRAM_PR 12 +#define SDRAM_RC 13 +#define SDRAM_LMR 14 +#define SDRAM_IIP 19 +#define SDRAM_RES0 31 +/* System Controller */ +/* 0 1 3 4 5 16 20 28 29 30 */ +#define SYSCNTR_BREV0 0 +#define SYSCNTR_BREV1 1 +#define SYSCNTR_BREV2 3 +#define SYSCNTR_BREV3 4 +#define SYSCNTR_RES0 5 +#define SYSCNTR_RES1 16 +#define SYSCNTR_RES2 20 +#define SYSCNTR_FLWAIT2 28 +#define SYSCNTR_FLWAIT1 29 +#define SYSCNTR_FLWAIT0 30 + +#define SYSCNTR_BREV(x) ( \ + (GET_REG_BIT(x,SYSCNTR_BREV3)<<3) |\ + (GET_REG_BIT(x,SYSCNTR_BREV2)<<2) |\ + (GET_REG_BIT(x,SYSCNTR_BREV1)<<1) |\ + (GET_REG_BIT(x,SYSCNTR_BREV0))) + +#define GET_SYSCNTR_FLWAIT(x) ( \ + (GET_REG_BIT(x,SYSCNTR_FLWAIT2)<<2) |\ + (GET_REG_BIT(x,SYSCNTR_FLWAIT1)<<1) |\ + (GET_REG_BIT(x,SYSCNTR_FLWAIT0))) + +#define SET_SYSCNTR_FLWAIT(x) ( \ + (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_FLWAIT2)) |\ + (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_FLWAIT1)) |\ + (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_FLWAIT0))) + +/* SDRAM Controller REG 2*/ +/* 9 10 11 12 13 14 19 31 */ +#define SDRAM_MUX0 9 +#define SDRAM_MUX1 10 +#define SDRAM_PDIS 11 +#define SDRAM_RES1 12 +#define SDRAM_RES2 13 +#define SDRAM_RES3 14 +#define SDRAM_RES4 19 +#define SDRAM_RIP 31 + +#define GET_SDRAM_MUX(x) ( \ + (GET_REG_BIT(x,SDRAM_MUX1)<<1)| \ + (GET_REG_BIT(x,SDRAM_MUX0))) + + +/* System Controller */ +/* 0 1 3 4 5 16 20 28 29 30 */ +#define SYSCNTR_FLAG 0 +#define SYSCNTR_IP 1 +#define SYSCNTR_BIND2 3 +#define SYSCNTR_BIND1 4 +#define SYSCNTR_BIND0 5 +#define SYSCNTR_PRM 16 +#define SYSCNTR_ICW 20 +#define SYSCNTR_ISB2 28 +#define SYSCNTR_ISB1 29 +#define SYSCNTR_ISB0 30 + +#define GET_SYSCNTR_BOOTIND(x) ( \ + (GET_REG_BIT(x,SYSCNTR_BIND2)<<2) |\ + (GET_REG_BIT(x,SYSCNTR_BIND1)<<1) |\ + (GET_REG_BIT(x,SYSCNTR_BIND0))) + +#define SET_SYSCNTR_BOOTIND(x) ( \ + (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_BIND2)) |\ + (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_BIND1))| \ + (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_BIND0))) + +#define GET_SYSCNTR_ISB(x) ( \ + (GET_REG_BIT(x,SYSCNTR_ISB2)<<2)| \ + (GET_REG_BIT(x,SYSCNTR_ISB1)<<1)| \ + (GET_REG_BIT(x,SYSCNTR_ISB0))) + +#define SET_SYSCNTR_ISB(x) ( \ + (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_ISB2))| \ + (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_ISB))| \ + (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_ISB0))) + +/* SDRAM Controller REG 3*/ +/* 9 10 11 12 13 14 19 31 */ +#define SDRAM_RES5 9 +#define SDRAM_CFG1 10 +#define SDRAM_CFG2 11 +#define SDRAM_CFG3 12 +#define SDRAM_RES6 13 +#define SDRAM_CFG5 14 +#define SDRAM_CFG6 19 +#define SDRAM_RES7 31 + +#define GET_SDRAM_CFG(x) ( \ + (GET_REG_BIT(x,SDRAM_CFG6)<<4) |\ + (GET_REG_BIT(x,SDRAM_CFG5)<<3) |\ + (GET_REG_BIT(x,SDRAM_CFG3)<<2) |\ + (GET_REG_BIT(x,SDRAM_CFG2)<<1) |\ + (GET_REG_BIT(x,SDRAM_CFG1))) + +/* System Controller */ +/* 0 1 3 4 5 16 20 28 29 30 */ +#define SYSCNTR_BDIS 0 +#define SYSCNTR_PCIM 1 +#define SYSCNTR_CFG0 3 +#define SYSCNTR_CFG1 4 +#define SYSCNTR_CFG2 5 +#define SYSCNTR_CFG3 16 +#define SYSCNTR_BOOTEN 20 +#define SYSCNTR_CPU_VPP 28 +#define SYSCNTR_FL_VPP 29 +#define SYSCNTR_FL_WP 30 + +#define GET_SYSCNTR_CFG(x) ( \ + (GET_REG_BIT(x,SYSCNTR_CFG3)<<3)| \ + (GET_REG_BIT(x,SYSCNTR_CFG2)<<2)| \ + (GET_REG_BIT(x,SYSCNTR_CFG1)<<1)| \ + (GET_REG_BIT(x,SYSCNTR_CFG0))) + + +/*************************************************************** + * MISC Defines + ***************************************************************/ + +#define PCI_VENDOR_ID_MPL 0x18E6 +#define PCI_DEVICE_ID_PATI 0x00DA + +#if defined(CONFIG_MIP405) +#define PATI_FIRMWARE_START_OFFSET 0x00300000 +#define PATI_ISO_STRING "MEV-10084-001" +#endif + +#define PATI_ENDIAN_MODE 0x3E + +/******************************************* + * PATI Mapping: + * ------------- + * PCI Map: + * ------- + * All addreses are mapped into the memory area + * (IO Area on some areas may also be possible) + * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes + * - pci_space0_addr: configurable + * - pci_space1_addr configurable + * + * Local Map: + * ---------- + * Local addresses (Remap) + * - SDRAM 0x06000000 Size 16MByte mask 0xff000000 + * - EPLD CFG 0x07000000 Size 512Bytes + * - FLASH 0x03000000 Size up to 8MByte + * - CPU 0x01000000 Size 4MByte (only accessable if special configured) + * + * Implemention: + * ------------- + * To prevent using large resources reservation on the host following + * PCI mapping is choosed: + * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes + * - pci_space0_addr: configured to the EPLD Config Area size 256Bytes + * - pci_space1_addr: configured to the SDRAM Area size 1MBytes, this + * space is used to switch between SDRAM, Flash and CPU + * + */ + +/* Attribute definitions */ +#define PATI_BUS_SIZE_8 0 +#define PATI_BUS_SIZE_16 1 +#define PATI_BUS_SIZE_32 3 + +#define PATI_SPACE0_MASK (0xFEFFFE00) /* Mask Attributes */ +#define PATI_SPACE1_MASK (0x00000000) /* Mask Attributes */ + +#define PATI_EXTRA_LONG_EEPROM 1 + +#define SPACE0_TA_ENABLE (1<<6) +#define SPACE1_TA_ENABLE (1<<6) + +/* Config Area */ +#define PATI_LOC_CFG_ADDR 0x07000000 /* Local Address */ +#define PATI_LOC_CFG_MASK 0xFFFFFF00 /* 256 Bytes */ +/* Attributes */ +#define PATI_LOC_CFG_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */ +#define PATI_LOC_CFG_BURST 0 /* No Burst */ +#define PATI_LOC_CFG_NO_PREFETCH 1 /* No Prefetch */ +#define PATI_LOC_CFG_TA_ENABLE 1 /* Enable TA */ + +#define PATI_LOC_CFG_SPACE0_ATTR ( \ + PATI_LOC_CFG_BUS_SIZE | \ + (PATI_LOC_CFG_TA_ENABLE << 6) | \ + (PATI_LOC_CFG_NO_PREFETCH << 8) | \ + (PATI_LOC_CFG_BURST << 24) | \ + (PATI_EXTRA_LONG_EEPROM << 25)) + +/* should never be used */ +#define PATI_LOC_CFG_SPACE1_ATTR ( \ + PATI_LOC_CFG_BUS_SIZE | \ + (PATI_LOC_CFG_TA_ENABLE << 6) | \ + (PATI_LOC_CFG_NO_PREFETCH << 9) | \ + (PATI_LOC_CFG_BURST << 8)) + + +/* SDRAM Area */ +#define PATI_LOC_SDRAM_ADDR 0x06000000 /* Local Address */ +#define PATI_LOC_SDRAM_MASK 0xFFF00000 /* 1MByte */ +/* Attributes */ +#define PATI_LOC_SDRAM_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */ +#define PATI_LOC_SDRAM_BURST 0 /* No Burst */ +#define PATI_LOC_SDRAM_NO_PREFETCH 0 /* Prefetch */ +#define PATI_LOC_SDRAM_TA_ENABLE 1 /* Enable TA */ + +/* should never be used */ +#define PATI_LOC_SDRAM_SPACE0_ATTR ( \ + PATI_LOC_SDRAM_BUS_SIZE | \ + (PATI_LOC_SDRAM_TA_ENABLE << 6) | \ + (PATI_LOC_SDRAM_NO_PREFETCH << 8) | \ + (PATI_LOC_SDRAM_BURST << 24) | \ + (PATI_EXTRA_LONG_EEPROM << 25)) + +#define PATI_LOC_SDRAM_SPACE1_ATTR ( \ + PATI_LOC_SDRAM_BUS_SIZE | \ + (PATI_LOC_SDRAM_TA_ENABLE << 6) | \ + (PATI_LOC_SDRAM_NO_PREFETCH << 9) | \ + (PATI_LOC_SDRAM_BURST << 8)) + + +/* Flash Area */ +#define PATI_LOC_FLASH_ADDR 0x03000000 /* Local Address */ +#define PATI_LOC_FLASH_MASK 0xFFF00000 /* 1MByte */ +/* Attributes */ +#define PATI_LOC_FLASH_BUS_SIZE PATI_BUS_SIZE_16 /* 16 Bit */ +#define PATI_LOC_FLASH_BURST 0 /* No Burst */ +#define PATI_LOC_FLASH_NO_PREFETCH 1 /* No Prefetch */ +#define PATI_LOC_FLASH_TA_ENABLE 1 /* Enable TA */ + +/* should never be used */ +#define PATI_LOC_FLASH_SPACE0_ATTR ( \ + PATI_LOC_FLASH_BUS_SIZE | \ + (PATI_LOC_FLASH_TA_ENABLE << 6) | \ + (PATI_LOC_FLASH_NO_PREFETCH << 8) | \ + (PATI_LOC_FLASH_BURST << 24) | \ + (PATI_EXTRA_LONG_EEPROM << 25)) + +#define PATI_LOC_FLASH_SPACE1_ATTR ( \ + PATI_LOC_FLASH_BUS_SIZE | \ + (PATI_LOC_FLASH_TA_ENABLE << 6) | \ + (PATI_LOC_FLASH_NO_PREFETCH << 9) | \ + (PATI_LOC_FLASH_BURST << 8)) + + +/* CPU Area */ +#define PATI_LOC_CPU_ADDR 0x01000000 /* Local Address */ +#define PATI_LOC_CPU_MASK 0xFFF00000 /* 1Mbyte */ +/* Attributes */ +#define PATI_LOC_CPU_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */ +#define PATI_LOC_CPU_BURST 0 /* No Burst */ +#define PATI_LOC_CPU_NO_PREFETCH 1 /* No Prefetch */ +#define PATI_LOC_CPU_TA_ENABLE 1 /* Enable TA */ + +/* should never be used */ +#define PATI_LOC_CPU_SPACE0_ATTR ( \ + PATI_LOC_CPU_BUS_SIZE | \ + (PATI_LOC_CPU_TA_ENABLE << 6) | \ + (PATI_LOC_CPU_NO_PREFETCH << 8) | \ + (PATI_LOC_CPU_BURST << 24) | \ + (PATI_EXTRA_CPU_EEPROM << 25)) + +#define PATI_LOC_CPU_SPACE1_ATTR ( \ + PATI_LOC_CPU_BUS_SIZE | \ + (PATI_LOC_CPU_TA_ENABLE << 6) | \ + (PATI_LOC_CPU_NO_PREFETCH << 9) | \ + (PATI_LOC_CPU_BURST << 8)) + +/*************************************************** + * Hardware Config word definition + ***************************************************/ +#define BOOT_EXT_FLASH 0x00000000 +#define BOOT_INT_FLASH 0x00000004 +#define BOOT_FROM_PCI 0x00000006 +#define BOOT_FROM_SDRAM 0x00000005 + +#define ENABLE_INT_ARB 0x00000008 + +#define INITIAL_IRQ_PREF 0x00000010 + +#define INITIAL_MEM_0M 0x00000000 +#define INITIAL_MEM_4M 0x00000080 +#define INITIAL_MEM_8M 0x00000040 +#define INITIAL_MEM_12M 0x000000C0 +#define INITIAL_MEM_16M 0x00000020 +#define INITIAL_MEM_20M 0x000000A0 +#define INITIAL_MEM_24M 0x00000060 +#define INITIAL_MEM_28M 0x000000E0 +/* CONF */ +#define INTERNAL_HWCONF 0x00000100 +/* PRPM */ +#define LOCAL_CPU_SLAVE 0x00000200 +/* BDIS */ +#define DISABLE_MEM_CNTR 0x00000400 +/* PCIM */ +#define PCI_MASTER_ONLY 0x00000800 + + +#define PATI_HW_START ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF)) +#define PATI_HW_PCI_ONLY ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY)) +#define PATI_HW_CPU_ACC ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY)) +#define PATI_HW_CPU_SLAVE ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY | LOCAL_CPU_SLAVE)) + +/*************************************************** + * Direct Master Config + ***************************************************/ +#define PATI_DMASTER_PCI_ADDR 0x01000000 +#define PATI_BUS_MASTER 1 + + +#define PATI_DMASTER_MASK 0xFFF00000 /* 1MByte */ +#define PATI_DMASTER_ADDR 0x01000000 /* Local Address */ + +#define PATI_DMASTER_MEMORY_EN 0x00000001 /* 0x00000001 */ +#define PATI_DMASTER_READ_AHEAD 0x00000004 /* 0x00000004 */ +#define PATI_DMASTER_READ_NOT_AHEAD 0x00000000 /* 0x00000004 */ +#define PATI_DMASTER_PRE_SIZE_CNTRL_0 0x00000000 +#define PATI_DMASTER_PRE_SIZE_CNTRL_4 0x00000008 +#define PATI_DMASTER_PRE_SIZE_CNTRL_8 0x00001000 +#define PATI_DMASTER_PRE_SIZE_CNTRL_16 0x00001008 +#define PATI_DMASTER_REL_PCI 0x00000000 +#define PATI_DMASTER_NOT_REL_PCI 0x00000010 +#define PATI_DMASTER_WR_INVAL 0x00000200 +#define PATI_DMASTER_NOT_WR_INVAL 0x00000000 +#define PATI_DMASTER_PRE_LIMIT 0x00000800 +#define PATI_DMASTER_PRE_CONT 0x00000000 +#define PATI_DMASTER_DELAY_WR_0 0x00000000 +#define PATI_DMASTER_DELAY_WR_4 0x00004000 +#define PATI_DMASTER_DELAY_WR_8 0x00008000 +#define PATI_DMASTER_DELAY_WR_16 0x0000C000 + +#define PATI_DMASTER_PCI_ADDR_MASK 0xFFFF0000 + +#define PATI_DMASTER_ATTR \ + PATI_DMASTER_MEMORY_EN | \ + PATI_DMASTER_READ_AHEAD | \ + PATI_DMASTER_PRE_SIZE_CNTRL_4 | \ + PATI_DMASTER_REL_PCI | \ + PATI_DMASTER_NOT_WR_INVAL | \ + PATI_DMASTER_PRE_LIMIT | \ + PATI_DMASTER_DELAY_WR_0 + + +#endif /* #ifndef __PATI_H_ */ diff --git a/board/mpl/pati/pci_eeprom.h b/board/mpl/pati/pci_eeprom.h new file mode 100644 index 000000000..96588089e --- /dev/null +++ b/board/mpl/pati/pci_eeprom.h @@ -0,0 +1,91 @@ + +#ifndef __PCI_EEPROM_H_ +#define __PCI_EEPROM_H_ 1 + +#include "pati.h" +/****************************************************************************** + * Eeprom Support + ******************************************************************************/ +/********************************************** +* Definitions +**********************************************/ +#define EE46_CMD_LEN 9 /* Bits in instructions */ +#define EE56_CMD_LEN 11 /* Bits in instructions */ +#define EE66_CMD_LEN 11 /* Bits in instructions */ +#define EE_READ 0x0180 /* 01 1000 0000 read instruction */ +#define EE_WRITE 0x0140 /* 01 0100 0000 write instruction */ +#define EE_WREN 0x0130 /* 01 0011 0000 write enable instruction */ +#define EE_WRALL 0x0110 /* 01 0001 0000 write all registers */ +#define EE_PRREAD 0x0180 /* 01 1000 0000 read address stored in Protect Register */ +#define EE_PRWRITE 0x0140 /* 01 0100 0000 write the address into PR */ +#define EE_WDS 0x0100 /* 01 0000 0000 write disable instruction */ +#define EE_PREN 0x0130 /* 01 0011 0000 protect enable instruction */ +#define EE_PRCLEAR 0x01FF /* 01 1111 1111 clear protect register instr */ +#define EE_PRDS 0x0100 /* 01 0000 0000 ONE TIME ONLY, permenant */ + +/*************************************************** + * EEPROM + ***************************************************/ +#define LOW_WORD(x) (((x) & 0xFFFF)) +#define HIGH_WORD(x) (((x) >> 16) & 0xFFFF) + +typedef struct pci_eeprom_t { + unsigned short offset; + unsigned short value; +} pci_eeprom; + +static pci_eeprom pati_eeprom[] = { + { 0x00,PCI_DEVICE_ID_PATI }, /* PCI Device ID PCIIDR[31:16] */ + { 0x02,PCI_VENDOR_ID_MPL }, /* PCI Vendor ID PCIIDR[15:0] */ + { 0x04,PCI_CLASS_PROCESSOR_POWERPC }, /* PCI Class Code PCICCR[23:8] */ + { 0x06,0x00BA }, /* PCI Class Code / PCI Revision ID PCICCR[7:0] / PCIREV[7:0] */ + { 0x08,0x0007 }, /* PCI Maximum Latency / PCI Minimum Grant PCIMLR[7:0] / PCIMGR[7:0] */ + { 0x0A,0x0100 }, /* PCI Interrupt Pin / PCI Interrupt Line PCIIPR[7:0] / PCIILR[7:0] */ + { 0x0C,0x0000 }, /* MSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[31:16] */ + { 0x0E,0x0000 }, /* LSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[15:0] */ + { 0x10,0x0000 }, /* MSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[31:16] */ + { 0x12,0x0000 }, /* LSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[15:0] */ + { 0x14,HIGH_WORD(PATI_LOC_CFG_MASK) }, /* MSW of Direct Slave Local Address Space 0 Range LAS0RR[31:16] */ + { 0x16,LOW_WORD(PATI_LOC_CFG_MASK) }, /* LSW of Direct Slave Local Address Space 0 Range LAS0RR[15:0] */ + { 0x18,HIGH_WORD(PATI_LOC_CFG_ADDR) }, /* MSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[31:16] (CFG) */ + { 0x1A,LOW_WORD(PATI_LOC_CFG_ADDR)|1 }, /* LSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[15:2, 0], Reserved [1] */ + { 0x1C,0x0000 }, /* MSW of Mode/DMA Arbitration MARBR[31, 29:16] or DMAARB[31, 29:16], Reserved [30] */ + { 0x1E,0x0000 }, /* LSW of Mode/DMA Arbitration MARBR[15:0] or DMAARB[15:0] */ + { 0x20,0x0030 }, /* Local Miscellaneous Control 2 / Serial EEPROM WP Addr Boundary LMISC2[5:0], Res[7:6] / PROT_AREA[6:0], Res[7] */ + { 0x22,0x0510 }, /* Local Miscellaneous Control 1 / Local Bus Big/Little Endian Descriptor LMISC1[7:0] / BIGEND[7:0] */ + { 0x24,0x0000 }, /* MSW of Direct Slave Expansion ROM Range EROMRR[31:16] */ + { 0x26,0x0000 }, /* LSW of Direct Slave Expansion ROM Range EROMRR[15:11, 0], Reserved [10:1] */ + { 0x28,0x0000 }, /* MSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[31:16] */ + { 0x2A,0x0000 }, /* LSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[15:11, 5:0], Reserved [10:6] */ + { 0x2C,(0x4243 | HIGH_WORD((PATI_LOC_CFG_SPACE0_ATTR))) }, /* MSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[31:16] */ + { 0x2E,LOW_WORD(PATI_LOC_CFG_SPACE0_ATTR) }, /* LSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[15:0] */ + { 0x30,HIGH_WORD(PATI_DMASTER_MASK) }, /* MSW of Local Range for Direct Master-to-PCI DMRR[31:16] */ + { 0x32,LOW_WORD(PATI_DMASTER_MASK) }, /* LSW of Local Range for Direct Master-to-PCI (Reserved) DMRR[15:0] */ + { 0x34,HIGH_WORD(PATI_DMASTER_ADDR) }, /* MSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[31:16] */ + { 0x36,LOW_WORD(PATI_DMASTER_ADDR) }, /* LSW of Local Base Address for Direct Master-to-PCI Memory (Reserved) DMLBAM[15:0] */ + { 0x38,0x0000 }, /* MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[31:16] */ + { 0x3A,0x0000 }, /* LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration (Reserved) DMLBAI[15:0] */ + { 0x3C,0x0000 }, /* MSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[31:16] */ + { 0x3E,0x0000 }, /* LSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[15:0] */ + { 0x40,0x0000 }, /* MSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[31, 23:16] Reserved [30:24]*/ + { 0x42,0x0000 }, /* LSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[15:0] */ + { 0x44,0x0000 }, /* PCI Subsystem ID PCISID[15:0] */ + { 0x46,0x0000 }, /* PCI Subsystem Vendor ID PCISVID[15:0] */ + { 0x48,HIGH_WORD(PATI_LOC_SDRAM_MASK) }, /* MSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[31:16] */ + { 0x4A,LOW_WORD(PATI_LOC_SDRAM_MASK) }, /* LSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[15:0] */ + { 0x4C,HIGH_WORD(PATI_LOC_SDRAM_ADDR) }, /* MSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[31:16] (SDRAM) */ + { 0x4E,LOW_WORD(PATI_LOC_SDRAM_ADDR) | 0x1 }, /* LSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[15:2, 0], Reserved [1] */ + { 0x50,HIGH_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* MSW of Local Address Space 1 Bus Region Descriptor LBRD1[31:16] */ + { 0x52,LOW_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* LSW of Local Address Space 1 Bus Region Descriptor (Reserved) LBRD1[15:0] */ + { 0x54,0x0000 }, /* Hot Swap Control/Status (Reserved) Reserved */ + { 0x56,0x0000 }, /* Hot Swap Next Capability Pointer / Hot Swap Control HS_NEXT[7:0] / HS_CNTL[7:0] */ + { 0x58,0x0000 }, /* Reserved Reserved */ + { 0x5A,0x0000 }, /* PCI Arbiter Control PCIARB[3:0], Reserved [15:4] */ + { 0x5C,0x0000 }, /* Power Management Capabilities PMC[15:9, 2:0] */ + { 0x5E,0x0000 }, /* Power Management Next Capability Pointer (Reserved) / Power Management Capability ID (Reserved) Reserved*/ + { 0x60,0x0000 }, /* Power Management Data / PMCSR Bridge Support Extension (Reserved) PMDATA[7:0] / Reserved */ + { 0x62,0x0000 }, /* Power Management Control/Status PMCSR[14:8] */ + { 0xFFFF,0xFFFF} /* terminaror */ +}; +#define PATI_EEPROM_LAST_OFFSET 0x64 +#endif /* #ifndef __PCI_EEPROM_H_ */ diff --git a/board/mpl/pati/plx9056.h b/board/mpl/pati/plx9056.h new file mode 100644 index 000000000..763a79378 --- /dev/null +++ b/board/mpl/pati/plx9056.h @@ -0,0 +1,114 @@ +/* + * (C) Copyright 2003 + * Denis Peter, d.peter@mpl.ch + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* PLX9096 register definitions +*/ +#ifndef __PLX9056_H_ +#define __PLX9056_H_ 1 + +#include + +#ifdef PLX9056_LOC +#define LOCAL_OFFSET 0x080 +/* PCI Config regs */ +#else +#define LOCAL_OFFSET 0x000 +#endif + +#define PCI9056_VENDOR_ID PCI_VENDOR_ID +//#define PCI9656_DEVICE_ID PCI_DEVICE_ID +#define PCI9056_COMMAND PCI_COMMAND +//#define PCI9656_STATUS PCI_STATUS +#define PCI9056_REVISION PCI_REVISION_ID + +#define PCI9056_CACHE_SIZE PCI_CACHE_LINE_SIZE +#define PCI9056_RTR_BASE PCI_BASE_ADDRESS_0 +#define PCI9056_RTR_IO_BASE PCI_BASE_ADDRESS_1 +#define PCI9056_LOCAL_BASE0 PCI_BASE_ADDRESS_2 +#define PCI9056_LOCAL_BASE1 PCI_BASE_ADDRESS_3 +#define PCI9056_UNUSED_BASE1 PCI_BASE_ADDRESS_4 +#define PCI9056_UNUSED_BASE2 PCI_BASE_ADDRESS_5 +#define PCI9056_CIS_PTR PCI_CARDBUS_CIS +#define PCI9056_SUB_ID PCI_SUBSYSTEM_VENDOR_ID +#define PCI9056_EXP_ROM_BASE PCI_ROM_ADDRESS +#define PCI9056_CAP_PTR PCI_CAPABILITY_LIST +#define PCI9056_INT_LINE PCI_INTERRUPT_LINE + +#if defined(PLX9056_LOC) + #define PCI9056_PM_CAP_ID 0x180 + #define PCI9056_PM_CSR 0x184 + #define PCI9056_HS_CAP_ID 0x188 + #define PCI9056_VPD_CAP_ID 0x18C + #define PCI9056_VPD_DATA 0x190 +#endif + + + +#define PCI_DEVICE_ID_PLX9056 0x9056 + +/* Local Configuration Registers Accessible via the PCI Base address + Variable */ +#define PCI9056_SPACE0_RANGE (0x000 + LOCAL_OFFSET) +#define PCI9056_SPACE0_REMAP (0x004 + LOCAL_OFFSET) +#define PCI9056_LOCAL_DMA_ARBIT (0x008 + LOCAL_OFFSET) +#define PCI9056_ENDIAN_DESC (0x00c + LOCAL_OFFSET) +#define PCI9056_EXP_ROM_RANGE (0x010 + LOCAL_OFFSET) +#define PCI9056_EXP_ROM_REMAP (0x014 + LOCAL_OFFSET) +#define PCI9056_SPACE0_ROM_DESC (0x018 + LOCAL_OFFSET) +#define PCI9056_DM_RANGE (0x01c + LOCAL_OFFSET) +#define PCI9056_DM_MEM_BASE (0x020 + LOCAL_OFFSET) +#define PCI9056_DM_IO_BASE (0x024 + LOCAL_OFFSET) +#define PCI9056_DM_PCI_MEM_REMAP (0x028 + LOCAL_OFFSET) +#define PCI9056_DM_PCI_IO_CONFIG (0x02c + LOCAL_OFFSET) +#define PCI9056_SPACE1_RANGE (0x0f0 + LOCAL_OFFSET) +#define PCI9056_SPACE1_REMAP (0x0f4 + LOCAL_OFFSET) +#define PCI9056_SPACE1_DESC (0x0f8 + LOCAL_OFFSET) +#define PCI9056_DM_DAC (0x0fc + LOCAL_OFFSET) + +#ifdef PLX9056_LOC +#define PCI9056_ARBITER_CTRL 0x1A0 +#define PCI9056_ABORT_ADDRESS 0x1A4 +#endif + +/* Runtime registers PCI Address + LOCAL_OFFSET */ +#ifdef PLX9056_LOC +#define PCI9056_MAILBOX0 0x0C0 +#define PCI9056_MAILBOX1 0x0C4 +#else +#define PCI9056_MAILBOX0 0x078 +#define PCI9056_MAILBOX1 0x07c +#endif + +#define PCI9056_MAILBOX2 (0x048 + LOCAL_OFFSET) +#define PCI9056_MAILBOX3 (0x04c + LOCAL_OFFSET) +#define PCI9056_MAILBOX4 (0x050 + LOCAL_OFFSET) +#define PCI9056_MAILBOX5 (0x054 + LOCAL_OFFSET) +#define PCI9056_MAILBOX6 (0x058 + LOCAL_OFFSET) +#define PCI9056_MAILBOX7 (0x05c + LOCAL_OFFSET) +#define PCI9056_PCI_TO_LOC_DBELL (0x060 + LOCAL_OFFSET) +#define PCI9056_LOC_TO_PCI_DBELL (0x064 + LOCAL_OFFSET) +#define PCI9056_INT_CTRL_STAT (0x068 + LOCAL_OFFSET) +#define PCI9056_EEPROM_CTRL_STAT (0x06c + LOCAL_OFFSET) +#define PCI9056_PERM_VENDOR_ID (0x070 + LOCAL_OFFSET) +#define PCI9056_REVISION_ID (0x074 + LOCAL_OFFSET) + + +#endif /* #ifndef __PLX9056_H_ */ + diff --git a/board/mpl/pati/u-boot.lds b/board/mpl/pati/u-boot.lds new file mode 100644 index 000000000..318880108 --- /dev/null +++ b/board/mpl/pati/u-boot.lds @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de + * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc5xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +/* . = env_start; + .ppcenv : + { + common/environment.o (.ppcenv) + } +*/ +} diff --git a/cpu/mpc5xx/Makefile b/cpu/mpc5xx/Makefile index ee20dda6c..b787b6141 100644 --- a/cpu/mpc5xx/Makefile +++ b/cpu/mpc5xx/Makefile @@ -35,7 +35,7 @@ include $(TOPDIR)/config.mk LIB = lib$(CPU).a START = start.S -OBJS = serial.o cpu.o cpu_init.o interrupts.o traps.o speed.o +OBJS = serial.o cpu.o cpu_init.o interrupts.o traps.o speed.o spi.o all: .depend $(START) $(LIB) diff --git a/cpu/mpc5xx/cpu.c b/cpu/mpc5xx/cpu.c index cc695118e..0c22a31f0 100644 --- a/cpu/mpc5xx/cpu.c +++ b/cpu/mpc5xx/cpu.c @@ -122,12 +122,30 @@ unsigned long get_tbclk (void) return (oscclk / 16); } +void dcache_enable (void) +{ + return; +} + +void dcache_disable (void) +{ + return; +} + +int dcache_status (void) +{ + return 0; /* always off */ +} /* * Reset board */ int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { +#if defined(CONFIG_PATI) + volatile ulong *addr = (ulong *) CFG_RESET_ADDRESS; + *addr = 1; +#else ulong addr; /* Interrupts off, enable reset */ @@ -150,5 +168,6 @@ int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) addr = CFG_MONITOR_BASE - sizeof (ulong); #endif ((void (*) (void)) addr) (); +#endif /* #if defined(CONFIG_PATI) */ return 1; } diff --git a/cpu/mpc5xx/cpu_init.c b/cpu/mpc5xx/cpu_init.c index e19d0f49b..f4cd24bf7 100644 --- a/cpu/mpc5xx/cpu_init.c +++ b/cpu/mpc5xx/cpu_init.c @@ -64,6 +64,8 @@ void cpu_init_f (volatile immap_t * immr) immr->im_sitk.sitk_piscrk = KAPWR_KEY; immr->im_sit.sit_piscr = CFG_PISCR; +#if !defined(CONFIG_PATI) + /* PATI sest PLL in start.S */ /* PLL (CPU clock) settings */ immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; @@ -81,6 +83,8 @@ void cpu_init_f (volatile immap_t * immr) #endif immr->im_clkrst.car_plprcr = reg; +#endif /* !defined(CONFIG_PATI) */ + /* System integration timers. CFG_MASK has EBDF configuration */ immr->im_clkrstk.cark_sccrk = KAPWR_KEY; reg = immr->im_clkrst.car_sccr; diff --git a/cpu/mpc5xx/interrupts.c b/cpu/mpc5xx/interrupts.c index 3678b5bfc..7f6e1363e 100644 --- a/cpu/mpc5xx/interrupts.c +++ b/cpu/mpc5xx/interrupts.c @@ -28,12 +28,20 @@ */ #include +#include #include #include +#if defined(CONFIG_PATI) +/* PATI uses IRQs for PCI doorbell */ +#undef NR_IRQS +#define NR_IRQS 16 +#endif + struct interrupt_action { interrupt_handler_t *handler; void *arg; + int count; }; static struct interrupt_action irq_vecs[NR_IRQS]; @@ -45,12 +53,18 @@ static struct interrupt_action irq_vecs[NR_IRQS]; int interrupt_init_cpu (ulong *decrementer_count) { volatile immap_t *immr = (immap_t *) CFG_IMMR; + int vec; /* Decrementer used here for status led */ *decrementer_count = get_tbclk () / CFG_HZ; /* Disable all interrupts */ immr->im_siu_conf.sc_simask = 0; + for (vec=0; vec, + * + * Copyright (c) 2001 Gerd Mennchen + * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, . + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * MPC5xx CPM SPI interface. + * + * Parts of this code are probably not portable and/or specific to + * the board which I used for the tests. Please send fixes/complaints + * to wd@denx.de + * + * Ported to MPC5xx + * Copyright (c) 2003 Denis Peter, MPL AG Switzerland, d.petr@mpl.ch. + */ + +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_SPI) + +#undef DEBUG + +#define SPI_EEPROM_WREN 0x06 +#define SPI_EEPROM_RDSR 0x05 +#define SPI_EEPROM_READ 0x03 +#define SPI_EEPROM_WRITE 0x02 + + +#ifdef DEBUG + +#define DPRINT(a) printf a; +/* ----------------------------------------------- + * Helper functions to peek into tx and rx buffers + * ----------------------------------------------- */ +static const char * const hex_digit = "0123456789ABCDEF"; + +static char quickhex (int i) +{ + return hex_digit[i]; +} + +static void memdump (void *pv, int num) +{ + int i; + unsigned char *pc = (unsigned char *) pv; + + for (i = 0; i < num; i++) + printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f)); + printf ("\t"); + for (i = 0; i < num; i++) + printf ("%c", isprint (pc[i]) ? pc[i] : '.'); + printf ("\n"); +} +#else /* !DEBUG */ + +#define DPRINT(a) + +#endif /* DEBUG */ + +/* ------------------- + * Function prototypes + * ------------------- */ +void spi_init (void); + +ssize_t spi_read (uchar *, int, uchar *, int); +ssize_t spi_write (uchar *, int, uchar *, int); +ssize_t spi_xfer (size_t); + + +/* ************************************************************************** + * + * Function: spi_init_f + * + * Description: Init SPI-Controller (ROM part) + * + * return: --- + * + * *********************************************************************** */ + +void spi_init_f (void) +{ + int i; + + volatile immap_t *immr; + volatile qsmcm5xx_t *qsmcm; + + immr = (immap_t *) CFG_IMMR; + qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; + + qsmcm->qsmcm_qsmcr = 0; /* all accesses enabled */ + qsmcm->qsmcm_qspi_il = 0; /* lowest IRQ */ + + /* -------------------------------------------- + * GPIO or per. Function + * PQSPAR[00] = 0 reserved + * PQSPAR[01] = 1 [0x4000] -> PERI: (SPICS3) + * PQSPAR[02] = 0 [0x0000] -> GPIO + * PQSPAR[03] = 0 [0x0000] -> GPIO + * PQSPAR[04] = 1 [0x0800] -> PERI: (SPICS0) + * PQSPAR[05] = 0 reseved + * PQSPAR[06] = 1 [0x0200] -> PERI: (SPIMOSI) + * PQSPAR[07] = 1 [0x0100] -> PERI: (SPIMISO) + * -------------------------------------------- */ + qsmcm->qsmcm_pqspar = 0x3 | (CFG_SPI_CS_USED << 3); + + /* -------------------------------------------- + * DDRQS[00] = 0 reserved + * DDRQS[01] = 1 [0x0040] -> SPICS3 Output + * DDRQS[02] = 0 [0x0000] -> GPIO Output + * DDRQS[03] = 0 [0x0000] -> GPIO Output + * DDRQS[04] = 1 [0x0008] -> SPICS0 Output + * DDRQS[05] = 1 [0x0004] -> SPICLK Output + * DDRQS[06] = 1 [0x0002] -> SPIMOSI Output + * DDRQS[07] = 0 [0x0001] -> SPIMISO Input + * -------------------------------------------- */ + qsmcm->qsmcm_ddrqs = 0x7E; + /* -------------------------------------------- + * Base state for used SPI CS pins, if base = 0 active must be 1 + * PORTQS[00] = 0 reserved + * PORTQS[01] = 0 reserved + * PORTQS[02] = 0 reserved + * PORTQS[03] = 0 reserved + * PORTQS[04] = 0 [0x0000] RxD2 + * PORTQS[05] = 1 [0x0400] TxD2 + * PORTQS[06] = 0 [0x0000] RxD1 + * PORTQS[07] = 1 [0x0100] TxD1 + * PORTQS[08] = 0 reserved + * PORTQS[09] = 0 [0x0000] -> SPICS3 Base Output + * PORTQS[10] = 0 [0x0000] -> SPICS2 Base Output + * PORTQS[11] = 0 [0x0000] -> SPICS1 Base Output + * PORTQS[12] = 0 [0x0000] -> SPICS0 Base Output + * PORTQS[13] = 0 [0x0004] -> SPICLK Output + * PORTQS[14] = 0 [0x0002] -> SPIMOSI Output + * PORTQS[15] = 0 [0x0001] -> SPIMISO Input + * -------------------------------------------- */ + qsmcm->qsmcm_portqs |= (CFG_SPI_CS_BASE << 3); + /* -------------------------------------------- + * Controll Register 0 + * SPCR0[00] = 1 (0x8000) Master + * SPCR0[01] = 0 (0x0000) Wired-Or + * SPCR0[2..5] = (0x2000) Bits per transfer (default 8) + * SPCR0[06] = 0 (0x0000) Normal polarity + * SPCR0[07] = 0 (0x0000) Normal Clock Phase + * SPCR0[08..15] = 14 1.4MHz + */ + qsmcm->qsmcm_spcr0=0xA00E; + /* -------------------------------------------- + * Controll Register 1 + * SPCR1[00] = 0 (0x0000) QSPI enabled + * SPCR1[1..7] = (0x7F00) Delay before Transfer + * SPCR1[8..15] = (0x0000) Delay After transfer (204.8usec@40MHz) + */ + qsmcm->qsmcm_spcr1=0x7F00; + /* -------------------------------------------- + * Controll Register 2 + * SPCR2[00] = 0 (0x0000) SPI IRQs Disabeld + * SPCR2[01] = 0 (0x0000) No Wrap around + * SPCR2[02] = 0 (0x0000) Wrap to 0 + * SPCR2[3..7] = (0x0000) End Queue pointer = 0 + * SPCR2[8..10] = 0 (0x0000) reserved + * SPCR2[11..15] = 0 (0x0000) NewQueue Address = 0 + */ + qsmcm->qsmcm_spcr2=0x0000; + /* -------------------------------------------- + * Controll Register 3 + * SPCR3[00..04] = 0 (0x0000) reserved + * SPCR3[05] = 0 (0x0000) Feedback disabled + * SPCR3[06] = 0 (0x0000) IRQ on HALTA & MODF disabled + * SPCR3[07] = 0 (0x0000) Not halted + */ + qsmcm->qsmcm_spcr3=0x00; + /* -------------------------------------------- + * SPSR (Controll Register 3) Read only/ reset Flags 08,09,10 + * SPCR3[08] = 1 (0x80) QSPI finished + * SPCR3[09] = 1 (0x40) Mode Fault Flag + * SPCR3[10] = 1 (0x20) HALTA + * SPCR3[11..15] = 0 (0x0000) Last executed command + */ + qsmcm->qsmcm_spsr=0xE0; + /*------------------------------------------- + * Setup RAM + */ + for(i=0;i<32;i++) { + qsmcm->qsmcm_recram[i]=0x0000; + qsmcm->qsmcm_tranram[i]=0x0000; + qsmcm->qsmcm_comdram[i]=0x00; + } + return; +} + +/* ************************************************************************** + * + * Function: spi_init_r + * Dummy, all initializations have been done in spi_init_r + * *********************************************************************** */ +void spi_init_r (void) +{ + return; + +} + +/**************************************************************************** + * Function: spi_write + **************************************************************************** */ +ssize_t short_spi_write (uchar *addr, int alen, uchar *buffer, int len) +{ + int i,dlen; + volatile immap_t *immr; + volatile qsmcm5xx_t *qsmcm; + + immr = (immap_t *) CFG_IMMR; + qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; + for(i=0;i<32;i++) { + qsmcm->qsmcm_recram[i]=0x0000; + qsmcm->qsmcm_tranram[i]=0x0000; + qsmcm->qsmcm_comdram[i]=0x00; + } + qsmcm->qsmcm_tranram[0] = SPI_EEPROM_WREN; /* write enable */ + spi_xfer(1); + i=0; + qsmcm->qsmcm_tranram[i++] = SPI_EEPROM_WRITE; /* WRITE memory array */ + qsmcm->qsmcm_tranram[i++] = addr[0]; + qsmcm->qsmcm_tranram[i++] = addr[1]; + + for(dlen=0;dlenqsmcm_tranram[i+dlen] = buffer[dlen]; /* WRITE memory array */ + } + /* transmit it */ + spi_xfer(i+dlen); + /* ignore received data */ + for (i = 0; i < 1000; i++) { + qsmcm->qsmcm_tranram[0] = SPI_EEPROM_RDSR; /* read status */ + qsmcm->qsmcm_tranram[1] = 0; + spi_xfer(2); + if (!(qsmcm->qsmcm_recram[1] & 1)) { + break; + } + udelay(1000); + } + if (i >= 1000) { + printf ("*** spi_write: Time out while writing!\n"); + } + return len; +} + +#define TRANSFER_LEN 16 + +ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) +{ + int index,i,newlen; + uchar newaddr[2]; + int curraddr; + + curraddr=(addr[alen-2]<<8)+addr[alen-1]; + i=len; + index=0; + do { + newaddr[1]=(curraddr & 0xff); + newaddr[0]=((curraddr>>8) & 0xff); + if(i>TRANSFER_LEN) { + newlen=TRANSFER_LEN; + i-=TRANSFER_LEN; + } + else { + newlen=i; + i=0; + } + short_spi_write (newaddr, 2, &buffer[index], newlen); + index+=newlen; + curraddr+=newlen; + }while(i); + return (len); +} + +/**************************************************************************** + * Function: spi_read + **************************************************************************** */ +ssize_t short_spi_read (uchar *addr, int alen, uchar *buffer, int len) +{ + int i; + volatile immap_t *immr; + volatile qsmcm5xx_t *qsmcm; + + immr = (immap_t *) CFG_IMMR; + qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; + + for(i=0;i<32;i++) { + qsmcm->qsmcm_recram[i]=0x0000; + qsmcm->qsmcm_tranram[i]=0x0000; + qsmcm->qsmcm_comdram[i]=0x00; + } + i=0; + qsmcm->qsmcm_tranram[i++] = (SPI_EEPROM_READ); /* READ memory array */ + qsmcm->qsmcm_tranram[i++] = addr[0] & 0xff; + qsmcm->qsmcm_tranram[i++] = addr[1] & 0xff; + spi_xfer(3 + len); + for(i=0;iqsmcm_recram[i+3]; + } + return len; +} + +ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len) +{ + int index,i,newlen; + uchar newaddr[2]; + int curraddr; + + curraddr=(addr[alen-2]<<8)+addr[alen-1]; + i=len; + index=0; + do { + newaddr[1]=(curraddr & 0xff); + newaddr[0]=((curraddr>>8) & 0xff); + if(i>TRANSFER_LEN) { + newlen=TRANSFER_LEN; + i-=TRANSFER_LEN; + } + else { + newlen=i; + i=0; + } + short_spi_read (newaddr, 2, &buffer[index], newlen); + index+=newlen; + curraddr+=newlen; + }while(i); + return (len); +} + + + +/**************************************************************************** + * Function: spi_xfer + **************************************************************************** */ +ssize_t spi_xfer (size_t count) +{ + volatile immap_t *immr; + volatile qsmcm5xx_t *qsmcm; + int i; + int tm; + ushort status; + immr = (immap_t *) CFG_IMMR; + qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; + DPRINT (("*** spi_xfer entered count %d***\n",count)); + + /* Set CS for device */ + for(i=0;i<(count-1);i++) + qsmcm->qsmcm_comdram[i] = 0x80 | CFG_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */ + + qsmcm->qsmcm_comdram[i] = CFG_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */ + qsmcm->qsmcm_spcr2=((count-1)&0x1F)<<8; + + DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n", count)); + + qsmcm->qsmcm_spsr=0xE0; /* clear all flags */ + + /* start spi transfer */ + DPRINT (("*** spi_xfer: Performing transfer ...\n")); + qsmcm->qsmcm_spcr1 |= 0x8000; /* Start transmit */ + + /* -------------------------------- + * Wait for SPI transmit to get out + * or time out (1 second = 1000 ms) + * -------------------------------- */ + for (tm=0; tm<1000; ++tm) { + status=qsmcm->qsmcm_spcr1; + if((status & 0x8000)==0) + break; + udelay (1000); + } + if (tm >= 1000) { + printf ("*** spi_xfer: Time out while xferring to/from SPI!\n"); + } +#ifdef DEBUG + printf ("\nspi_xfer: txbuf after xfer\n"); + memdump ((void *) qsmcm->qsmcm_tranram, 32); /* dump of txbuf before transmit */ + printf ("spi_xfer: rxbuf after xfer\n"); + memdump ((void *) qsmcm->qsmcm_recram, 32); /* dump of rxbuf after transmit */ + printf ("\nspi_xfer: commbuf after xfer\n"); + memdump ((void *) qsmcm->qsmcm_comdram, 32); /* dump of txbuf before transmit */ + printf ("\n"); +#endif + + return count; +} + +#endif /* CONFIG_SPI */ + + diff --git a/cpu/mpc5xx/start.S b/cpu/mpc5xx/start.S index 548ec99e2..b56be2f30 100644 --- a/cpu/mpc5xx/start.S +++ b/cpu/mpc5xx/start.S @@ -117,6 +117,29 @@ boot_warm: mtspr COUNTA, r0 mtspr COUNTB, r0 +#if defined(CONFIG_PATI) + /* the external flash access on PATI fails if programming the PLL to 40MHz. + * Copy the PLL programming code to the internal RAM and execute it + *----------------------------------------------------------------------*/ + lis r3, CFG_MONITOR_BASE@h + ori r3, r3, CFG_MONITOR_BASE@l + addi r3, r3, pll_prog_code_start - _start + EXC_OFF_SYS_RESET + + lis r4, CFG_INIT_RAM_ADDR@h + ori r4, r4, CFG_INIT_RAM_ADDR@l + mtlr r4 + addis r5,0,0x0 + ori r5,r5,((pll_prog_code_end - pll_prog_code_start) >>2) + mtctr r5 + addi r3, r3, -4 + addi r4, r4, -4 +0: + lwzu r0,4(r3) + stwu r0,4(r4) + bdnz 0b /* copy loop */ + blrl +#endif + /* * Calculate absolute address in FLASH and jump there *----------------------------------------------------------------------*/ @@ -553,3 +576,30 @@ trap_reloc: isync blr + + +#if defined(CONFIG_PATI) +/* Program the PLL */ +pll_prog_code_start: + lis r4, (CFG_IMMR + 0x002fc384)@h + ori r4, r4, (CFG_IMMR + 0x002fc384)@l + lis r3, (0x55ccaa33)@h + ori r3, r3, (0x55ccaa33)@l + stw r3, 0(r4) + lis r4, (CFG_IMMR + 0x002fc284)@h + ori r4, r4, (CFG_IMMR + 0x002fc284)@l + lis r3, CFG_PLPRCR@h + ori r3, r3, CFG_PLPRCR@l + stw r3, 0(r4) + addis r3,0,0x0 + ori r3,r3,0xA000 + mtctr r3 +..spinlp: + bdnz ..spinlp /* spin loop */ + blr +pll_prog_code_end: + nop + blr +#endif + + diff --git a/drivers/rtl8139.c b/drivers/rtl8139.c index 5b14e717d..b9e4a8d41 100644 --- a/drivers/rtl8139.c +++ b/drivers/rtl8139.c @@ -44,7 +44,7 @@ which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My interpretation of this "reserved" is that Etherboot may do whatever it likes, as long as its environment is kept intact (like the BIOS - variables). Hopefully fixed rtl_poll() once and for all. The symptoms + variables). Hopefully fixed rtl_poll() once and for all. The symptoms were that if Etherboot was left at the boot menu for several minutes, the first eth_poll failed. Seems like I am the only person who does this. First of all I fixed the debugging code and then set out for a long bug @@ -53,18 +53,18 @@ driver and even the FreeBSD driver (what a piece of crap!) - and eventually spotted the nasty thing: the transmit routine was acknowledging each and every interrupt pending, including the RxOverrun and RxFIFIOver - interrupts. This confused the RTL8139 thoroughly. It destroyed the + interrupts. This confused the RTL8139 thoroughly. It destroyed the Rx ring contents by dumping the 2K FIFO contents right where we wanted to get the next packet. Oh well, what fun. - 18 Jan 2000 mdc@thinguin.org (Marty Connor) + 18 Jan 2000 mdc@thinguin.org (Marty Connor) Drastically simplified error handling. Basically, if any error in transmission or reception occurs, the card is reset. Also, pointed all transmit descriptors to the same buffer to - save buffer space. This should decrease driver size and avoid + save buffer space. This should decrease driver size and avoid corruption because of exceeding 32K during runtime. - 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de) + 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de) rtl_poll was quite broken: it used the RxOK interrupt flag instead of the RxBufferEmpty flag which often resulted in very bad transmission performace - below 1kBytes/s. @@ -77,10 +77,6 @@ #include #include -#ifdef __MIPS__ -static unsigned long mips_io_port_base = 0; -#endif - #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ defined(CONFIG_RTL8139) @@ -95,11 +91,11 @@ static unsigned long mips_io_port_base = 0; /* PCI Tuning Parameters Threshold is bytes transferred to chip before transmission starts. */ -#define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */ -#define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */ -#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */ -#define TX_DMA_BURST 4 /* Calculate as 16<priv, a) -#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) +#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) +#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) /* Symbolic offsets to registers. */ enum RTL8139_registers { @@ -276,12 +272,12 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis) /* Serial EEPROM section. */ /* EEPROM_Ctrl bits. */ -#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ -#define EE_CS 0x08 /* EEPROM chip select. */ -#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */ -#define EE_WRITE_0 0x00 -#define EE_WRITE_1 0x02 -#define EE_DATA_READ 0x01 /* EEPROM chip data out. */ +#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ +#define EE_CS 0x08 /* EEPROM chip select. */ +#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */ +#define EE_WRITE_0 0x00 +#define EE_WRITE_1 0x02 +#define EE_DATA_READ 0x01 /* EEPROM chip data out. */ #define EE_ENB (0x80 | EE_CS) /* @@ -289,12 +285,12 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis) No extra delay is needed with 33Mhz PCI, but 66Mhz may change this. */ -#define eeprom_delay() inl(ee_addr) +#define eeprom_delay() inl(ee_addr) /* The EEPROM commands include the alway-set leading bit. */ -#define EE_WRITE_CMD (5) -#define EE_READ_CMD (6) -#define EE_ERASE_CMD (7) +#define EE_WRITE_CMD (5) +#define EE_READ_CMD (6) +#define EE_ERASE_CMD (7) static int read_eeprom(int location, int addr_len) { @@ -390,7 +386,7 @@ static void rtl_reset(struct eth_device *dev) /* If we add multicast support, the MAR0 register would have to be * initialized to 0xffffffffffffffff (two 32 bit accesses). Etherboot - * only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast. */ + * only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast. */ outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd); @@ -436,7 +432,7 @@ static int rtl_transmit(struct eth_device *dev, volatile void *packet, int lengt status = inw(ioaddr + IntrStatus); /* Only acknlowledge interrupt sources we can properly handle * here - the RxOverflow/RxFIFOOver MUST be handled in the - * rtl_poll() function. */ + * rtl_poll() function. */ outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus); if ((status & (TxOK | TxErr | PCIErr)) != 0) break; } while (currticks() < to); @@ -490,7 +486,7 @@ static int rtl_poll(struct eth_device *dev) if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) || (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) { printf("rx error %hX\n", rx_status); - rtl_reset(dev); /* this clears all interrupts still pending */ + rtl_reset(dev); /* this clears all interrupts still pending */ return 0; } @@ -527,6 +523,8 @@ static void rtl_disable(struct eth_device *dev) { int i; + ioaddr = dev->iobase; + /* reset the chip */ outb(CmdReset, ioaddr + ChipCmd); diff --git a/include/asm-arm/u-boot-arm.h b/include/asm-arm/u-boot-arm.h index 4c92b1f36..d5dbd6d1b 100644 --- a/include/asm-arm/u-boot-arm.h +++ b/include/asm-arm/u-boot-arm.h @@ -43,6 +43,8 @@ int cleanup_before_linux(void); /* board/.../... */ int board_init(void); int dram_init (void); +void setup_serial_tag (struct tag **params); +void setup_revision_tag (struct tag **params); /* ------------------------------------------------------------ */ /* Here is a list of some prototypes which are incompatible to */ diff --git a/include/common.h b/include/common.h index 73a5a2e88..6b9254824 100644 --- a/include/common.h +++ b/include/common.h @@ -185,6 +185,7 @@ void inline setenv (char *, char *); void setenv (char *, char *); #endif /* CONFIG_PPC */ #ifdef CONFIG_ARM +# include # include /* ARM version to be fixed! */ #endif /* CONFIG_ARM */ #ifdef CONFIG_I386 /* x86 version to be fixed! */ diff --git a/include/configs/PATI.h b/include/configs/PATI.h new file mode 100644 index 000000000..42c78d462 --- /dev/null +++ b/include/configs/PATI.h @@ -0,0 +1,285 @@ +/* + * (C) Copyright 2003 + * Denis Peter d.peter@mpl.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, + */ + +/* + * File: PATI.h + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ + +#define CONFIG_MPC555 1 /* This is an MPC555 CPU */ +#define CONFIG_PATI 1 /* ...On a PATI board */ +/* Serial Console Configuration */ +#define CONFIG_5xx_CONS_SCI1 +#undef CONFIG_5xx_CONS_SCI2 + +#define CONFIG_BAUDRATE 9600 + +#define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_LOADB | CFG_CMD_REGINFO | \ + CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_ENV | CFG_CMD_REGINFO | \ + CFG_CMD_BDI | CFG_CMD_CONSOLE | CFG_CMD_RUN | CFG_CMD_BSP | \ + CFG_CMD_IMI | CFG_CMD_EEPROM | CFG_CMD_IRQ | CFG_CMD_MISC \ +) + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif +#define CONFIG_BOOTCOMMAND "" /* autoboot command */ + +#define CONFIG_BOOTARGS "" /* */ + +#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ + +/*#define CONFIG_STATUS_LED 1 *//* Enable status led */ + +#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */ + +/* + * Miscellaneous configurable options + */ +#define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */ +#define CONFIG_PREBOOT + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "pati=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00010000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } + + +/*********************************************************************** + * Last Stage Init + ***********************************************************************/ +#define CONFIG_LAST_STAGE_INIT + +/* + * Low Level Configuration Settings + */ + +/* + * Internal Memory Mapped (This is not the IMMR content) + */ +#define CFG_IMMR 0x01C00000 /* Physical start adress of internal memory map */ + +/* + * Definitions for initial stack pointer and data area + */ +#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ +#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ +#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial global data */ +#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */ +#define CFG_INIT_SP_ADDR (CFG_IMMR + 0x03fa000) /* Physical start adress of inital stack */ +/* + * Start addresses for the final memory configuration + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ +#define CFG_FLASH_BASE 0xffC00000 /* External flash */ +#define PCI_BASE 0x03000000 /* PCI Base (CS2) */ +#define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */ +#define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */ + +#define CFG_MONITOR_BASE 0xFFF00000 +/* CFG_FLASH_BASE */ /* TEXT_BASE is defined in the board config.mk file. */ + /* This adress is given to the linker with -Ttext to */ + /* locate the text section at this adress. */ +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + + + +#define CFG_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + + +/*----------------------------------------------------------------------- + * FLASH organization + *----------------------------------------------------------------------- + * + */ + +#define CFG_MAX_FLASH_BANKS 1 /* Max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* Max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ + + +#define CFG_ENV_IS_IN_EEPROM +#ifdef CFG_ENV_IS_IN_EEPROM +#define CFG_ENV_OFFSET 0 +#define CFG_ENV_SIZE 2048 +#endif + +#undef CFG_ENV_IS_IN_FLASH +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SIZE 0x00002000 /* Set whole sector as env */ +#define CFG_ENV_OFFSET ((0 - CFG_FLASH_BASE) - CFG_ENV_SIZE) /* Environment starts at this adress */ +#endif + + +#define CONFIG_SPI 1 +#define CFG_SPI_CS_USED 0x09 /* CS0 and CS3 are used */ +#define CFG_SPI_CS_BASE 0x08 /* CS3 is active low */ +#define CFG_SPI_CS_ACT 0x00 /* CS3 is active low */ +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * SW Watchdog freeze + */ +#undef CONFIG_WATCHDOG +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + + + + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF00 +#define CFG_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ + SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000) + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration + *----------------------------------------------------------------------- + * Data show cycle + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */ + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register + *----------------------------------------------------------------------- + * Set all bits to 40 Mhz + * + */ +#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ + + +#define CFG_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) + +/*----------------------------------------------------------------------- + * UMCR - UIMB Module Configuration Register + *----------------------------------------------------------------------- + * + */ +#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ + +/*----------------------------------------------------------------------- + * ICTRL - I-Bus Support Control Register + */ +#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ + +/*----------------------------------------------------------------------- + * USIU - Memory Controller Register + *----------------------------------------------------------------------- + */ +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA) +#define CFG_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */ +/* SDRAM */ +#define CFG_BR1_PRELIM (CFG_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) +#define CFG_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */ +/* PCI */ +#define CFG_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA) +#define CFG_OR2_PRELIM (OR_ADDR_MK_FF) +/* config registers: */ +#define CFG_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) +#define CFG_OR3_PRELIM (0xffff0000) + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* We don't realign the flash */ + +/*----------------------------------------------------------------------- + * DER - Timer Decrementer + *----------------------------------------------------------------------- + * Initialise to zero + */ +#define CFG_DER 0x00000000 + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +#define VERSION_TAG "released" +#define CONFIG_ISO_STRING "MEV-10084-001" + +#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG + +#endif /* __CONFIG_H */ diff --git a/include/mpc5xx.h b/include/mpc5xx.h index 345fca8de..7508f6df2 100644 --- a/include/mpc5xx.h +++ b/include/mpc5xx.h @@ -75,6 +75,10 @@ #define SIUMCR_DBPC01 0x00080000 /* - " - */ #define SIUMCR_DBPC10 0x00100000 /* - " - */ #define SIUMCR_DBPC11 0x00180000 /* - " - */ +#define SIUMCR_GPC00 0x00000000 /* General Pins Config */ +#define SIUMCR_GPC01 0x00020000 /* General Pins Config */ +#define SIUMCR_GPC10 0x00040000 /* General Pins Config */ +#define SIUMCR_GPC11 0x00060000 /* General Pins Config */ #define SIUMCR_DLK 0x00010000 /* Debug Register Lock */ #define SIUMCR_SC00 0x00000000 /* Multi Chip 32 bit */ #define SIUMCR_SC01 0x00004000 /* Muilt Chip 16 bit */ @@ -98,6 +102,7 @@ * PISCR - Periodic Interrupt Status and Control Register */ #define PISCR_PITF ((ushort)0x0002) /* PIT stops when FREEZE */ +#define PISCR_PS 0x0080 /* Periodic Interrupt Status */ /*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register @@ -106,11 +111,12 @@ #define PLPRCR_DIVF_MSK 0x0000001f /* DIVF mask */ #define PLPRCR_CSRC_MSK 0x00000400 /* CSRC mask */ #define PLPRCR_MF_SHIFT 0x00000014 /* Multiplication factor shift value */ -#define PLPRCR_DIVF_0 0x00900000 /* Division factor 0 */ -#define PLPRCR_MF_9 0x00000000 /* Mulitipliaction factor 9 */ +#define PLPRCR_DIVF_0 0x00000000 /* Division factor 0 */ +#define PLPRCR_MF_9 0x00900000 /* Mulitipliaction factor 9 */ #define PLPRCR_TEXPS 0x00004000 /* TEXP Status */ #define PLPRCR_TMIST 0x00001000 /* Timers Interrupt Status */ #define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */ +#define PLPRCR_SPLSS 0x00008000 /* SPLL Lock Status Sticky bit */ /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register @@ -124,6 +130,7 @@ #define SCCR_TBS 0x02000000 /* Time Base Source */ #define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */ #define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */ +#define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */ #define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */ #define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */ @@ -136,6 +143,7 @@ #define BR_PS_16 0x00000800 /* 16 bit port size */ #define BR_PS_32 0x00000000 /* 32 bit port size */ #define BR_LBDIR 0x00000008 /* Late burst data in progess */ +#define BR_SETA 0x00000004 /* External Data Acknowledge */ #define OR_SCY_3 0x00000030 /* 3 clock cycles wait states */ #define OR_SCY_1 0x00000000 /* 1 clock cycle wait state */ #define OR_SCY_8 0x00000080 /* 8 clock cycles wait states */ @@ -143,7 +151,7 @@ #define OR_BSCY 0x00000060 /* Burst beats length in clocks */ #define OR_ACS_10 0x00000600 /* Adress to chip-select setup */ #define OR_CSNT 0x00000800 /* Chip-select negotation time */ -#define OR_ETHR 0x00000000 /* Extended hold time on read */ +#define OR_ETHR 0x00000100 /* Extended hold time on read */ #define OR_ADDR_MK_FF 0xFF000000 #define OR_ADDR_MK_FFFF 0xFFFF0000 diff --git a/lib_arm/armlinux.c b/lib_arm/armlinux.c index 19680b58a..e96ea8152 100644 --- a/lib_arm/armlinux.c +++ b/lib_arm/armlinux.c @@ -30,16 +30,14 @@ #include #endif -#include -#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) -#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size)) - /*cmd_boot.c*/ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); #if defined (CONFIG_SETUP_MEMORY_TAGS) || \ defined (CONFIG_CMDLINE_TAG) || \ defined (CONFIG_INITRD_TAG) || \ + defined (CONFIG_SERIAL_TAG) || \ + defined (CONFIG_REVISION_TAG) || \ defined (CONFIG_VFD) static void setup_start_tag (bd_t *bd); @@ -221,8 +219,16 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], #if defined (CONFIG_SETUP_MEMORY_TAGS) || \ defined (CONFIG_CMDLINE_TAG) || \ defined (CONFIG_INITRD_TAG) || \ + defined (CONFIG_SERIAL_TAG) || \ + defined (CONFIG_REVISION_TAG) || \ defined (CONFIG_VFD) setup_start_tag (bd); +#ifdef CONFIG_SERIAL_TAG + setup_serial_tag (¶ms); +#endif +#ifdef CONFIG_REVISION_TAG + setup_revision_tag (¶ms); +#endif #ifdef CONFIG_SETUP_MEMORY_TAGS setup_memory_tags (bd); #endif @@ -251,6 +257,8 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], #if defined (CONFIG_SETUP_MEMORY_TAGS) || \ defined (CONFIG_CMDLINE_TAG) || \ defined (CONFIG_INITRD_TAG) || \ + defined (CONFIG_SERIAL_TAG) || \ + defined (CONFIG_REVISION_TAG) || \ defined (CONFIG_VFD) static void setup_start_tag (bd_t *bd) { @@ -308,10 +316,6 @@ static void setup_commandline_tag (bd_t *bd, char *commandline) } -#ifndef ATAG_INITRD2 -#define ATAG_INITRD2 0x54420005 -#endif - #ifdef CONFIG_INITRD_TAG static void setup_initrd_tag (bd_t *bd, ulong initrd_start, ulong initrd_end) {