Merge branch 'for-next/openrisc'
This commit is contained in:
Sascha Hauer
commit
b7a7b02af5
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@ -46,9 +46,47 @@ __reset:
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l.ori r3,r0,SPR_SR_SM
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l.mtspr r0,r3,SPR_SR
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l.jal _cur
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l.nop
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_cur:
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l.ori r8, r9, 0 /* Get _cur current address */
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l.movhi r3, hi(_cur)
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l.ori r3, r3, lo(_cur)
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l.sfeq r8, r3 /* If we are running at the linked address */
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l.bf _no_vector_reloc /* there is not need for relocation */
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l.sub r8, r8, r3
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l.mfspr r4, r0, SPR_CPUCFGR
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l.andi r4, r4, SPR_CPUCFGR_EVBARP /* Exception Vector Base Address Register present ? */
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l.sfnei r4,0
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l.bnf _reloc_vectors
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l.movhi r5, 0 /* Destination */
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l.mfspr r4, r0, SPR_EVBAR
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l.add r5, r5, r4
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_reloc_vectors:
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/* Relocate vectors*/
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l.movhi r6, hi(__start) /* Length */
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l.ori r6, r6, lo(__start)
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l.ori r3, r8, 0
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.L_relocvectors:
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l.lwz r7, 0(r3)
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l.sw 0(r5), r7
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l.addi r5, r5, 4
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l.sfeq r5, r6
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l.bnf .L_relocvectors
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l.addi r3, r3, 4
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_no_vector_reloc:
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/* Relocate barebox */
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l.movhi r3,hi(__start) /* source start address */
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l.movhi r3,hi(__start) /* source start offset */
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l.ori r3,r3,lo(__start)
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l.add r3,r8,r3
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l.movhi r4,hi(_stext) /* dest start address */
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l.ori r4,r4,lo(_stext)
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l.movhi r5,hi(__end) /* dest end address */
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@ -62,22 +100,11 @@ __reset:
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l.bf .L_reloc
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l.addi r4,r4,4 /*delay slot */
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#ifdef CONFIG_SYS_RELOCATE_VECTORS
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/* Relocate vectors from 0xf0000000 to 0x00000000 */
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l.movhi r4, 0xf000 /* source */
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l.movhi r5, 0 /* destination */
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l.addi r6, r5, CONFIG_SYS_VECTORS_LEN /* length */
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.L_relocvectors:
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l.lwz r7, 0(r4)
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l.sw 0(r5), r7
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l.addi r5, r5, 4
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l.sfeq r5,r6
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l.bnf .L_relocvectors
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l.addi r4,r4, 4
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#endif
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l.j _start
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l.nop
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/* JUMP TO RELOC ADDR */
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l.movhi r4, hi(_start)
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l.ori r4, r4, lo(_start)
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l.jr r4
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l.nop
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/* bus error */
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.org 0x200
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@ -49,6 +49,11 @@
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#define SPR_ICCFGR (SPRGROUP_SYS + 6)
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#define SPR_DCFGR (SPRGROUP_SYS + 7)
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#define SPR_PCCFGR (SPRGROUP_SYS + 8)
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#define SPR_VR2 (SPRGROUP_SYS + 9)
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#define SPR_AVR (SPRGROUP_SYS + 10)
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#define SPR_EVBAR (SPRGROUP_SYS + 11)
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#define SPR_AECR (SPRGROUP_SYS + 12)
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#define SPR_AESR (SPRGROUP_SYS + 13)
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#define SPR_NPC (SPRGROUP_SYS + 16)
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#define SPR_SR (SPRGROUP_SYS + 17)
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#define SPR_PPC (SPRGROUP_SYS + 18)
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@ -164,7 +169,13 @@
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#define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */
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#define SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */
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#define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */
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#define SPR_CPUCFGR_RES 0xfffffc00 /* Reserved */
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#define SPR_CPUCFGR_ND 0x00000400 /* No delay slot */
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#define SPR_CPUCFGR_AVRP 0x00000800 /* Arch. Version Register present */
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#define SPR_CPUCFGR_EVBARP 0x00001000 /* Exception Vector Base Address Register (EVBAR) present */
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#define SPR_CPUCFGR_ISRP 0x00002000 /* Implementation-Specific Registers (ISR0-7) present */
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#define SPR_CPUCFGR_AECSRP 0x00004000 /* Arithmetic Exception Control Register (AECR) and */
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/* Arithmetic Exception Status Register (AESR) presents */
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#define SPR_CPUCFGR_RES 0xffffc000 /* Reserved */
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/*
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* Bit definitions for the Debug configuration register and other
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@ -23,6 +23,13 @@
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#include <asm/cache.h>
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#include <asm/openrisc_exc.h>
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/* CPUID */
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#define OR1KSIM 0x00
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#define OR1200 0x12
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#define MOR1KX 0x01
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#define ALTOR32 0x32
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#define OR10 0x10
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static volatile int illegal_instruction;
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static void illegal_instruction_handler(void)
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@ -56,10 +63,46 @@ static int checkinstructions(void)
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return 0;
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}
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static void cpu_implementation(ulong vr2, char *string)
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{
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switch (vr2 >> 24) {
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case OR1KSIM:
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sprintf(string, "or1ksim");
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break;
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case OR1200:
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sprintf(string, "OR1200");
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break;
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case MOR1KX:
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sprintf(string, "mor1kx v%u.%u - ", (uint)((vr2 >> 16) & 0xff),
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(uint)((vr2 >> 8) & 0xff));
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if ((uint)(vr2 & 0xff) == 1)
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strcat(string, "cappuccino");
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else if ((uint)(vr2 & 0xff) == 2)
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strcat(string, "espresso");
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else if ((uint)(vr2 & 0xff) == 3)
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strcat(string, "prontoespresso");
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else
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strcat(string, "unknwown");
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break;
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case ALTOR32:
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sprintf(string, "AltOr32");
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break;
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case OR10:
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sprintf(string, "OR10");
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break;
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default:
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sprintf(string, "unknown");
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}
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}
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int checkcpu(void)
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{
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ulong upr = mfspr(SPR_UPR);
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ulong vr = mfspr(SPR_VR);
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ulong vr2 = mfspr(SPR_VR2);
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ulong iccfgr = mfspr(SPR_ICCFGR);
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ulong dccfgr = mfspr(SPR_DCCFGR);
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ulong immucfgr = mfspr(SPR_IMMUCFGR);
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@ -71,9 +114,16 @@ int checkcpu(void)
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uint ways;
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uint sets;
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char impl_str[50];
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printf("CPU: OpenRISC-%x00 (rev %d) @ %d MHz\n",
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ver, rev, (CONFIG_SYS_CLK_FREQ / 1000000));
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if (vr2) {
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cpu_implementation(vr2, impl_str);
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printf(" Implementation: %s\n", impl_str);
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}
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if (upr & SPR_UPR_DCP) {
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block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
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ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
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