Add support for multiple I2C buses
Hello,
Attached is a patch providing support for multiple I2C buses at the
command level. The second part of the patch includes an implementation
for the MPC834x CPU and MPC8349EMDS board.
/*** Note: This patch replaces ticket DNX#2006083042000018 ***/
Signed-off-by: Ben Warren <bwarren@qstreams.com>
Overview:
1. Include new 'i2c' command (based on USB implementation) using
CONFIG_I2C_CMD_TREE.
2. Allow multiple buses by defining CONFIG_I2C_MULTI_BUS. Note that
the commands to change bus number and speed are only available under the
new 'i2c' command mentioned in the first bullet.
3. The option CFG_I2C_NOPROBES has been expanded to work in multi-bus
systems. When CONFIG_I2C_MULTI_BUS is used, this option takes the form
of an array of bus-device pairs. Otherwise, it is an array of uchar.
CHANGELOG:
Added new 'i2c' master command for all I2C interaction. This is
conditionally compiled with CONFIG_I2C_CMD_TREE. New commands added for
setting I2C bus speed as well as changing the active bus if the board
has more than one (conditionally compiled with
CONFIG_I2C_MULTI_BUS). Updated NOPROBE logic to handle multiple buses.
Updated README.
regards,
Ben
This commit is contained in:
Ben Warren
Kim Phillips
parent
bed85caf87
commit
bb99ad6d82
42
README
42
README
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@ -1207,7 +1207,12 @@ The following options need to be configured:
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clock chips. See common/cmd_i2c.c for a description of the
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command line interface.
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CONFIG_HARD_I2C selects the CPM hardware driver for I2C.
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CONFIG_I2C_CMD_TREE is a recommended option that places
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all I2C commands under a single 'i2c' root command. The
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older 'imm', 'imd', 'iprobe' etc. commands are considered
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deprecated and may disappear in the future.
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CONFIG_HARD_I2C selects a hardware I2C controller.
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CONFIG_SOFT_I2C configures u-boot to use a software (aka
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bit-banging) driver instead of CPM or similar hardware
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@ -1312,6 +1317,31 @@ The following options need to be configured:
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in u-boot bd_info structure based on u-boot environment
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variable "i2cfast". (see also i2cfast)
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CONFIG_I2C_MULTI_BUS
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This option allows the use of multiple I2C buses, each of which
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must have a controller. At any point in time, only one bus is
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active. To switch to a different bus, use the 'i2c dev' command.
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Note that bus numbering is zero-based.
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CFG_I2C_NOPROBES
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This option specifies a list of I2C devices that will be skipped
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when the 'i2c probe' command is issued (or 'iprobe' using the legacy
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command). If CONFIG_I2C_MULTI_BUS is set, specify a list of bus-device
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pairs. Otherwise, specify a 1D array of device addresses
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e.g.
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#undef CONFIG_I2C_MULTI_BUS
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#define CFG_I2C_NOPROBES {0x50,0x68}
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will skip addresses 0x50 and 0x68 on a board with one I2C bus
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#define CONFIG_I2C_MULTI_BUS
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#define CFG_I2C_MULTI_NOPROBES {{0,0x50},{0,0x68},{1,0x54}}
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will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
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- SPI Support: CONFIG_SPI
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Enables SPI driver (so far only tested with
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@ -2209,6 +2239,16 @@ Low Level (hardware related) configuration options:
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CFG_POCMR2_MASK_ATTRIB: (MPC826x only)
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Overrides the default PCI memory map in cpu/mpc8260/pci.c if set.
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- CONFIG_SPD_EEPROM
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Get DDR timing information from an I2C EEPROM. Common with pluggable
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memory modules such as SODIMMs
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SPD_EEPROM_ADDRESS
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I2C address of the SPD EEPROM
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- CFG_SPD_BUS_NUM
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If SPD EEPROM is on an I2C bus other than the first one, specify here.
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Note that the value must resolve to something your driver can deal with.
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- CONFIG_ETHER_ON_FEC[12]
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Define to enable FEC[12] on a 8xx series processor.
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159
common/cmd_i2c.c
159
common/cmd_i2c.c
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@ -101,8 +101,31 @@ static uchar i2c_mm_last_chip;
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static uint i2c_mm_last_addr;
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static uint i2c_mm_last_alen;
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/* If only one I2C bus is present, the list of devices to ignore when
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* the probe command is issued is represented by a 1D array of addresses.
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* When multiple buses are present, the list is an array of bus-address
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* pairs. The following macros take care of this */
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#if defined(CFG_I2C_NOPROBES)
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#if defined(CONFIG_I2C_MULTI_BUS)
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static struct
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{
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uchar bus;
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uchar addr;
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} i2c_no_probes[] = CFG_I2C_NOPROBES;
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#define GET_BUS_NUM i2c_get_bus_num()
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#define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b))
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#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a))
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#define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr
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#else /* single bus */
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static uchar i2c_no_probes[] = CFG_I2C_NOPROBES;
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#define GET_BUS_NUM 0
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#define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */
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#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a))
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#define NO_PROBE_ADDR(i) i2c_no_probes[(i)]
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#endif /* CONFIG_MULTI_BUS */
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#define NUM_ELEMENTS_NOPROBE (sizeof(i2c_no_probes)/sizeof(i2c_no_probes[0]))
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#endif
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static int
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@ -538,14 +561,17 @@ int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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int j;
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#if defined(CFG_I2C_NOPROBES)
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int k, skip;
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#endif
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uchar bus = GET_BUS_NUM;
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#endif /* NOPROBES */
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puts ("Valid chip addresses:");
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for(j = 0; j < 128; j++) {
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#if defined(CFG_I2C_NOPROBES)
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skip = 0;
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for (k = 0; k < sizeof(i2c_no_probes); k++){
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if (j == i2c_no_probes[k]){
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for(k=0; k < NUM_ELEMENTS_NOPROBE; k++)
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{
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if(COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k))
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{
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skip = 1;
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break;
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}
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@ -561,8 +587,11 @@ int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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#if defined(CFG_I2C_NOPROBES)
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puts ("Excluded chip addresses:");
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for( k = 0; k < sizeof(i2c_no_probes); k++ )
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printf(" %02X", i2c_no_probes[k] );
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for(k=0; k < NUM_ELEMENTS_NOPROBE; k++)
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{
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if(COMPARE_BUS(bus,k))
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printf(" %02X", NO_PROBE_ADDR(k));
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}
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putc ('\n');
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#endif
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@ -873,6 +902,104 @@ int do_sdram ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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}
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#endif /* CFG_CMD_SDRAM */
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#if defined(CONFIG_I2C_CMD_TREE)
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#if defined(CONFIG_I2C_MULTI_BUS)
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int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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int bus_idx, ret=0;
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if (argc == 1) /* querying current setting */
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{
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printf("Current bus is %d\n", i2c_get_bus_num());
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}
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else
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{
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bus_idx = simple_strtoul(argv[1], NULL, 10);
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printf("Setting bus to %d\n", bus_idx);
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ret = i2c_set_bus_num(bus_idx);
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if(ret)
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{
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printf("Failure changing bus number (%d)\n", ret);
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}
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}
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return ret;
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}
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#endif /* CONFIG_I2C_MULTI_BUS */
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int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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int speed, ret=0;
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if (argc == 1) /* querying current speed */
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{
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printf("Current bus speed=%d\n", i2c_get_bus_speed());
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}
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else
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{
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speed = simple_strtoul(argv[1], NULL, 10);
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printf("Setting bus speed to %d Hz\n", speed);
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ret = i2c_set_bus_speed(speed);
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if(ret)
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{
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printf("Failure changing bus speed (%d)\n", ret);
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}
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}
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return ret;
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}
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int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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#if defined(CONFIG_I2C_MULTI_BUS)
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if(!strncmp(argv[1], "de", 2))
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{
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return do_i2c_bus_num(cmdtp, flag, --argc, ++argv);
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}
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#endif /* CONFIG_I2C_MULTI_BUS */
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if(!strncmp(argv[1], "sp", 2))
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{
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return do_i2c_bus_speed(cmdtp, flag, --argc, ++argv);
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}
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if(!strncmp(argv[1], "md", 2))
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{
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return do_i2c_md(cmdtp, flag, --argc, ++argv);
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}
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if(!strncmp(argv[1], "mm", 2))
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{
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return do_i2c_mm(cmdtp, flag, --argc, ++argv);
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}
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if(!strncmp(argv[1], "mw", 2))
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{
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return do_i2c_mw(cmdtp, flag, --argc, ++argv);
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}
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if(!strncmp(argv[1], "nm", 2))
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{
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return do_i2c_nm(cmdtp, flag, --argc, ++argv);
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}
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if(!strncmp(argv[1], "cr", 2))
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{
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return do_i2c_crc(cmdtp, flag, --argc, ++argv);
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}
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if(!strncmp(argv[1], "pr", 2))
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{
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return do_i2c_probe(cmdtp, flag, --argc, ++argv);
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}
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if(!strncmp(argv[1], "lo", 2))
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{
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return do_i2c_loop(cmdtp, flag, --argc, ++argv);
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}
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#if (CONFIG_COMMANDS & CFG_CMD_SDRAM)
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if(!strncmp(argv[1], "sd", 2))
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{
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return do_sdram(cmdtp, flag, --argc, ++argv);
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}
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#endif /* CFG_CMD_SDRAM */
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else
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{
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printf ("Usage:\n%s\n", cmdtp->usage);
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}
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return 0;
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}
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#endif /* CONFIG_I2C_CMD_TREE */
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/***************************************************/
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@ -930,4 +1057,26 @@ U_BOOT_CMD(
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" (valid chip values 50..57)\n"
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);
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#endif
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#if defined(CONFIG_I2C_CMD_TREE)
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U_BOOT_CMD(
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i2c, 6, 1, do_i2c,
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"i2c - I2C sub-system\n",
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#if defined(CONFIG_I2C_MULTI_BUS)
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"dev [dev] - show or set current I2C bus\n"
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#endif /* CONFIG_I2C_MULTI_BUS */
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"i2c speed [speed] - show or set I2C bus speed\n"
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"i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
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"i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
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"i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
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"i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
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"i2c crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
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"i2c probe - show devices on the I2C bus\n"
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"i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
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#if (CONFIG_COMMANDS & CFG_CMD_SDRAM)
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"i2c sdram chip - print SDRAM configuration information\n"
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#endif /* CFG_CMD_SDRAM */
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);
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#endif /* CONFIG_I2C_CMD_TREE */
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#endif /* CFG_CMD_I2C */
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@ -82,4 +82,49 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
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uchar i2c_reg_read (uchar chip, uchar reg);
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void i2c_reg_write(uchar chip, uchar reg, uchar val);
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/*
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* Functions for setting the current I2C bus and its speed
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*/
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/*
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* i2c_set_bus_num:
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*
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* Change the active I2C bus. Subsequent read/write calls will
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* go to this one.
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*
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* bus - bus index, zero based
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*
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* Returns: 0 on success, not 0 on failure
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*
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*/
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int i2c_set_bus_num(uchar bus);
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/*
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* i2c_get_bus_num:
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*
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* Returns index of currently active I2C bus. Zero-based.
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*/
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uchar i2c_get_bus_num(void);
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/*
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* i2c_set_bus_speed:
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*
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* Change the speed of the active I2C bus
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*
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* speed - bus speed in Hz
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*
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* Returns: 0 on success, not 0 on failure
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*
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*/
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int i2c_set_bus_speed(int);
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/*
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* i2c_get_bus_speed:
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*
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* Returns speed of currently active I2C bus in Hz
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*/
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int i2c_get_bus_speed(void);
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#endif /* _I2C_H_ */
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