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arm: move __mmu_cache_flush to bare_init section 

Instead of having seperate cache flush functions in the startup code
we want to call the generic functions. To accomplish this they have
to be in the bare_init section.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer 2010-04-16 15:46:53 +02:00
parent 64a6eb6a38
commit bd9e5ca89e
4 changed files with 9 additions and 0 deletions
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2
arch/arm/cpu/cache-armv4.S
View File

@ -41,6 +41,7 @@ ENTRY(__mmu_cache_off)
mov pc, lr
ENDPROC(__mmu_cache_off)
.section ".text_bare_init.text"
ENTRY(__mmu_cache_flush)
mrc p15, 0, r6, c0, c0 @ get processor ID
mov r2, #64*1024 @ default: 32K dcache size (*2)
@ -73,6 +74,7 @@ no_cache_id:
mov pc, lr
ENDPROC(__mmu_cache_flush)
.section ".text.text"
/*
* dma_inv_range(start, end)
*

2
arch/arm/cpu/cache-armv5.S
View File

@ -41,6 +41,7 @@ ENTRY(__mmu_cache_off)
mov pc, lr
ENDPROC(__mmu_cache_off)
.section ".text_bare_init.text"
ENTRY(__mmu_cache_flush)
1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
bne 1b
@ -48,6 +49,7 @@ ENTRY(__mmu_cache_flush)
mcr p15, 0, r0, c7, c10, 4 @ drain WB
mov pc, lr
ENDPROC(__mmu_cache_flush)
.section ".text.text"
/*
* dma_inv_range(start, end)

3
arch/arm/cpu/cache-armv6.S
View File

@ -31,6 +31,7 @@ __common_mmu_cache_on:
mrc p15, 0, r0, c1, c0, 0 @ and read it back to
sub pc, lr, r0, lsr #32 @ properly flush pipeline
ENTRY(__mmu_cache_off)
#ifdef CONFIG_MMU
mrc p15, 0, r0, c1, c0
@ -42,6 +43,7 @@ ENTRY(__mmu_cache_off)
#endif
mov pc, lr
.section ".text_bare_init.text"
ENTRY(__mmu_cache_flush)
mov r1, #0
mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
@ -50,6 +52,7 @@ ENTRY(__mmu_cache_flush)
mcr p15, 0, r1, c7, c10, 4 @ drain WB
mov pc, lr
ENDPROC(__mmu_cache_flush)
.section ".text.text"
/*
* v6_dma_inv_range(start,end)

2
arch/arm/cpu/cache-armv7.S
View File

@ -49,6 +49,7 @@ ENTRY(__mmu_cache_off)
mov pc, r12
ENDPROC(__mmu_cache_on)
.section ".text_bare_init.text"
ENTRY(__mmu_cache_flush)
mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
@ -105,6 +106,7 @@ iflush:
mcr p15, 0, r10, c7, c5, 4 @ ISB
mov pc, lr
ENDPROC(__mmu_cache_flush)
.section ".text.text"
/*
* cache_line_size - get the cache line size from the CSIDR register