[ARM] Add MX35 support
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
b3f3ca075d
commit
bee65f0d3f
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@ -67,6 +67,10 @@ config ARCH_IMX31
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bool
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select ARCH_IMX
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config ARCH_IMX35
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bool
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select ARCH_IMX
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config ARCH_AT91RM9200
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bool
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select ARM920T
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@ -8,4 +8,5 @@ obj-$(CONFIG_ARM920T) += start-arm.o
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obj-$(CONFIG_ARM926EJS) += start-arm.o
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obj-$(CONFIG_ARMCORTEXA8) += start-arm.o
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obj-$(CONFIG_ARCH_IMX31) += start-arm.o
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obj-$(CONFIG_ARCH_IMX35) += start-arm.o
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obj-$(CONFIG_CMD_ARM_CPUINFO) += cpuinfo.o
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@ -2,6 +2,7 @@ obj-y += clocksource.o
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obj-$(CONFIG_ARCH_IMX1) += speed-imx1.o gpio.o
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obj-$(CONFIG_ARCH_IMX27) += speed-imx27.o gpio.o imx27.o
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obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o gpio-imx31.o
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obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o gpio-imx35.o
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obj-$(CONFIG_IMX_CLKO) += clko.o
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obj-y += speed.o
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@ -0,0 +1,27 @@
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/*
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* (C) 2007, Sascha Hauer <sha@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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void imx_gpio_mode(unsigned long mode)
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{
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writel((mode >> 16) & 0xff, IMX_IOMUXC_BASE + (mode & 0xffff));
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}
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@ -0,0 +1,162 @@
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <init.h>
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unsigned long imx_get_mpllclk(void)
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{
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ulong mpctl = readl(IMX_CCM_BASE + CCM_MPCTL);
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return imx_decode_pll(mpctl, CONFIG_MX35_HCLK_FREQ);
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}
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unsigned long imx_get_ppllclk(void)
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{
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ulong ppctl = readl(IMX_CCM_BASE + CCM_PPCTL);
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return imx_decode_pll(ppctl, CONFIG_MX35_HCLK_FREQ);
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}
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struct arm_ahb_div {
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unsigned char arm, ahb, sel;
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};
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static struct arm_ahb_div clk_consumer[] = {
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{ .arm = 1, .ahb = 4, .sel = 0},
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{ .arm = 1, .ahb = 3, .sel = 1},
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{ .arm = 2, .ahb = 2, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 4, .ahb = 1, .sel = 0},
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{ .arm = 1, .ahb = 5, .sel = 0},
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{ .arm = 1, .ahb = 8, .sel = 0},
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{ .arm = 1, .ahb = 6, .sel = 1},
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{ .arm = 2, .ahb = 4, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 4, .ahb = 2, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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};
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static struct arm_ahb_div clk_automotive[] = {
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{ .arm = 1, .ahb = 3, .sel = 0},
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{ .arm = 1, .ahb = 2, .sel = 1},
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{ .arm = 2, .ahb = 1, .sel = 1},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 1, .ahb = 6, .sel = 0},
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{ .arm = 1, .ahb = 4, .sel = 1},
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{ .arm = 2, .ahb = 2, .sel = 1},
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{ .arm = 0, .ahb = 0, .sel = 0},
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};
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unsigned long imx_get_armclk(void)
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{
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unsigned long pdr0 = readl(IMX_CCM_BASE + CCM_PDR0);
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struct arm_ahb_div *aad;
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unsigned long fref = imx_get_mpllclk();
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if (pdr0 & PDR0_AUTO_CON) {
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/* consumer path is selected */
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aad = &clk_consumer[(pdr0 >> 16) & 0xf];
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if (aad->sel)
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fref = fref * 2 / 3;
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} else {
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/* auto path is selected */
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aad = &clk_automotive[(pdr0 >> 9) & 0x7];
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if (aad->sel)
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fref = fref * 3 / 4;
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}
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return fref / aad->arm;
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}
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unsigned long imx_get_ahbclk(void)
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{
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unsigned long pdr0 = readl(IMX_CCM_BASE + CCM_PDR0);
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struct arm_ahb_div *aad;
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unsigned long fref = imx_get_mpllclk();
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if (pdr0 & PDR0_AUTO_CON)
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/* consumer path is selected */
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aad = &clk_consumer[(pdr0 >> 16) & 0xf];
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else
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/* auto path is selected */
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aad = &clk_automotive[(pdr0 >> 9) & 0x7];
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return fref / aad->ahb;
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}
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unsigned long imx_get_ipgclk(void)
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{
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ulong clk = imx_get_ahbclk();
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return clk >> 1;
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}
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static unsigned long get_3_3_div(unsigned long in)
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{
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return (((in >> 3) & 0x7) + 1) * ((in & 0x7) + 1);
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}
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unsigned long imx_get_perclk1(void)
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{
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ulong pdr0 = readl(IMX_CCM_BASE + CCM_PDR0);
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ulong pdr4 = readl(IMX_CCM_BASE + CCM_PDR4);
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ulong div;
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ulong fref;
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if (pdr0 & PDR0_PER_SEL) {
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/* perclk from arm high frequency clock and synched with AHB clki */
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fref = imx_get_armclk();
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div = get_3_3_div((pdr4 >> 16));
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} else {
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/* perclk from AHB divided clock */
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fref = imx_get_ahbclk();
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div = ((pdr0 >> 12) & 0x7) + 1; //FIXME check datasheet 111 -> 7 ?
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}
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return fref / div;
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}
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unsigned long imx_get_uartclk(void)
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{
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unsigned long pdr3 = readl(IMX_CCM_BASE + CCM_PDR3);
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unsigned long pdr4 = readl(IMX_CCM_BASE + CCM_PDR4);
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unsigned long div = get_3_3_div(pdr4 >> 10);
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if (pdr3 & (1 << 14))
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return imx_get_armclk() / div;
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else
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return imx_get_ppllclk() / div;
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}
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static int imx_dump_clocks(void)
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{
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printf("mpll: %10d Hz\n", imx_get_mpllclk());
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printf("ppll: %10d Hz\n", imx_get_ppllclk());
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printf("arm: %10d Hz\n", imx_get_armclk());
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printf("perclk1: %10d Hz\n", imx_get_perclk1());
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printf("ahb: %10d Hz\n", imx_get_ahbclk());
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printf("ipg: %10d Hz\n", imx_get_ipgclk());
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printf("uart: %10d Hz\n", imx_get_uartclk());
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return 0;
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}
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late_initcall(imx_dump_clocks);
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@ -45,6 +45,8 @@
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# include <asm/arch/imx27-regs.h>
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#elif defined CONFIG_ARCH_IMX31
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# include <asm/arch/imx31-regs.h>
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#elif defined CONFIG_ARCH_IMX35
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# include <asm/arch/imx35-regs.h>
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#else
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# error "unknown i.MX soc type"
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#endif
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@ -0,0 +1,275 @@
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/*
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* (c) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_ARCH_MX35_REGS_H
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#define __ASM_ARCH_MX35_REGS_H
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/*
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* sanity check
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*/
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#ifndef _IMX_REGS_H
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# error "Please do not include directly. Use imx-regs.h instead."
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#endif
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#define IMX_L2CC_BASE 0x30000000
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#define IMX_UART1_BASE 0x43F90000
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#define IMX_UART2_BASE 0x43F94000
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#define IMX_TIM1_BASE 0x53F90000
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#define IMX_IOMUXC_BASE 0x43FAC000
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#define IMX_WDT_BASE 0x53FDC000
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#define IMX_MAX_BASE 0x43F04000
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#define IMX_ESD_BASE 0xb8001000
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#define IMX_AIPS1_BASE 0x43F00000
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#define IMX_AIPS2_BASE 0x53F00000
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#define IMX_CCM_BASE 0x53F80000
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#define IMX_IIM_BASE 0x53FF0000
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#define IMX_M3IF_BASE 0xB8003000
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#define IMX_NAND_BASE 0xBB000000
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/*
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* Clock Controller Module (CCM)
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*/
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#define CCM_CCMR 0x00
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#define CCM_PDR0 0x04
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#define CCM_PDR1 0x08
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#define CCM_PDR2 0x0C
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#define CCM_PDR3 0x10
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#define CCM_PDR4 0x14
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#define CCM_RCSR 0x18
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#define CCM_MPCTL 0x1C
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#define CCM_PPCTL 0x20
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#define CCM_ACMR 0x24
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#define CCM_COSR 0x28
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#define CCM_CGR0 0x2C
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#define CCM_CGR1 0x30
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#define CCM_CGR2 0x34
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#define CCM_CGR3 0x38
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#define PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9)
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#define PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12)
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#define PDR0_CON_MUX_DIV(x) (((x) & 0xf) << 16)
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#define PDR0_HSP_PODF(x) (((x) & 0x3) << 20)
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#define PDR0_AUTO_CON (1 << 0)
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#define PDR0_PER_SEL (1 << 26)
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/*
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* Adresses and ranges of the external chip select lines
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*/
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#define IMX_CS0_BASE 0xA0000000
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#define IMX_CS0_RANGE (128 * 1024 * 1024)
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#define IMX_CS1_BASE 0xA8000000
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#define IMX_CS1_RANGE (128 * 1024 * 1024)
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#define IMX_CS2_BASE 0xB0000000
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#define IMX_CS2_RANGE (32 * 1024 * 1024)
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#define IMX_CS3_BASE 0xB2000000
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#define IMX_CS3_RANGE (32 * 1024 * 1024)
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#define IMX_CS4_BASE 0xB4000000
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#define IMX_CS4_RANGE (32 * 1024 * 1024)
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#define IMX_CS5_BASE 0xB6000000
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#define IMX_CS5_RANGE (32 * 1024 * 1024)
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#define IMX_SDRAM_CS0 0x80000000
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#define IMX_SDRAM_CS1 0x90000000
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#define WEIM_BASE 0xb8002000
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#define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
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#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
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#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)
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/*
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* Definitions for the clocksource driver
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*
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* These defines are using the i.MX1/27 notation
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* to reuse the clocksource code for these CPUs
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* on the i.MX35
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*/
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/* Part 1: Registers */
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#define GPT_TCTL 0x00
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#define GPT_TPRER 0x04
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#define GPT_TCMP 0x10
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#define GPT_TCR 0x1c
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#define GPT_TCN 0x24
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#define GPT_TSTAT 0x08
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/* Part 2: Bitfields */
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#define TCTL_SWR (1<<15) /* Software reset */
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#define TCTL_FRR (1<<9) /* Freerun / restart */
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#define TCTL_CAP (3<<6) /* Capture Edge */
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#define TCTL_OM (1<<5) /* output mode */
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#define TCTL_IRQEN (1<<4) /* interrupt enable */
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#define TCTL_CLKSOURCE (6) /* Clock source bit position */
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#define TCTL_TEN (1) /* Timer enable */
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#define TPRER_PRES (0xff) /* Prescale */
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#define TSTAT_CAPT (1<<1) /* Capture event */
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#define TSTAT_COMP (1) /* Compare event */
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/*
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* Watchdog Registers
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*/
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#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
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#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */
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#define WSTR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Status Register */
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/* important definition of some bits of WCR */
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#define WCR_WDE 0x04
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/* bits in the SW_MUX_CTL registers */
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#define MUX_CTL_ALT0 (0 << 0)
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#define MUX_CTL_ALT1 (1 << 0)
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#define MUX_CTL_ALT2 (2 << 0)
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#define MUX_CTL_ALT3 (3 << 0)
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#define MUX_CTL_ALT4 (4 << 0)
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#define MUX_CTL_ALT5 (5 << 0)
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#define MUX_CTL_ALT6 (6 << 0)
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#define MUX_CTL_ALT7 (7 << 0)
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#define MUX_CTL_PAD_SION (1 << 4)
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/* Register offsets based on IOMUXC_BASE */
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#define MUX_CTL_COMPARE 0x8
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#define MUX_CTL_WDOG_RST 0xc
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#define MUX_CTL_I2C1_CLK 0x110
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#define MUX_CTL_I2C1_DAT 0x114
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#define MUX_CTL_I2C2_CLK 0x118
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#define MUX_CTL_STXD5 0x130
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#define MUX_CTL_SRXD5 0x134
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#define MUX_CTL_SCK5 0x138
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#define MUX_CTL_STXFS5 0x13c
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#define MUX_CTL_TX5_RX0 0x158
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#define MUX_CTL_TX4_RX1 0x15c
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#define MUX_CTL_CSPI1_MOSI 0x170
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#define MUX_CTL_CSPI1_MISO 0x174
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#define MUX_CTL_CSPI1_SS0 0x178
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#define MUX_CTL_CSPI1_SS1 0x17c
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#define MUX_CTL_CSPI1_SCLK 0x180
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#define MUX_CTL_CSPI1_SPI_RDY 0x184
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#define MUX_CTL_RXD1 0x188
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#define MUX_CTL_TXD1 0x18c
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#define MUX_CTL_RTS1 0x190
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#define MUX_CTL_CTS1 0x194
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#define MUX_CTL_ATA_RESET_B 0x274
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#define MUX_CTL_FEC_TX_CLK 0x2e0
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#define MUX_CTL_FEC_RX_CLK 0x2e4
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#define MUX_CTL_FEC_RX_DV 0x2e8
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#define MUX_CTL_FEC_COL 0x2ec
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#define MUX_CTL_FEC_RDATA0 0x2f0
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#define MUX_CTL_FEC_TDATA0 0x2f4
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#define MUX_CTL_FEC_TX_EN 0x2f8
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#define MUX_CTL_FEC_MDC 0x2fc
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#define MUX_CTL_FEC_MDIO 0x300
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#define MUX_CTL_FEC_TX_ERR 0x304
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#define MUX_CTL_FEC_RX_ERR 0x308
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#define MUX_CTL_FEC_CRS 0x30c
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#define MUX_CTL_FEC_RDATA1 0x310
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#define MUX_CTL_FEC_TDATA1 0x314
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#define MUX_CTL_FEC_RDATA2 0x318
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#define MUX_CTL_FEC_TDATA2 0x31c
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#define MUX_CTL_FEC_RDATA3 0x320
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#define MUX_CTL_FEC_TDATA3 0x324
|
||||
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#define PAD_CTL_COMPARE 0x32c
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#define PAD_CTL_WDOG_RST 0x330
|
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|
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#define PAD_CTL_I2C1_CLK 0x554
|
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#define PAD_CTL_I2C1_DAT 0x558
|
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#define PAD_CTL_I2C2_CLK 0x55c
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|
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#define PAD_CTL_STXD5 0x574
|
||||
#define PAD_CTL_SRXD5 0x578
|
||||
#define PAD_CTL_SCK5 0x57c
|
||||
#define PAD_CTL_STXFS5 0x580
|
||||
|
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#define PAD_CTL_TX5_RX0 0x59c
|
||||
#define PAD_CTL_TX4_RX1 0x5a0
|
||||
|
||||
#define PAD_CTL_CSPI1_MOSI 0x5b4
|
||||
#define PAD_CTL_CSPI1_MISO 0x5b8
|
||||
#define PAD_CTL_CSPI1_SS0 0x5bc
|
||||
#define PAD_CTL_CSPI1_SS1 0x5c0
|
||||
#define PAD_CTL_CSPI1_SCLK 0x5c4
|
||||
#define PAD_CTL_CSPI1_SPI_RDY 0x5c8
|
||||
#define PAD_CTL_RXD1 0x5cc
|
||||
#define PAD_CTL_TXD1 0x5d0
|
||||
#define PAD_CTL_RTS1 0x5d4
|
||||
#define PAD_CTL_CTS1 0x5d8
|
||||
|
||||
#define PAD_CTL_ATA_RESET_B 0x6d8
|
||||
|
||||
#define PAD_CTL_FEC_TX_CLK 0x744
|
||||
#define PAD_CTL_FEC_RX_CLK 0x748
|
||||
#define PAD_CTL_FEC_RX_DV 0x74c
|
||||
#define PAD_CTL_FEC_COL 0x750
|
||||
#define PAD_CTL_FEC_RDATA0 0x754
|
||||
#define PAD_CTL_FEC_TDATA0 0x758
|
||||
#define PAD_CTL_FEC_TX_EN 0x75c
|
||||
#define PAD_CTL_FEC_MDC 0x760
|
||||
#define PAD_CTL_FEC_MDIO 0x764
|
||||
#define PAD_CTL_FEC_TX_ERR 0x768
|
||||
#define PAD_CTL_FEC_RX_ERR 0x76c
|
||||
#define PAD_CTL_FEC_CRS 0x770
|
||||
#define PAD_CTL_FEC_RDATA1 0x774
|
||||
#define PAD_CTL_FEC_TDATA1 0x778
|
||||
#define PAD_CTL_FEC_RDATA2 0x77c
|
||||
#define PAD_CTL_FEC_TDATA2 0x780
|
||||
#define PAD_CTL_FEC_RDATA3 0x784
|
||||
#define PAD_CTL_FEC_TDATA3 0x788
|
||||
|
||||
/* The modes a specific pin can be in
|
||||
* these macros can be used in mx31_gpio_mux() and have the form
|
||||
* MUX_[contact name]__[pin function]
|
||||
*/
|
||||
|
||||
#define MUX_RXD1_UART1_RXD_MUX ((MUX_CTL_ALT0 << 16) | MUX_CTL_RXD1)
|
||||
#define MUX_TXD1_UART1_TXD_MUX ((MUX_CTL_ALT0 << 16) | MUX_CTL_TXD1)
|
||||
#define MUX_RTS1_UART1_RTS_B ((MUX_CTL_ALT0 << 16) | MUX_CTL_RTS1)
|
||||
#define MUX_RTS1_UART1_CTS_B ((MUX_CTL_ALT0 << 16) | MUX_CTL_CTS1)
|
||||
|
||||
#define MUX_I2C1_CLK_I2C1_SLC ((MUX_CTL_ALT0 << 16) | MUX_CTL_I2C1_CLK)
|
||||
#define MUX_I2C1_DAT_I2C1_SDA ((MUX_CTL_ALT0 << 16) | MUX_CTL_I2C1_DAT)
|
||||
|
||||
#define MUX_FEC_TX_CLK_FEC_TX_CLK ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_TX_CLK)
|
||||
#define MUX_FEC_RX_CLK_FEC_RX_CLK ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_RX_CLK)
|
||||
#define MUX_FEC_RX_DV_FEC_RX_DV ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_RX_DV)
|
||||
#define MUX_FEC_COL_FEC_COL ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_COL)
|
||||
#define MUX_FEC_TX_EN_FEC_TX_EN ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_TX_EN)
|
||||
#define MUX_FEC_MDC_FEC_MDC ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_MDC)
|
||||
#define MUX_FEC_MDIO_FEC_MDIO ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_MDIO)
|
||||
#define MUX_FEC_TX_ERR_FEC_TX_ERR ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_TX_ERR)
|
||||
#define MUX_FEC_RX_ERR_FEC_RX_ERR ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_RX_ERR)
|
||||
#define MUX_FEC_CRS_FEC_CRS ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_CRS)
|
||||
#define MUX_FEC_RDATA0_FEC_RDATA0 ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_RDATA0)
|
||||
#define MUX_FEC_TDATA0_FEC_TDATA0 ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_TDATA0)
|
||||
#define MUX_FEC_RDATA1_FEC_RDATA1 ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_RDATA1)
|
||||
#define MUX_FEC_TDATA1_FEC_TDATA1 ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_TDATA1)
|
||||
#define MUX_FEC_RDATA2_FEC_RDATA2 ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_RDATA2)
|
||||
#define MUX_FEC_TDATA2_FEC_TDATA2 ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_TDATA2)
|
||||
#define MUX_FEC_RDATA3_FEC_RDATA3 ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_RDATA3)
|
||||
#define MUX_FEC_TDATA3_FEC_TDATA3 ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_TDATA3)
|
||||
|
||||
#endif /* __ASM_ARCH_MX35_REGS_H */
|
||||
|
||||
Loading…
Reference in New Issue