From bf04eedf69d8842f0ba1e88bebce214d84cd8c04 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20B=C3=A9nard?= Date: Tue, 10 Sep 2013 10:15:31 +0200 Subject: [PATCH] i.MX28: unbreak ethernet MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit since the switch to common clock, ethernet driver doesn't works and and access to the network leads to : eth0: Read MDIO failed... unable to handle NULL pointer dereference at address 0x000000c7 The problem is that bit 31 (SLEEP) of register HW_CLKCTRL_ENET is kept to its default value (1) which means : "put Ethernet block in sleep mode. CLK_H_MAC0(1), CLK_H_MAC0(1)_S, and CLK_ENET0(1)_TX are gated off. Ethernet can be wakeup remotely in sleep mode" In that case the FEC don't get its clock. This patch fix the problem by toggling this bit when FEC's clock is enabled. Tested on i.MX28EVK. Signed-off-by: Eric Bénard Signed-off-by: Sascha Hauer --- drivers/clk/mxs/clk-imx28.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c index ed38d4b78..05b3c2a04 100644 --- a/drivers/clk/mxs/clk-imx28.c +++ b/drivers/clk/mxs/clk-imx28.c @@ -68,7 +68,7 @@ enum imx28_clk { emi_xtal, lcdif_div, etm_div, ptp, saif0_div, saif1_div, clk32k_div, rtc, lradc, spdif_div, clk32k, pwm, uart, ssp0, ssp1, ssp2, ssp3, gpmi, spdif, emi, saif0, saif1, lcdif, etm, - fec, can0, can1, usb0, usb1, usb0_phy, usb1_phy, enet_out, + fec_sleep, fec, can0, can1, usb0, usb1, usb0_phy, usb1_phy, enet_out, lcdif_comp, clk_max }; @@ -124,7 +124,8 @@ int __init mx28_clocks_init(void __iomem *regs) clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31); clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", LCDIF, 31); clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31); - clks[fec] = mxs_clk_gate("fec", "hbus", ENET, 30); + clks[fec_sleep] = mxs_clk_gate("fec_sleep", "hbus", ENET, 31); + clks[fec] = mxs_clk_gate("fec", "fec_sleep", ENET, 30); clks[usb0_phy] = mxs_clk_gate("usb0_phy", "pll0", PLL0CTRL0, 18); clks[usb1_phy] = mxs_clk_gate("usb1_phy", "pll1", PLL1CTRL0, 18); clks[enet_out] = clk_gate("enet_out", "pll2", ENET, 18);