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Eukrea CPUIMX27 : add SDRAM size choice 

Add a menu entry and proper settings for 128MB and 256MB
RAM size.

Signed-off-by: Eric Benard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Eric Benard 2009-10-22 16:46:12 +02:00 committed by Sascha Hauer
parent ce96b9c05e
commit bf33c69764
3 changed files with 30 additions and 4 deletions
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9
arch/arm/mach-imx/Kconfig
View File

@ -249,6 +249,15 @@ config PCM037_SDRAM_BANK1_256MB
endchoice
endif
if MACH_EUKREA_CPUIMX27
choice
prompt "SDRAM Size"
config EUKREA_CPUIMX27_SDRAM_128MB
bool "128 MB"
config EUKREA_CPUIMX27_SDRAM_256MB
bool "256 MB"
endchoice
endif
endmenu
menu "i.MX specific settings "

8
board/eukrea_cpuimx27/eukrea_cpuimx27.c
View File

@ -52,10 +52,16 @@ static struct memory_platform_data ram_pdata = {
.flags = DEVFS_RDWR,
};
#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB
#define SDRAM0 256
#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB
#define SDRAM0 128
#endif
static struct device_d sdram_dev = {
.name = "mem",
.map_base = 0xa0000000,
.size = 128 * 1024 * 1024,
.size = SDRAM0 * 1024 * 1024,
.platform_data = &ram_pdata,
};

17
board/eukrea_cpuimx27/lowlevel_init.S
View File

@ -6,14 +6,21 @@
ldr r1, =val; \
str r1, [r0];
#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB
#define ROWS0 ESDCTL_ROW14
#define CFG0 0x00695729
#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB
#define ROWS0 ESDCTL_ROW13
#define CFG0 0x00395B28
#endif
#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
#define ESDCTL0_VAL (ESDCTL0_SDE | ROWS0 | ESDCTL0_COL10)
.macro sdram_init
/*
* DDR on CSD0
*/
writel(0x00000008, ESDMISC) /* Enable DDR SDRAM operation */
writel(0x0000000C, ESDMISC) /* Enable DDR SDRAM operation */
writel(0x55555555, DSCR(3)) /* Set the driving strength */
writel(0x55555555, DSCR(5))
@ -22,7 +29,7 @@
writel(0x15555555, DSCR(8))
writel(0x00000004, ESDMISC) /* Initial reset */
writel(0x0039572A, ESDCFG0)
writel(CFG0, ESDCFG0)
writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0) /* precharge CSD0 all banks */
writel(0x00000000, 0xA0000F00) /* CSD0 precharge address (A10 = 1) */
@ -40,7 +47,11 @@
ldr r0, =0xA0000033
mov r1, #0xda
strb r1, [r0]
#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB
ldr r0, =0xA2000000
#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB
ldr r0, =0xA1000000
#endif
mov r1, #0xff
strb r1, [r0]
writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0)