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dts: update to v4.9-rc1 

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer 2016-10-18 10:10:24 +02:00
parent 834f6bf5e5
commit bfbf18d991
832 changed files with 34648 additions and 7411 deletions
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98
dts/Bindings/arm/altera/socfpga-eccmgr.txt
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@ -90,6 +90,47 @@ Required Properties:
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
NAND FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-nand-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent NAND node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
DMA FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-dma-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent DMA node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
USB FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-usb-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent USB node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
QSPI FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-qspi-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent QSPI node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
SDMMC FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-sdmmc-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent SD/MMC node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order for port A, and then single bit error interrupt,
then double bit error interrupt in this order for port B.
Example:
eccmgr: eccmgr@ffd06000 {
@ -132,4 +173,61 @@ Example:
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
<37 IRQ_TYPE_LEVEL_HIGH>;
};
nand-buf-ecc@ff8c2000 {
compatible = "altr,socfpga-nand-ecc";
reg = <0xff8c2000 0x400>;
altr,ecc-parent = <&nand>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>,
<43 IRQ_TYPE_LEVEL_HIGH>;
};
nand-rd-ecc@ff8c2400 {
compatible = "altr,socfpga-nand-ecc";
reg = <0xff8c2400 0x400>;
altr,ecc-parent = <&nand>;
interrupts = <13 IRQ_TYPE_LEVEL_HIGH>,
<45 IRQ_TYPE_LEVEL_HIGH>;
};
nand-wr-ecc@ff8c2800 {
compatible = "altr,socfpga-nand-ecc";
reg = <0xff8c2800 0x400>;
altr,ecc-parent = <&nand>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
<44 IRQ_TYPE_LEVEL_HIGH>;
};
dma-ecc@ff8c8000 {
compatible = "altr,socfpga-dma-ecc";
reg = <0xff8c8000 0x400>;
altr,ecc-parent = <&pdma>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
<42 IRQ_TYPE_LEVEL_HIGH>;
usb0-ecc@ff8c8800 {
compatible = "altr,socfpga-usb-ecc";
reg = <0xff8c8800 0x400>;
altr,ecc-parent = <&usb0>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
<34 IRQ_TYPE_LEVEL_HIGH>;
};
qspi-ecc@ff8c8400 {
compatible = "altr,socfpga-qspi-ecc";
reg = <0xff8c8400 0x400>;
altr,ecc-parent = <&qspi>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
<46 IRQ_TYPE_LEVEL_HIGH>;
};
sdmmc-ecc@ff8c2c00 {
compatible = "altr,socfpga-sdmmc-ecc";
reg = <0xff8c2c00 0x400>;
altr,ecc-parent = <&mmc>;
interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
<47 IRQ_TYPE_LEVEL_HIGH>,
<16 IRQ_TYPE_LEVEL_HIGH>,
<48 IRQ_TYPE_LEVEL_HIGH>;
};
};

6
dts/Bindings/arm/arch_timer.txt
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@ -25,6 +25,12 @@ to deliver its interrupts via SPIs.
- always-on : a boolean property. If present, the timer is powered through an
always-on power domain, therefore it never loses context.
- fsl,erratum-a008585 : A boolean property. Indicates the presence of
QorIQ erratum A-008585, which says that reading the counter is
unreliable unless the same value is returned by back-to-back reads.
This also affects writes to the tval register, due to the implicit
counter read.
** Optional properties:
- arm,cpu-registers-not-fw-configured : Firmware does not initialize

4
dts/Bindings/arm/bcm/brcm,bcm2835.txt
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@ -38,6 +38,10 @@ Raspberry Pi Compute Module
Required root node properties:
compatible = "raspberrypi,compute-module", "brcm,bcm2835";
Raspberry Pi Zero
Required root node properties:
compatible = "raspberrypi,model-zero", "brcm,bcm2835";
Generic BCM2835 board
Required root node properties:
compatible = "brcm,bcm2835";

4
dts/Bindings/arm/davinci.txt
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@ -5,6 +5,10 @@ DA850/OMAP-L138/AM18x Evaluation Module (EVM) board
Required root node properties:
- compatible = "ti,da850-evm", "ti,da850";
DA850/OMAP-L138/AM18x L138/C6748 Development Kit (LCDK) board
Required root node properties:
- compatible = "ti,da850-lcdk", "ti,da850";
EnBW AM1808 based CMC board
Required root node properties:
- compatible = "enbw,cmc", "ti,da850;

39
dts/Bindings/arm/hisilicon/hisilicon.txt
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@ -175,38 +175,55 @@ Example:
};
-----------------------------------------------------------------------
Hisilicon HiP05 PCIe-SAS system controller
Hisilicon HiP05/HiP06 PCIe-SAS sub system controller
Required properties:
- compatible : "hisilicon,pcie-sas-subctrl", "syscon";
- reg : Register address and size
The HiP05 PCIe-SAS system controller is shared by PCIe and SAS controllers in
HiP05 Soc to implement some basic configurations.
The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
HiP05 or HiP06 Soc to implement some basic configurations.
Example:
/* for HiP05 PCIe-SAS system */
pcie_sas: system_controller@0xb0000000 {
/* for HiP05 PCIe-SAS sub system */
pcie_sas: system_controller@b0000000 {
compatible = "hisilicon,pcie-sas-subctrl", "syscon";
reg = <0xb0000000 0x10000>;
};
Hisilicon HiP05 PERISUB system controller
Hisilicon HiP05/HiP06 PERI sub system controller
Required properties:
- compatible : "hisilicon,hip05-perisubc", "syscon";
- compatible : "hisilicon,peri-subctrl", "syscon";
- reg : Register address and size
The HiP05 PERISUB system controller is shared by peripheral controllers in
HiP05 Soc to implement some basic configurations. The peripheral
The PERI sub system controller is shared by peripheral controllers in
HiP05 or HiP06 Soc to implement some basic configurations. The peripheral
controllers include mdio, ddr, iic, uart, timer and so on.
Example:
/* for HiP05 perisub-ctrl-c system */
/* for HiP05 sub peri system */
peri_c_subctrl: syscon@80000000 {
compatible = "hisilicon,hip05-perisubc", "syscon";
compatible = "hisilicon,peri-subctrl", "syscon";
reg = <0x0 0x80000000 0x0 0x10000>;
};
Hisilicon HiP05/HiP06 DSA sub system controller
Required properties:
- compatible : "hisilicon,dsa-subctrl", "syscon";
- reg : Register address and size
The DSA sub system controller is shared by peripheral controllers in
HiP05 or HiP06 Soc to implement some basic configurations.
Example:
/* for HiP05 dsa sub system */
pcie_sas: system_controller@a0000000 {
compatible = "hisilicon,dsa-subctrl", "syscon";
reg = <0xa0000000 0x10000>;
};
-----------------------------------------------------------------------
Hisilicon CPU controller

15
dts/Bindings/arm/marvell/armada-39x.txt
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@ -8,8 +8,19 @@ Required root node property:
- compatible: must contain "marvell,armada390"
In addition, boards using the Marvell Armada 398 SoC shall have the
following property before the previous one:
In addition, boards using the Marvell Armada 395 SoC shall have the
following property before the common "marvell,armada390" one:
Required root node property:
compatible: must contain "marvell,armada395"
Example:
compatible = "marvell,a395-gp", "marvell,armada395", "marvell,armada390";
Boards using the Marvell Armada 398 SoC shall have the following
property before the common "marvell,armada390" one:
Required root node property:

25
dts/Bindings/arm/marvell/marvell,orion5x.txt Normal file
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@ -0,0 +1,25 @@
Marvell Orion SoC Family Device Tree Bindings
---------------------------------------------
Boards with a SoC of the Marvell Orion family, eg 88f5181
* Required root node properties:
compatible: must contain "marvell,orion5x"
In addition, the above compatible shall be extended with the specific
SoC. Currently known SoC compatibles are:
"marvell,orion5x-88f5181"
"marvell,orion5x-88f5182"
And in addition, the compatible shall be extended with the specific
board. Currently known boards are:
"buffalo,lsgl"
"buffalo,lswsgl"
"buffalo,lswtgl"
"lacie,ethernet-disk-mini-v2"
"lacie,d2-network"
"marvell,rd-88f5182-nas"
"maxtor,shared-storage-2"
"netgear,wnr854t"

3
dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt
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@ -5,7 +5,8 @@ The Mediatek apmixedsys controller provides the PLLs to the system.
Required Properties:
- compatible: Should be:
- compatible: Should be one of:
- "mediatek,mt2701-apmixedsys"
- "mediatek,mt8135-apmixedsys"
- "mediatek,mt8173-apmixedsys"
- #clock-cells: Must be 1

22
dts/Bindings/arm/mediatek/mediatek,bdpsys.txt Normal file
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@ -0,0 +1,22 @@
Mediatek bdpsys controller
============================
The Mediatek bdpsys controller provides various clocks to the system.
Required Properties:
- compatible: Should be:
- "mediatek,mt2701-bdpsys", "syscon"
- #clock-cells: Must be 1
The bdpsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
Example:
bdpsys: clock-controller@1c000000 {
compatible = "mediatek,mt2701-bdpsys", "syscon";
reg = <0 0x1c000000 0 0x1000>;
#clock-cells = <1>;
};

22
dts/Bindings/arm/mediatek/mediatek,ethsys.txt Normal file
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@ -0,0 +1,22 @@
Mediatek ethsys controller
============================
The Mediatek ethsys controller provides various clocks to the system.
Required Properties:
- compatible: Should be:
- "mediatek,mt2701-ethsys", "syscon"
- #clock-cells: Must be 1
The ethsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
Example:
ethsys: clock-controller@1b000000 {
compatible = "mediatek,mt2701-ethsys", "syscon";
reg = <0 0x1b000000 0 0x1000>;
#clock-cells = <1>;
};

24
dts/Bindings/arm/mediatek/mediatek,hifsys.txt Normal file
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@ -0,0 +1,24 @@
Mediatek hifsys controller
============================
The Mediatek hifsys controller provides various clocks and reset
outputs to the system.
Required Properties:
- compatible: Should be:
- "mediatek,mt2701-hifsys", "syscon"
- #clock-cells: Must be 1
The hifsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
Example:
hifsys: clock-controller@1a000000 {
compatible = "mediatek,mt2701-hifsys", "syscon";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

3
dts/Bindings/arm/mediatek/mediatek,imgsys.txt
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@ -5,7 +5,8 @@ The Mediatek imgsys controller provides various clocks to the system.
Required Properties:
- compatible: Should be:
- compatible: Should be one of:
- "mediatek,mt2701-imgsys", "syscon"
- "mediatek,mt8173-imgsys", "syscon"
- #clock-cells: Must be 1

3
dts/Bindings/arm/mediatek/mediatek,infracfg.txt
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@ -6,7 +6,8 @@ outputs to the system.
Required Properties:
- compatible: Should be:
- compatible: Should be one of:
- "mediatek,mt2701-infracfg", "syscon"
- "mediatek,mt8135-infracfg", "syscon"
- "mediatek,mt8173-infracfg", "syscon"
- #clock-cells: Must be 1

3
dts/Bindings/arm/mediatek/mediatek,mmsys.txt
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@ -5,7 +5,8 @@ The Mediatek mmsys controller provides various clocks to the system.
Required Properties:
- compatible: Should be:
- compatible: Should be one of:
- "mediatek,mt2701-mmsys", "syscon"
- "mediatek,mt8173-mmsys", "syscon"
- #clock-cells: Must be 1

3
dts/Bindings/arm/mediatek/mediatek,pericfg.txt
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@ -6,7 +6,8 @@ outputs to the system.
Required Properties:
- compatible: Should be:
- compatible: Should be one of:
- "mediatek,mt2701-pericfg", "syscon"
- "mediatek,mt8135-pericfg", "syscon"
- "mediatek,mt8173-pericfg", "syscon"
- #clock-cells: Must be 1

3
dts/Bindings/arm/mediatek/mediatek,topckgen.txt
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@ -5,7 +5,8 @@ The Mediatek topckgen controller provides various clocks to the system.
Required Properties:
- compatible: Should be:
- compatible: Should be one of:
- "mediatek,mt2701-topckgen"
- "mediatek,mt8135-topckgen"
- "mediatek,mt8173-topckgen"
- #clock-cells: Must be 1

3
dts/Bindings/arm/mediatek/mediatek,vdecsys.txt
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@ -5,7 +5,8 @@ The Mediatek vdecsys controller provides various clocks to the system.
Required Properties:
- compatible: Should be:
- compatible: Should be one of:
- "mediatek,mt2701-vdecsys", "syscon"
- "mediatek,mt8173-vdecsys", "syscon"
- #clock-cells: Must be 1

6
dts/Bindings/arm/omap/omap.txt
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@ -180,3 +180,9 @@ Boards:
- DRA722 EVM: Software Development Board for DRA722
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"
- DM3730 Logic PD Torpedo + Wireless: Commercial System on Module with WiFi and Bluetooth
compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3"
- DM3730 Logic PD SOM-LV: Commercial System on Module with WiFi and Bluetooth
compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3"

12
dts/Bindings/arm/rockchip.txt
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@ -31,6 +31,10 @@ Rockchip platforms device tree bindings
or
- compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288";
- Firefly Firefly-RK3288 Reload board:
Required root node properties:
- compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288";
- ChipSPARK PopMetal-RK3288 board:
Required root node properties:
- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
@ -110,6 +114,14 @@ Rockchip platforms device tree bindings
- Rockchip RK3229 Evaluation board:
- compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
- Rockchip RK3288 Fennec board:
Required root node properties:
- compatible = "rockchip,rk3288-fennec", "rockchip,rk3288";
- Rockchip RK3399 evb:
Required root node properties:
- compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
- Tronsmart Orion R68 Meta
Required root node properties:
- compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368";

1
dts/Bindings/arm/samsung/pmu.txt
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@ -10,6 +10,7 @@ Properties:
- "samsung,exynos5260-pmu" - for Exynos5260 SoC.
- "samsung,exynos5410-pmu" - for Exynos5410 SoC,
- "samsung,exynos5420-pmu" - for Exynos5420 SoC.
- "samsung,exynos5433-pmu" - for Exynos5433 SoC.
- "samsung,exynos7-pmu" - for Exynos7 SoC.
second value must be always "syscon".

6
dts/Bindings/arm/shmobile.txt
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@ -49,6 +49,8 @@ Boards:
compatible = "renesas,genmai", "renesas,r7s72100"
- Gose
compatible = "renesas,gose", "renesas,r8a7793"
- H3ULCB (RTP0RC7795SKB00010S)
compatible = "renesas,h3ulcb", "renesas,r8a7795";
- Henninger
compatible = "renesas,henninger", "renesas,r8a7791"
- Koelsch (RTP0RC7791SEB00010S)
@ -63,9 +65,13 @@ Boards:
compatible = "renesas,marzen", "renesas,r8a7779"
- Porter (M2-LCDP)
compatible = "renesas,porter", "renesas,r8a7791"
- RSKRZA1 (YR0K77210C000BE)
compatible = "renesas,rskrza1", "renesas,r7s72100"
- Salvator-X (RTP0RC7795SIPB0010S)
compatible = "renesas,salvator-x", "renesas,r8a7795";
- Salvator-X
compatible = "renesas,salvator-x", "renesas,r8a7796";
- SILK (RTP0RC7794LCB00011S)
compatible = "renesas,silk", "renesas,r8a7794"
- Wheat
compatible = "renesas,wheat", "renesas,r8a7792"

1
dts/Bindings/arm/sunxi.txt
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@ -14,3 +14,4 @@ using one of the following compatible strings:
allwinner,sun8i-a83t
allwinner,sun8i-h3
allwinner,sun9i-a80
nextthing,gr8

6
dts/Bindings/arm/technologic.txt
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@ -4,3 +4,9 @@ Technologic Systems Platforms Device Tree Bindings
TS-4800 board
Required root node properties:
- compatible = "technologic,imx51-ts4800", "fsl,imx51";
TS-4900 is a System-on-Module based on the Freescale i.MX6 System-on-Chip.
It can be mounted on a carrier board providing additional peripheral connectors.
Required root node properties:
- compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl"
- compatible = "technologic,imx6q-ts4900", "fsl,imx6q"

24
dts/Bindings/arm/zte.txt
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@ -13,3 +13,27 @@ Low power management required properties:
Bus matrix required properties:
- compatible = "zte,zx-bus-matrix"
---------------------------------------
- ZX296718 SoC:
Required root node properties:
- compatible = "zte,zx296718"
ZX296718 EVB board:
- "zte,zx296718-evb"
System management required properties:
- compatible = "zte,zx296718-aon-sysctrl"
- compatible = "zte,zx296718-sysctrl"
Example:
aon_sysctrl: aon-sysctrl@116000 {
compatible = "zte,zx296718-aon-sysctrl", "syscon";
reg = <0x116000 0x1000>;
};
sysctrl: sysctrl@1463000 {
compatible = "zte,zx296718-sysctrl", "syscon";
reg = <0x1463000 0x1000>;
};

17
dts/Bindings/auxdisplay/img-ascii-lcd.txt Normal file
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@ -0,0 +1,17 @@
Binding for ASCII LCD displays on Imagination Technologies boards
Required properties:
- compatible : should be one of:
"img,boston-lcd"
"mti,malta-lcd"
"mti,sead3-lcd"
Required properties for "img,boston-lcd":
- reg : memory region locating the device registers
Required properties for "mti,malta-lcd" or "mti,sead3-lcd":
- regmap: phandle of the system controller containing the LCD registers
- offset: offset in bytes to the LCD registers within the system controller
The layout of the registers & properties of the display are determined
from the compatible string, making this binding somewhat trivial.

138
dts/Bindings/bus/qcom,ebi2.txt Normal file
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@ -0,0 +1,138 @@
Qualcomm External Bus Interface 2 (EBI2)
The EBI2 contains two peripheral blocks: XMEM and LCDC. The XMEM handles any
external memory (such as NAND or other memory-mapped peripherals) whereas
LCDC handles LCD displays.
As it says it connects devices to an external bus interface, meaning address
lines (up to 9 address lines so can only address 1KiB external memory space),
data lines (16 bits), OE (output enable), ADV (address valid, used on some
NOR flash memories), WE (write enable). This on top of 6 different chip selects
(CS0 thru CS5) so that in theory 6 different devices can be connected.
Apparently this bus is clocked at 64MHz. It has dedicated pins on the package
and the bus can only come out on these pins, however if some of the pins are
unused they can be left unconnected or remuxed to be used as GPIO or in some
cases other orthogonal functions as well.
Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
The chip selects have the following memory range assignments. This region of
memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big.
Chip Select Physical address base
CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A,
August 6, 2012 contains some incomplete documentation of the EBI2.
FIXME: the manual mentions "write precharge cycles" and "precharge cycles".
We have not been able to figure out which bit fields these correspond to
in the hardware, or what valid values exist. The current hypothesis is that
this is something just used on the FAST chip selects and that the SLOW
chip selects are understood fully. There is also a "byte device enable"
flag somewhere for 8bit memories.
FIXME: The chipselects have SLOW and FAST configuration registers. It's a bit
unclear what this means, if they are mutually exclusive or can be used
together, or if some chip selects are hardwired to be FAST and others are SLOW
by design.
The XMEM registers are totally undocumented but could be partially decoded
because the Cypress AN49576 Antioch Westbridge apparently has suspiciously
similar register layout, see: http://www.cypress.com/file/105771/download
Required properties:
- compatible: should be one of:
"qcom,msm8660-ebi2"
"qcom,apq8060-ebi2"
- #address-cells: shoule be <2>: the first cell is the chipselect,
the second cell is the offset inside the memory range
- #size-cells: should be <1>
- ranges: should be set to:
ranges = <0 0x0 0x1a800000 0x00800000>,
<1 0x0 0x1b000000 0x00800000>,
<2 0x0 0x1b800000 0x00800000>,
<3 0x0 0x1d000000 0x08000000>,
<4 0x0 0x1c800000 0x00800000>,
<5 0x0 0x1c000000 0x00800000>;
- reg: two ranges of registers: EBI2 config and XMEM config areas
- reg-names: should be "ebi2", "xmem"
- clocks: two clocks, EBI_2X and EBI
- clock-names: shoule be "ebi2x", "ebi2"
Optional subnodes:
- Nodes inside the EBI2 will be considered device nodes.
The following optional properties are properties that can be tagged onto
any device subnode. We are assuming that there can be only ONE device per
chipselect subnode, else the properties will become ambigous.
Optional properties arrays for SLOW chip selects:
- qcom,xmem-recovery-cycles: recovery cycles is the time the memory continues to
drive the data bus after OE is de-asserted, in order to avoid contention on
the data bus. They are inserted when reading one CS and switching to another
CS or read followed by write on the same CS. Valid values 0 thru 15. Minimum
value is actually 1, so a value of 0 will still yield 1 recovery cycle.
- qcom,xmem-write-hold-cycles: write hold cycles, these are extra cycles
inserted after every write minimum 1. The data out is driven from the time
WE is asserted until CS is asserted. With a hold of 1 (value = 0), the CS
stays active for 1 extra cycle etc. Valid values 0 thru 15.
- qcom,xmem-write-delta-cycles: initial latency for write cycles inserted for
the first write to a page or burst memory. Valid values 0 thru 255.
- qcom,xmem-read-delta-cycles: initial latency for read cycles inserted for the
first read to a page or burst memory. Valid values 0 thru 255.
- qcom,xmem-write-wait-cycles: number of wait cycles for every write access, 0=1
cycle. Valid values 0 thru 15.
- qcom,xmem-read-wait-cycles: number of wait cycles for every read access, 0=1
cycle. Valid values 0 thru 15.
Optional properties arrays for FAST chip selects:
- qcom,xmem-address-hold-enable: this is a boolean property stating that we
shall hold the address for an extra cycle to meet hold time requirements
with ADV assertion.
- qcom,xmem-adv-to-oe-recovery-cycles: the number of cycles elapsed before an OE
assertion, with respect to the cycle where ADV (address valid) is asserted.
2 means 2 cycles between ADV and OE. Valid values 0, 1, 2 or 3.
- qcom,xmem-read-hold-cycles: the length in cycles of the first segment of a
read transfer. For a single read trandfer this will be the time from CS
assertion to OE assertion. Valid values 0 thru 15.
Example:
ebi2@1a100000 {
compatible = "qcom,apq8060-ebi2";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0x0 0x1a800000 0x00800000>,
<1 0x0 0x1b000000 0x00800000>,
<2 0x0 0x1b800000 0x00800000>,
<3 0x0 0x1d000000 0x08000000>,
<4 0x0 0x1c800000 0x00800000>,
<5 0x0 0x1c000000 0x00800000>;
reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
reg-names = "ebi2", "xmem";
clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
clock-names = "ebi2x", "ebi2";
/* Make sure to set up the pin control for the EBI2 */
pinctrl-names = "default";
pinctrl-0 = <&foo_ebi2_pins>;
foo-ebi2@2,0 {
compatible = "foo";
reg = <2 0x0 0x100>;
(...)
qcom,xmem-recovery-cycles = <0>;
qcom,xmem-write-hold-cycles = <3>;
qcom,xmem-write-delta-cycles = <31>;
qcom,xmem-read-delta-cycles = <28>;
qcom,xmem-write-wait-cycles = <9>;
qcom,xmem-read-wait-cycles = <9>;
};
};

45
dts/Bindings/clock/amlogic,gxbb-aoclkc.txt Normal file
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@ -0,0 +1,45 @@
* Amlogic GXBB AO Clock and Reset Unit
The Amlogic GXBB AO clock controller generates and supplies clock to various
controllers within the Always-On part of the SoC.
Required Properties:
- compatible: should be "amlogic,gxbb-aoclkc"
- reg: physical base address of the clock controller and length of memory
mapped region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/gxbb-aoclkc.h header and can be
used in device tree sources.
- #reset-cells: should be 1.
Each reset is assigned an identifier and client nodes can use this identifier
to specify the reset which they consume. All available resets are defined as
preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be
used in device tree sources.
Example: AO Clock controller node:
clkc_AO: clock-controller@040 {
compatible = "amlogic,gxbb-aoclkc";
reg = <0x0 0x040 0x0 0x4>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Example: UART controller node that consumes the clock and reset generated
by the clock controller:
uart_AO: serial@4c0 {
compatible = "amlogic,meson-uart";
reg = <0x4c0 0x14>;
interrupts = <0 90 1>;
clocks = <&clkc_AO CLKID_AO_UART1>;
resets = <&clkc_AO RESET_AO_UART1>;
status = "disabled";
};

34
dts/Bindings/clock/arm-syscon-icst.txt
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@ -5,20 +5,50 @@ Technology (IDT). ARM integrated these oscillators deeply into their
reference designs by adding special control registers that manage such
oscillators to their system controllers.
The ARM system controller contains logic to serialize and initialize
The various ARM system controllers contain logic to serialize and initialize
an ICST clock request after a write to the 32 bit register at an offset
into the system controller. Furthermore, to even be able to alter one of
these frequencies, the system controller must first be unlocked by
writing a special token to another offset in the system controller.
Some ARM hardware contain special versions of the serial interface that only
connects the low 8 bits of the VDW (missing one bit), hardwires RDW to
different values and sometimes also hardwire the output divider. They
therefore have special compatible strings as per this table (the OD value is
the value on the pins, not the resulting output divider):
Hardware variant: RDW OD VDW
Integrator/AP 22 1 Bit 8 0, rest variable
integratorap-cm
Integrator/AP 46 3 Bit 8 0, rest variable
integratorap-sys
Integrator/AP 22 or 1 17 or (33 or 25 MHz)
integratorap-pci 14 1 14
Integrator/CP 22 variable Bit 8 0, rest variable
integratorcp-cm-core
Integrator/CP 22 variable Bit 8 0, rest variable
integratorcp-cm-mem
The ICST oscillator must be provided inside a system controller node.
Required properties:
- compatible: must be one of
"arm,syscon-icst525"
"arm,syscon-icst307"
"arm,syscon-icst525-integratorap-cm"
"arm,syscon-icst525-integratorap-sys"
"arm,syscon-icst525-integratorap-pci"
"arm,syscon-icst525-integratorcp-cm-core"
"arm,syscon-icst525-integratorcp-cm-mem"
- lock-offset: the offset address into the system controller where the
unlocking register is located
- vco-offset: the offset address into the system controller where the
ICST control register is located (even 32 bit address)
- compatible: must be one of "arm,syscon-icst525" or "arm,syscon-icst307"
- #clock-cells: must be <0>
- clocks: parent clock, since the ICST needs a parent clock to derive its
frequency from, this attribute is compulsory.

70
dts/Bindings/clock/armada3700-periph-clock.txt Normal file
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@ -0,0 +1,70 @@
* Peripheral Clock bindings for Marvell Armada 37xx SoCs
Marvell Armada 37xx SoCs provide peripheral clocks which are
used as clock source for the peripheral of the SoC.
There are two different blocks associated to north bridge and south
bridge.
The peripheral clock consumer should specify the desired clock by
having the clock ID in its "clocks" phandle cell.
The following is a list of provided IDs for Armada 370 North bridge clocks:
ID Clock name Description
-----------------------------------
0 mmc MMC controller
1 sata_host Sata Host
2 sec_at Security AT
3 sac_dap Security DAP
4 tsecm Security Engine
5 setm_tmx Serial Embedded Trace Module
6 avs Adaptive Voltage Scaling
7 sqf SPI
8 pwm PWM
9 i2c_2 I2C 2
10 i2c_1 I2C 1
11 ddr_phy DDR PHY
12 ddr_fclk DDR F clock
13 trace Trace
14 counter Counter
15 eip97 EIP 97
16 cpu CPU
The following is a list of provided IDs for Armada 370 South bridge clocks:
ID Clock name Description
-----------------------------------
0 gbe-50 50 MHz parent clock for Gigabit Ethernet
1 gbe-core parent clock for Gigabit Ethernet core
2 gbe-125 125 MHz parent clock for Gigabit Ethernet
3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
7 gbe1-core Gigabit Ethernet core port 1
8 gbe0-core Gigabit Ethernet core port 0
9 gbe-bm Gigabit Ethernet Buffer Manager
10 sdio SDIO
11 usb32-sub2-sys USB 2 clock
12 usb32-ss-sys USB 3 clock
Required properties:
- compatible : shall be "marvell,armada-3700-periph-clock-nb" for the
north bridge block, or
"marvell,armada-3700-periph-clock-sb" for the south bridge block
- reg : must be the register address of North/South Bridge Clock register
- #clock-cells : from common clock binding; shall be set to 1
- clocks : list of the parent clock phandle in the following order:
TBG-A P, TBG-B P, TBG-A S, TBG-B S and finally the xtal clock.
Example:
nb_perih_clk: nb-periph-clk@13000{
compatible = "marvell,armada-3700-periph-clock-nb";
reg = <0x13000 0x1000>;
clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
<&tbg 3>, <&xtalclk>;
#clock-cells = <1>;
};

27
dts/Bindings/clock/armada3700-tbg-clock.txt Normal file
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@ -0,0 +1,27 @@
* Time Base Generator Clock bindings for Marvell Armada 37xx SoCs
Marvell Armada 37xx SoCs provde Time Base Generator clocks which are
used as parent clocks for the peripheral clocks.
The TBG clock consumer should specify the desired clock by having the
clock ID in its "clocks" phandle cell.
The following is a list of provided IDs and clock names on Armada 3700:
0 = TBG A P
1 = TBG B P
2 = TBG A S
3 = TBG B S
Required properties:
- compatible : shall be "marvell,armada-3700-tbg-clock"
- reg : must be the register address of North Bridge PLL register
- #clock-cells : from common clock binding; shall be set to 1
Example:
tbg: tbg@13200 {
compatible = "marvell,armada-3700-tbg-clock";
reg = <0x13200 0x1000>;
clocks = <&xtalclk>;
#clock-cells = <1>;
};

28
dts/Bindings/clock/armada3700-xtal-clock.txt Normal file
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@ -0,0 +1,28 @@
* Xtal Clock bindings for Marvell Armada 37xx SoCs
Marvell Armada 37xx SoCs allow to determine the xtal clock frequencies by
reading the gpio latch register.
This node must be a subnode of the node exposing the register address
of the GPIO block where the gpio latch is located.
Required properties:
- compatible : shall be one of the following:
"marvell,armada-3700-xtal-clock"
- #clock-cells : from common clock binding; shall be set to 0
Optional properties:
- clock-output-names : from common clock binding; allows overwrite default clock
output names ("xtal")
Example:
gpio1: gpio@13800 {
compatible = "marvell,armada-3700-gpio", "syscon", "simple-mfd";
reg = <0x13800 0x1000>;
xtalclk: xtal-clk {
compatible = "marvell,armada-3700-xtal-clock";
clock-output-names = "xtal";
#clock-cells = <0>;
};
};

3
dts/Bindings/clock/at91-clock.txt
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@ -6,7 +6,8 @@ This binding uses the common clock binding[1].
Required properties:
- compatible : shall be one of the following:
"atmel,at91sam9x5-sckc":
"atmel,at91sam9x5-sckc" or
"atmel,sama5d4-sckc":
at91 SCKC (Slow Clock Controller)
This node contains the slow clock definitions.

36
dts/Bindings/clock/brcm,bcm53573-ilp.txt Normal file
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@ -0,0 +1,36 @@
Broadcom BCM53573 ILP clock
===========================
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
This binding is used for ILP clock (sometimes referred as "slow clock")
on Broadcom BCM53573 devices using Cortex-A7 CPU.
ILP's rate has to be calculated on runtime and it depends on ALP clock
which has to be referenced.
This clock is part of PMU (Power Management Unit), a Broadcom's device
handing power-related aspects. Its node must be sub-node of the PMU
device.
Required properties:
- compatible: "brcm,bcm53573-ilp"
- clocks: has to reference an ALP clock
- #clock-cells: should be <0>
- clock-output-names: from common clock bindings, should contain clock
name
Example:
pmu@18012000 {
compatible = "simple-mfd", "syscon";
reg = <0x18012000 0x00001000>;
ilp {
compatible = "brcm,bcm53573-ilp";
clocks = <&alp>;
#clock-cells = <0>;
clock-output-names = "ilp";
};
};

4
dts/Bindings/clock/clk-exynos-audss.txt
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@ -10,6 +10,8 @@ Required Properties:
- "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
- "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
SoCs.
- "samsung,exynos5410-audss-clock" - controller compatible with Exynos5410
SoCs.
- "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
SoCs.
- reg: physical base address and length of the controller's register set.
@ -91,5 +93,5 @@ i2s0: i2s@03830000 {
<&clock_audss EXYNOS_MOUT_AUDSS>,
<&clock_audss EXYNOS_MOUT_I2S>;
clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
"mout_audss", "mout_i2s";
"mout_audss", "mout_i2s";
};

21
dts/Bindings/clock/exynos5410-clock.txt
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@ -12,24 +12,29 @@ Required Properties:
- #clock-cells: should be 1.
- clocks: should contain an entry specifying the root clock from external
oscillator supplied through XXTI or XusbXTI pin. This clock should be
defined using standard clock bindings with "fin_pll" clock-output-name.
That clock is being passed internally to the 9 PLLs.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos5410.h header and can be used in device
tree sources.
External clock:
There is clock that is generated outside the SoC. It
is expected that it is defined using standard clock bindings
with following clock-output-name:
- "fin_pll" - PLL input clock from XXTI
Example 1: An example of a clock controller node is listed below.
fin_pll: xxti {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "fin_pll";
#clock-cells = <0>;
};
clock: clock-controller@0x10010000 {
compatible = "samsung,exynos5410-clock";
reg = <0x10010000 0x30000>;
#clock-cells = <1>;
clocks = <&fin_pll>;
};
Example 2: UART controller node that consumes the clock generated by the clock

118
dts/Bindings/clock/maxim,max77686.txt
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@ -1,10 +1,24 @@
Binding for Maxim MAX77686 32k clock generator block
Binding for Maxim MAX77686/MAX77802/MAX77620 32k clock generator block
This is a part of device tree bindings of MAX77686 multi-function device.
More information can be found in bindings/mfd/max77686.txt file.
This is a part of device tree bindings of MAX77686/MAX77802/MAX77620
multi-function device. More information can be found in MFD DT binding
doc as follows:
bindings/mfd/max77686.txt for MAX77686 and
bindings/mfd/max77802.txt for MAX77802 and
bindings/mfd/max77620.txt for MAX77620.
The MAX77686 contains three 32.768khz clock outputs that can be controlled
(gated/ungated) over I2C.
(gated/ungated) over I2C. Clocks are defined as preprocessor macros in
dt-bindings/clock/maxim,max77686.h.
The MAX77802 contains two 32.768khz clock outputs that can be controlled
(gated/ungated) over I2C. Clocks are defined as preprocessor macros in
dt-bindings/clock/maxim,max77802.h.
The MAX77686 contains one 32.768khz clock outputs that can be controlled
(gated/ungated) over I2C. Clocks are defined as preprocessor macros in
dt-bindings/clock/maxim,max77620.h.
Following properties should be presend in main device node of the MFD chip.
@ -17,30 +31,84 @@ Optional properties:
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Following indices are allowed:
- 0: 32khz_ap clock,
- 1: 32khz_cp clock,
- 2: 32khz_pmic clock.
- 0: 32khz_ap clock (max77686, max77802), 32khz_out0 (max77620)
- 1: 32khz_cp clock (max77686, max77802),
- 2: 32khz_pmic clock (max77686).
Clocks are defined as preprocessor macros in dt-bindings/clock/maxim,max77686.h
header and can be used in device tree sources.
Clocks are defined as preprocessor macros in above dt-binding header for
respective chips.
Example: Node of the MFD chip
Example:
max77686: max77686@09 {
compatible = "maxim,max77686";
interrupt-parent = <&wakeup_eint>;
interrupts = <26 0>;
reg = <0x09>;
#clock-cells = <1>;
1. With MAX77686:
/* ... */
};
#include <dt-bindings/clock/maxim,max77686.h>
/* ... */
Example: Clock consumer node
Node of the MFD chip
max77686: max77686@09 {
compatible = "maxim,max77686";
interrupt-parent = <&wakeup_eint>;
interrupts = <26 0>;
reg = <0x09>;
#clock-cells = <1>;
foo@0 {
compatible = "bar,foo";
/* ... */
clock-names = "my-clock";
clocks = <&max77686 MAX77686_CLK_PMIC>;
};
/* ... */
};
Clock consumer node
foo@0 {
compatible = "bar,foo";
/* ... */
clock-names = "my-clock";
clocks = <&max77686 MAX77686_CLK_PMIC>;
};
2. With MAX77802:
#include <dt-bindings/clock/maxim,max77802.h>
/* ... */
Node of the MFD chip
max77802: max77802@09 {
compatible = "maxim,max77802";
interrupt-parent = <&wakeup_eint>;
interrupts = <26 0>;
reg = <0x09>;
#clock-cells = <1>;
/* ... */
};
Clock consumer node
foo@0 {
compatible = "bar,foo";
/* ... */
clock-names = "my-clock";
clocks = <&max77802 MAX77802_CLK_32K_AP>;
};
3. With MAX77620:
#include <dt-bindings/clock/maxim,max77620.h>
/* ... */
Node of the MFD chip
max77620: max77620@3c {
compatible = "maxim,max77620";
reg = <0x3c>;
#clock-cells = <1>;
/* ... */
};
Clock consumer node
foo@0 {
compatible = "bar,foo";
/* ... */
clock-names = "my-clock";
clocks = <&max77620 MAX77620_CLK_32K_OUT0>;
};

44
dts/Bindings/clock/maxim,max77802.txt
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@ -1,44 +0,0 @@
Binding for Maxim MAX77802 32k clock generator block
This is a part of device tree bindings of MAX77802 multi-function device.
More information can be found in bindings/mfd/max77802.txt file.
The MAX77802 contains two 32.768khz clock outputs that can be controlled
(gated/ungated) over I2C.
Following properties should be present in main device node of the MFD chip.
Required properties:
- #clock-cells: From common clock binding; shall be set to 1.
Optional properties:
- clock-output-names: From common clock binding.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Following indices are allowed:
- 0: 32khz_ap clock,
- 1: 32khz_cp clock.
Clocks are defined as preprocessor macros in dt-bindings/clock/maxim,max77802.h
header and can be used in device tree sources.
Example: Node of the MFD chip
max77802: max77802@09 {
compatible = "maxim,max77802";
interrupt-parent = <&wakeup_eint>;
interrupts = <26 0>;
reg = <0x09>;
#clock-cells = <1>;
/* ... */
};
Example: Clock consumer node
foo@0 {
compatible = "bar,foo";
/* ... */
clock-names = "my-clock";
clocks = <&max77802 MAX77802_CLK_32K_AP>;
};

1
dts/Bindings/clock/mvebu-core-clock.txt
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@ -52,6 +52,7 @@ Required properties:
"marvell,dove-core-clock" - for Dove SoC core clocks
"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
"marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC
"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC

2
dts/Bindings/clock/mvebu-gated-clock.txt
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@ -86,6 +86,8 @@ ID Clock Peripheral
7 pex3 PCIe 3
8 pex0 PCIe 0
9 usb3h0 USB3 Host 0
10 usb3h1 USB3 Host 1
15 sata0 SATA 0
17 sdio SDIO
22 xor0 XOR 0
28 xor1 XOR 1

17
dts/Bindings/clock/qcom,gcc.txt
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@ -15,6 +15,7 @@ Required properties :
"qcom,gcc-msm8974pro"
"qcom,gcc-msm8974pro-ac"
"qcom,gcc-msm8996"
"qcom,gcc-mdm9615"
- reg : shall contain base register location and length
- #clock-cells : shall contain 1
@ -22,6 +23,11 @@ Required properties :
Optional properties :
- #power-domain-cells : shall contain 1
- Qualcomm TSENS (thermal sensor device) on some devices can
be part of GCC and hence the TSENS properties can also be
part of the GCC/clock-controller node.
For more details on the TSENS properties please refer
Documentation/devicetree/bindings/thermal/qcom-tsens.txt
Example:
clock-controller@900000 {
@ -31,3 +37,14 @@ Example:
#reset-cells = <1>;
#power-domain-cells = <1>;
};
Example of GCC with TSENS properties:
clock-controller@900000 {
compatible = "qcom,gcc-apq8064";
reg = <0x00900000 0x4000>;
nvmem-cells = <&tsens_calib>, <&tsens_backup>;
nvmem-cell-names = "calib", "calib_backup";
#clock-cells = <1>;
#reset-cells = <1>;
#thermal-sensor-cells = <1>;
};

1
dts/Bindings/clock/qcom,lcc.txt
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@ -7,6 +7,7 @@ Required properties :
"qcom,lcc-msm8960"
"qcom,lcc-apq8064"
"qcom,lcc-ipq8064"
"qcom,lcc-mdm9615"
- reg : shall contain base register location and length
- #clock-cells : shall contain 1

42
dts/Bindings/clock/st,stm32-rcc.txt
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@ -1,16 +1,16 @@
STMicroelectronics STM32 Reset and Clock Controller
===================================================
The RCC IP is both a reset and a clock controller. This documentation only
describes the clock part.
The RCC IP is both a reset and a clock controller.
Please also refer to clock-bindings.txt in this directory for common clock
controller binding usage.
Please refer to clock-bindings.txt for common clock controller binding usage.
Please also refer to reset.txt for common reset controller binding usage.
Required properties:
- compatible: Should be "st,stm32f42xx-rcc"
- reg: should be register base and length as documented in the
datasheet
- #reset-cells: 1, see below
- #clock-cells: 2, device nodes should specify the clock in their "clocks"
property, containing a phandle to the clock device node, an index selecting
between gated clocks and other clocks and an index specifying the clock to
@ -19,6 +19,7 @@ Required properties:
Example:
rcc: rcc@40023800 {
#reset-cells = <1>;
#clock-cells = <2>
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
reg = <0x40023800 0x400>;
@ -35,16 +36,23 @@ from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
It is calculated as: index = register_offset / 4 * 32 + bit_offset.
Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).
To simplify the usage and to share bit definition with the reset and clock
drivers of the RCC IP, macros are available to generate the index in
human-readble format.
For STM32F4 series, the macro are available here:
- include/dt-bindings/mfd/stm32f4-rcc.h
Example:
/* Gated clock, AHB1 bit 0 (GPIOA) */
... {
clocks = <&rcc 0 0>
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
};
/* Gated clock, AHB2 bit 4 (CRYP) */
... {
clocks = <&rcc 0 36>
clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
};
Specifying other clocks
@ -61,5 +69,25 @@ Example:
/* Misc clock, FCLK */
... {
clocks = <&rcc 1 1>
clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
};
Specifying softreset control of devices
=======================================
Device nodes should specify the reset channel required in their "resets"
property, containing a phandle to the reset device node and an index specifying
which channel to use.
The index is the bit number within the RCC registers bank, starting from RCC
base address.
It is calculated as: index = register_offset / 4 * 32 + bit_offset.
Where bit_offset is the bit offset within the register.
For example, for CRC reset:
crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140
example:
timer2 {
resets = <&rcc STM32F4_APB1_RESET(TIM2)>;
};

49
dts/Bindings/clock/st/st,clkgen-divmux.txt
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@ -1,49 +0,0 @@
Binding for a ST divider and multiplexer clock driver.
This binding uses the common clock binding[1].
Base address is located to the parent node. See clock binding[2]
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
Required properties:
- compatible : shall be:
"st,clkgena-divmux-c65-hs", "st,clkgena-divmux"
"st,clkgena-divmux-c65-ls", "st,clkgena-divmux"
"st,clkgena-divmux-c32-odf0", "st,clkgena-divmux"
"st,clkgena-divmux-c32-odf1", "st,clkgena-divmux"
"st,clkgena-divmux-c32-odf2", "st,clkgena-divmux"
"st,clkgena-divmux-c32-odf3", "st,clkgena-divmux"
- #clock-cells : From common clock binding; shall be set to 1.
- clocks : From common clock binding
- clock-output-names : From common clock binding.
Example:
clockgen-a@fd345000 {
reg = <0xfd345000 0xb50>;
clk_m_a1_div1: clk-m-a1-div1 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf1",
"st,clkgena-divmux";
clocks = <&clk_m_a1_osc_prediv>,
<&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
<&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
clock-output-names = "clk-m-rx-icn-ts",
"clk-m-rx-icn-vdp-0",
"", /* unused */
"clk-m-prv-t1-bus",
"clk-m-icn-reg-12",
"clk-m-icn-reg-10",
"", /* unused */
"clk-m-icn-st231";
};
};

20
dts/Bindings/clock/st/st,clkgen-mux.txt
View File

@ -10,14 +10,7 @@ This binding uses the common clock binding[1].
Required properties:
- compatible : shall be:
"st,stih416-clkgenc-vcc-hd", "st,clkgen-mux"
"st,stih416-clkgenf-vcc-fvdp", "st,clkgen-mux"
"st,stih416-clkgenf-vcc-hva", "st,clkgen-mux"
"st,stih416-clkgenf-vcc-hd", "st,clkgen-mux"
"st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"
"st,stih415-clkgen-a9-mux", "st,clkgen-mux"
"st,stih416-clkgen-a9-mux", "st,clkgen-mux"
"st,stih407-clkgen-a9-mux", "st,clkgen-mux"
"st,stih407-clkgen-a9-mux"
- #clock-cells : from common clock binding; shall be set to 0.
@ -27,10 +20,13 @@ Required properties:
Example:
clk_m_hva: clk-m-hva@fd690868 {
clk_m_a9: clk-m-a9@92b0000 {
#clock-cells = <0>;
compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
reg = <0xfd690868 4>;
compatible = "st,stih407-clkgen-a9-mux";
reg = <0x92b0000 0x10000>;
clocks = <&clockgen_f 1>, <&clk_m_a1_div0 3>;
clocks = <&clockgen_a9_pll 0>,
<&clockgen_a9_pll 0>,
<&clk_s_c0_flexgen 13>,
<&clk_m_a9_ext2f_div2>;
};

35
dts/Bindings/clock/st/st,clkgen-pll.txt
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@ -9,24 +9,10 @@ Base address is located to the parent node. See clock binding[2]
Required properties:
- compatible : shall be:
"st,clkgena-prediv-c65", "st,clkgena-prediv"
"st,clkgena-prediv-c32", "st,clkgena-prediv"
"st,clkgena-plls-c65"
"st,plls-c32-a1x-0", "st,clkgen-plls-c32"
"st,plls-c32-a1x-1", "st,clkgen-plls-c32"
"st,stih415-plls-c32-a9", "st,clkgen-plls-c32"
"st,stih415-plls-c32-ddr", "st,clkgen-plls-c32"
"st,stih416-plls-c32-a9", "st,clkgen-plls-c32"
"st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
"sst,plls-c32-cx_0", "st,clkgen-plls-c32"
"sst,plls-c32-cx_1", "st,clkgen-plls-c32"
"st,stih418-plls-c28-a9", "st,clkgen-plls-c32"
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
"st,clkgen-pll0"
"st,clkgen-pll1"
"st,stih407-clkgen-plla9"
"st,stih418-clkgen-plla9"
- #clock-cells : From common clock binding; shall be set to 1.
@ -36,17 +22,16 @@ Required properties:
Example:
clockgen-a@fee62000 {
reg = <0xfee62000 0xb48>;
clockgen-a9@92b0000 {
compatible = "st,clkgen-c32";
reg = <0x92b0000 0xffff>;
clk_s_a0_pll: clk-s-a0-pll {
clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>;
compatible = "st,clkgena-plls-c65";
compatible = "st,stih407-clkgen-plla9";
clocks = <&clk_sysin>;
clock-output-names = "clk-s-a0-pll0-hs",
"clk-s-a0-pll0-ls",
"clk-s-a0-pll1";
clock-output-names = "clockgen-a9-pll-odf";
};
};

36
dts/Bindings/clock/st/st,clkgen-prediv.txt
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@ -1,36 +0,0 @@
Binding for a ST pre-divider clock driver.
This binding uses the common clock binding[1].
Base address is located to the parent node. See clock binding[2]
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
Required properties:
- compatible : shall be:
"st,clkgena-prediv-c65", "st,clkgena-prediv"
"st,clkgena-prediv-c32", "st,clkgena-prediv"
- #clock-cells : From common clock binding; shall be set to 0.
- clocks : From common clock binding
- clock-output-names : From common clock binding.
Example:
clockgen-a@fd345000 {
reg = <0xfd345000 0xb50>;
clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c32",
"st,clkgena-prediv";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a2-osc-prediv";
};
};

61
dts/Bindings/clock/st/st,clkgen-vcc.txt
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@ -1,61 +0,0 @@
Binding for a type of STMicroelectronics clock crossbar (VCC).
The crossbar can take up to 4 input clocks and control up to 16
output clocks. Not all inputs or outputs have to be in use in a
particular instantiation. Each output can be individually enabled,
select any of the input clocks and apply a divide (by 1,2,4 or 8) to
that selected clock.
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be:
"st,stih416-clkgenc", "st,vcc"
"st,stih416-clkgenf", "st,vcc"
- #clock-cells : from common clock binding; shall be set to 1.
- reg : A Base address and length of the register set.
- clocks : from common clock binding
- clock-output-names : From common clock binding. The block has 16
clock outputs but not all of them in a specific instance
have to be used in the SoC. If a clock name is left as
an empty string then no clock will be created for the
output associated with that string index. If fewer than
16 strings are provided then no clocks will be created
for the remaining outputs.
Example:
clockgen_c_vcc: clockgen-c-vcc@0xfe8308ac {
#clock-cells = <1>;
compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
reg = <0xfe8308ac 12>;
clocks = <&clk_s_vcc_hd>,
<&clockgen_c 1>,
<&clk_s_tmds_fromphy>,
<&clockgen_c 2>;
clock-output-names = "clk-s-pix-hdmi",
"clk-s-pix-dvo",
"clk-s-out-dvo",
"clk-s-pix-hd",
"clk-s-hddac",
"clk-s-denc",
"clk-s-sddac",
"clk-s-pix-main",
"clk-s-pix-aux",
"clk-s-stfe-frc-0",
"clk-s-ref-mcru",
"clk-s-slave-mcru",
"clk-s-tmds-hdmi",
"clk-s-hdmi-reject-pll",
"clk-s-thsens";
};

54
dts/Bindings/clock/st/st,clkgen.txt
View File

@ -13,14 +13,6 @@ address is common of all subnode.
...
};
prediv_node {
...
};
divmux_node {
...
};
quadfs_node {
...
};
@ -29,10 +21,6 @@ address is common of all subnode.
...
};
vcc_node {
...
};
flexgen_node {
...
};
@ -43,11 +31,8 @@ This binding uses the common clock binding[1].
Each subnode should use the binding described in [2]..[7]
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt
[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
[6] Documentation/devicetree/bindings/clock/st,vcc.txt
[7] Documentation/devicetree/bindings/clock/st,quadfs.txt
[8] Documentation/devicetree/bindings/clock/st,flexgen.txt
@ -57,44 +42,27 @@ Required properties:
Example:
clockgen-a@fee62000 {
reg = <0xfee62000 0xb48>;
clockgen-a@090ff000 {
compatible = "st,clkgen-c32";
reg = <0x90ff000 0x1000>;
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
compatible = "st,clkgena-plls-c65";
clocks = <&clk-sysin>;
clock-output-names = "clk-s-a0-pll0-hs",
"clk-s-a0-pll0-ls",
"clk-s-a0-pll1";
};
clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c65",
"st,clkgena-prediv";
compatible = "st,clkgen-pll0";
clocks = <&clk_sysin>;
clock-output-names = "clk-s-a0-osc-prediv";
clock-output-names = "clk-s-a0-pll-ofd-0";
};
clk_s_a0_hs: clk-s-a0-hs {
clk_s_a0_flexgen: clk-s-a0-flexgen {
compatible = "st,flexgen";
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c65-hs",
"st,clkgena-divmux";
clocks = <&clk-s_a0_osc_prediv>,
<&clk-s_a0_pll 0>, /* pll0 hs */
<&clk-s_a0_pll 2>; /* pll1 */
clocks = <&clk_s_a0_pll 0>,
<&clk_sysin>;
clock-output-names = "clk-s-fdma-0",
"clk-s-fdma-1",
""; /* clk-s-jit-sense */
/* fourth output unused */
clock-output-names = "clk-ic-lmi0";
};
};

4
dts/Bindings/clock/st/st,flexgen.txt
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@ -60,6 +60,10 @@ This binding uses the common clock binding[2].
Required properties:
- compatible : shall be:
"st,flexgen"
"st,flexgen-audio", "st,flexgen" (enable clock propagation on parent for
audio use case)
"st,flexgen-video", "st,flexgen" (enable clock propagation on parent
and activate synchronous mode)
- #clock-cells : from common clock binding; shall be set to 1 (multiple clock
outputs).

29
dts/Bindings/clock/st/st,quadfs.txt
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@ -11,12 +11,8 @@ This binding uses the common clock binding[1].
Required properties:
- compatible : shall be:
"st,stih416-quadfs216", "st,quadfs"
"st,stih416-quadfs432", "st,quadfs"
"st,stih416-quadfs660-E", "st,quadfs"
"st,stih416-quadfs660-F", "st,quadfs"
"st,stih407-quadfs660-C", "st,quadfs"
"st,stih407-quadfs660-D", "st,quadfs"
"st,quadfs"
"st,quadfs-pll"
- #clock-cells : from common clock binding; shall be set to 1.
@ -35,14 +31,15 @@ Required properties:
Example:
clockgen_e: clockgen-e@fd3208bc {
#clock-cells = <1>;
compatible = "st,stih416-quadfs660-E", "st,quadfs";
reg = <0xfd3208bc 0xB0>;
clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
#clock-cells = <1>;
compatible = "st,quadfs-pll";
reg = <0x9103000 0x1000>;
clocks = <&clk_sysin>;
clock-output-names = "clk-m-pix-mdtp-0",
"clk-m-pix-mdtp-1",
"clk-m-pix-mdtp-2",
"clk-m-mpelpc";
};
clocks = <&clk_sysin>;
clock-output-names = "clk-s-c0-fs0-ch0",
"clk-s-c0-fs0-ch1",
"clk-s-c0-fs0-ch2",
"clk-s-c0-fs0-ch3";
};

5
dts/Bindings/clock/sunxi-ccu.txt
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@ -2,7 +2,10 @@ Allwinner Clock Control Unit Binding
------------------------------------
Required properties :
- compatible: must contain one of the following compatible:
- compatible: must contain one of the following compatibles:
- "allwinner,sun6i-a31-ccu"
- "allwinner,sun8i-a23-ccu"
- "allwinner,sun8i-a33-ccu"
- "allwinner,sun8i-h3-ccu"
- reg: Must contain the registers base address and length

134
dts/Bindings/clock/uniphier-clock.txt Normal file
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@ -0,0 +1,134 @@
UniPhier clock controller
System clock
------------
Required properties:
- compatible: should be one of the following:
"socionext,uniphier-sld3-clock" - for sLD3 SoC.
"socionext,uniphier-ld4-clock" - for LD4 SoC.
"socionext,uniphier-pro4-clock" - for Pro4 SoC.
"socionext,uniphier-sld8-clock" - for sLD8 SoC.
"socionext,uniphier-pro5-clock" - for Pro5 SoC.
"socionext,uniphier-pxs2-clock" - for PXs2/LD6b SoC.
"socionext,uniphier-ld11-clock" - for LD11 SoC.
"socionext,uniphier-ld20-clock" - for LD20 SoC.
- #clock-cells: should be 1.
Example:
sysctrl@61840000 {
compatible = "socionext,uniphier-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x4000>;
clock {
compatible = "socionext,uniphier-ld20-clock";
#clock-cells = <1>;
};
other nodes ...
};
Provided clocks:
8: ST DMAC
12: GIO (Giga bit stream I/O)
14: USB3 ch0 host
15: USB3 ch1 host
16: USB3 ch0 PHY0
17: USB3 ch0 PHY1
20: USB3 ch1 PHY0
21: USB3 ch1 PHY1
Media I/O (MIO) clock
---------------------
Required properties:
- compatible: should be one of the following:
"socionext,uniphier-sld3-mio-clock" - for sLD3 SoC.
"socionext,uniphier-ld4-mio-clock" - for LD4 SoC.
"socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.
"socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.
"socionext,uniphier-pro5-mio-clock" - for Pro5 SoC.
"socionext,uniphier-pxs2-mio-clock" - for PXs2/LD6b SoC.
"socionext,uniphier-ld11-mio-clock" - for LD11 SoC.
"socionext,uniphier-ld20-mio-clock" - for LD20 SoC.
- #clock-cells: should be 1.
Example:
mioctrl@59810000 {
compatible = "socionext,uniphier-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
clock {
compatible = "socionext,uniphier-ld20-mio-clock";
#clock-cells = <1>;
};
other nodes ...
};
Provided clocks:
0: SD ch0 host
1: eMMC host
2: SD ch1 host
7: MIO DMAC
8: USB2 ch0 host
9: USB2 ch1 host
10: USB2 ch2 host
11: USB2 ch3 host
12: USB2 ch0 PHY
13: USB2 ch1 PHY
14: USB2 ch2 PHY
15: USB2 ch3 PHY
Peripheral clock
----------------
Required properties:
- compatible: should be one of the following:
"socionext,uniphier-sld3-peri-clock" - for sLD3 SoC.
"socionext,uniphier-ld4-peri-clock" - for LD4 SoC.
"socionext,uniphier-pro4-peri-clock" - for Pro4 SoC.
"socionext,uniphier-sld8-peri-clock" - for sLD8 SoC.
"socionext,uniphier-pro5-peri-clock" - for Pro5 SoC.
"socionext,uniphier-pxs2-peri-clock" - for PXs2/LD6b SoC.
"socionext,uniphier-ld11-peri-clock" - for LD11 SoC.
"socionext,uniphier-ld20-peri-clock" - for LD20 SoC.
- #clock-cells: should be 1.
Example:
perictrl@59820000 {
compatible = "socionext,uniphier-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
clock {
compatible = "socionext,uniphier-ld20-peri-clock";
#clock-cells = <1>;
};
other nodes ...
};
Provided clocks:
0: UART ch0
1: UART ch1
2: UART ch2
3: UART ch3
4: I2C ch0
5: I2C ch1
6: I2C ch2
7: I2C ch3
8: I2C ch4
9: I2C ch5
10: I2C ch6

18
dts/Bindings/clock/xgene.txt
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@ -8,6 +8,7 @@ Required properties:
- compatible : shall be one of the following:
"apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
"apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
"apm,xgene-pmd-clock" - for a X-Gene PMD clock
"apm,xgene-device-clock" - for a X-Gene device clock
"apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
"apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
@ -22,6 +23,15 @@ Required properties for SoC or PCP PLL clocks:
Optional properties for PLL clocks:
- clock-names : shall be the name of the PLL. If missing, use the device name.
Required properties for PMD clocks:
- reg : shall be the physical register address for the pmd clock.
- clocks : shall be the input parent clock phandle for the clock.
- #clock-cells : shall be set to 1.
- clock-output-names : shall be the name of the clock referenced by derive
clock.
Optional properties for PLL clocks:
- clock-names : shall be the name of the clock. If missing, use the device name.
Required properties for device clocks:
- reg : shall be a list of address and length pairs describing the CSR
reset and/or the divider. Either may be omitted, but at least
@ -59,6 +69,14 @@ For example:
type = <0>;
};
pmd0clk: pmd0clk@7e200200 {
compatible = "apm,xgene-pmd-clock";
#clock-cells = <1>;
clocks = <&pmdpll 0>;
reg = <0x0 0x7e200200 0x0 0x10>;
clock-output-names = "pmd0clk";
};
socpll: socpll@17000120 {
compatible = "apm,xgene-socpll-clock";
#clock-cells = <1>;

35
dts/Bindings/clock/zx296718-clk.txt Normal file
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@ -0,0 +1,35 @@
Device Tree Clock bindings for ZTE zx296718
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be one of the following:
"zte,zx296718-topcrm":
zx296718 top clock selection, divider and gating
"zte,zx296718-lsp0crm" and
"zte,zx296718-lsp1crm":
zx296718 device level clock selection and gating
- reg: Address and length of the register set
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296718-clock.h
for the full list of zx296718 clock IDs.
topclk: topcrm@1461000 {
compatible = "zte,zx296718-topcrm-clk";
reg = <0x01461000 0x1000>;
#clock-cells = <1>;
};
usbphy0:usb-phy0 {
compatible = "zte,zx296718-usb-phy";
#phy-cells = <0>;
clocks = <&topclk USB20_PHY_CLK>;
clock-names = "phyclk";
status = "okay";
};

19
dts/Bindings/devfreq/event/rockchip-dfi.txt Normal file
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@ -0,0 +1,19 @@
* Rockchip rk3399 DFI device
Required properties:
- compatible: Must be "rockchip,rk3399-dfi".
- reg: physical base address of each DFI and length of memory mapped region
- rockchip,pmu: phandle to the syscon managing the "pmu general register files"
- clocks: phandles for clock specified in "clock-names" property
- clock-names : the name of clock used by the DFI, must be "pclk_ddr_mon";
Example:
dfi: dfi@0xff630000 {
compatible = "rockchip,rk3399-dfi";
reg = <0x00 0xff630000 0x00 0x4000>;
rockchip,pmu = <&pmugrf>;
clocks = <&cru PCLK_DDR_MON>;
clock-names = "pclk_ddr_mon";
status = "disabled";
};

209
dts/Bindings/devfreq/rk3399_dmc.txt Normal file
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@ -0,0 +1,209 @@
* Rockchip rk3399 DMC(Dynamic Memory Controller) device
Required properties:
- compatible: Must be "rockchip,rk3399-dmc".
- devfreq-events: Node to get DDR loading, Refer to
Documentation/devicetree/bindings/devfreq/
rockchip-dfi.txt
- interrupts: The interrupt number to the CPU. The interrupt
specifier format depends on the interrupt controller.
It should be DCF interrupts, when DDR dvfs finish,
it will happen.
- clocks: Phandles for clock specified in "clock-names" property
- clock-names : The name of clock used by the DFI, must be
"pclk_ddr_mon";
- operating-points-v2: Refer to Documentation/devicetree/bindings/power/opp.txt
for details.
- center-supply: DMC supply node.
- status: Marks the node enabled/disabled.
Following properties are ddr timing:
- rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/ddr.h,
it select ddr3 cl-trp-trcd type, default value
"DDR3_DEFAULT".it must selected according to
"Speed Bin" in ddr3 datasheet, DO NOT use
smaller "Speed Bin" than ddr3 exactly is.
- rockchip,pd_idle : Config the PD_IDLE value, defined the power-down
idle period, memories are places into power-down
mode if bus is idle for PD_IDLE DFI clocks.
- rockchip,sr_idle : Configure the SR_IDLE value, defined the
selfrefresh idle period, memories are places
into self-refresh mode if bus is idle for
SR_IDLE*1024 DFI clocks (DFI clocks freq is
half of dram's clocks), defaule value is "0".
- rockchip,sr_mc_gate_idle : Defined the self-refresh with memory and
controller clock gating idle period, memories
are places into self-refresh mode and memory
controller clock arg gating if bus is idle for
sr_mc_gate_idle*1024 DFI clocks.
- rockchip,srpd_lite_idle : Defined the self-refresh power down idle
period, memories are places into self-refresh
power down mode if bus is idle for
srpd_lite_idle*1024 DFI clocks. This parameter
is for LPDDR4 only.
- rockchip,standby_idle : Defined the standby idle period, memories are
places into self-refresh than controller, pi,
phy and dram clock will gating if bus is idle
for standby_idle * DFI clocks.
- rockchip,dram_dll_disb_freq : It's defined the DDR3 dll bypass frequency in
MHz, when ddr freq less than DRAM_DLL_DISB_FREQ,
ddr3 dll will bypssed note: if dll was bypassed,
the odt also stop working.
- rockchip,phy_dll_disb_freq : Defined the PHY dll bypass frequency in
MHz (Mega Hz), when ddr freq less than
DRAM_DLL_DISB_FREQ, phy dll will bypssed.
note: phy dll and phy odt are independent.
- rockchip,ddr3_odt_disb_freq : When dram type is DDR3, this parameter defined
the odt disable frequency in MHz (Mega Hz),
when ddr frequency less then ddr3_odt_disb_freq,
the odt on dram side and controller side are
both disabled.
- rockchip,ddr3_drv : When dram type is DDR3, this parameter define
the dram side driver stength in ohm, default
value is DDR3_DS_40ohm.
- rockchip,ddr3_odt : When dram type is DDR3, this parameter define
the dram side ODT stength in ohm, default value
is DDR3_ODT_120ohm.
- rockchip,phy_ddr3_ca_drv : When dram type is DDR3, this parameter define
the phy side CA line(incluing command line,
address line and clock line) driver strength.
Default value is PHY_DRV_ODT_40.
- rockchip,phy_ddr3_dq_drv : When dram type is DDR3, this parameter define
the phy side DQ line(incluing DQS/DQ/DM line)
driver strength. default value is PHY_DRV_ODT_40.
- rockchip,phy_ddr3_odt : When dram type is DDR3, this parameter define the
phy side odt strength, default value is
PHY_DRV_ODT_240.
- rockchip,lpddr3_odt_disb_freq : When dram type is LPDDR3, this parameter defined
then odt disable frequency in MHz (Mega Hz),
when ddr frequency less then ddr3_odt_disb_freq,
the odt on dram side and controller side are
both disabled.
- rockchip,lpddr3_drv : When dram type is LPDDR3, this parameter define
the dram side driver stength in ohm, default
value is LP3_DS_34ohm.
- rockchip,lpddr3_odt : When dram type is LPDDR3, this parameter define
the dram side ODT stength in ohm, default value
is LP3_ODT_240ohm.
- rockchip,phy_lpddr3_ca_drv : When dram type is LPDDR3, this parameter define
the phy side CA line(incluing command line,
address line and clock line) driver strength.
default value is PHY_DRV_ODT_40.
- rockchip,phy_lpddr3_dq_drv : When dram type is LPDDR3, this parameter define
the phy side DQ line(incluing DQS/DQ/DM line)
driver strength. default value is
PHY_DRV_ODT_40.
- rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define
the phy side odt strength, default value is
PHY_DRV_ODT_240.
- rockchip,lpddr4_odt_disb_freq : When dram type is LPDDR4, this parameter
defined the odt disable frequency in
MHz (Mega Hz), when ddr frequency less then
ddr3_odt_disb_freq, the odt on dram side and
controller side are both disabled.
- rockchip,lpddr4_drv : When dram type is LPDDR4, this parameter define
the dram side driver stength in ohm, default
value is LP4_PDDS_60ohm.
- rockchip,lpddr4_dq_odt : When dram type is LPDDR4, this parameter define
the dram side ODT on dqs/dq line stength in ohm,
default value is LP4_DQ_ODT_40ohm.
- rockchip,lpddr4_ca_odt : When dram type is LPDDR4, this parameter define
the dram side ODT on ca line stength in ohm,
default value is LP4_CA_ODT_40ohm.
- rockchip,phy_lpddr4_ca_drv : When dram type is LPDDR4, this parameter define
the phy side CA line(incluing command address
line) driver strength. default value is
PHY_DRV_ODT_40.
- rockchip,phy_lpddr4_ck_cs_drv : When dram type is LPDDR4, this parameter define
the phy side clock line and cs line driver
strength. default value is PHY_DRV_ODT_80.
- rockchip,phy_lpddr4_dq_drv : When dram type is LPDDR4, this parameter define
the phy side DQ line(incluing DQS/DQ/DM line)
driver strength. default value is PHY_DRV_ODT_80.
- rockchip,phy_lpddr4_odt : When dram type is LPDDR4, this parameter define
the phy side odt strength, default value is
PHY_DRV_ODT_60.
Example:
dmc_opp_table: dmc_opp_table {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <900000>;
};
opp01 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <900000>;
};
};
dmc: dmc {
compatible = "rockchip,rk3399-dmc";
devfreq-events = <&dfi>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_DDRCLK>;
clock-names = "dmc_clk";
operating-points-v2 = <&dmc_opp_table>;
center-supply = <&ppvar_centerlogic>;
upthreshold = <15>;
downdifferential = <10>;
rockchip,ddr3_speed_bin = <21>;
rockchip,pd_idle = <0x40>;
rockchip,sr_idle = <0x2>;
rockchip,sr_mc_gate_idle = <0x3>;
rockchip,srpd_lite_idle = <0x4>;
rockchip,standby_idle = <0x2000>;
rockchip,dram_dll_dis_freq = <300>;
rockchip,phy_dll_dis_freq = <125>;
rockchip,auto_pd_dis_freq = <666>;
rockchip,ddr3_odt_dis_freq = <333>;
rockchip,ddr3_drv = <DDR3_DS_40ohm>;
rockchip,ddr3_odt = <DDR3_ODT_120ohm>;
rockchip,phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;
rockchip,phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;
rockchip,phy_ddr3_odt = <PHY_DRV_ODT_240>;
rockchip,lpddr3_odt_dis_freq = <333>;
rockchip,lpddr3_drv = <LP3_DS_34ohm>;
rockchip,lpddr3_odt = <LP3_ODT_240ohm>;
rockchip,phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>;
rockchip,phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>;
rockchip,phy_lpddr3_odt = <PHY_DRV_ODT_240>;
rockchip,lpddr4_odt_dis_freq = <333>;
rockchip,lpddr4_drv = <LP4_PDDS_60ohm>;
rockchip,lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
rockchip,lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
rockchip,phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;
rockchip,phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
rockchip,phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
rockchip,phy_lpddr4_odt = <PHY_DRV_ODT_60>;
status = "disabled";
};

48
dts/Bindings/display/bridge/dumb-vga-dac.txt Normal file
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@ -0,0 +1,48 @@
Dumb RGB to VGA DAC bridge
---------------------------
This binding is aimed for dumb RGB to VGA DAC based bridges that do not require
any configuration.
Required properties:
- compatible: Must be "dumb-vga-dac"
Required nodes:
This device has two video ports. Their connections are modelled using the OF
graph bindings specified in Documentation/devicetree/bindings/graph.txt.
- Video port 0 for RGB input
- Video port 1 for VGA output
Example
-------
bridge {
compatible = "dumb-vga-dac";
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
vga_bridge_in: endpoint {
remote-endpoint = <&tcon0_out_vga>;
};
};
port@1 {
reg = <1>;
vga_bridge_out: endpoint {
remote-endpoint = <&vga_con_in>;
};
};
};
};

18
dts/Bindings/display/bridge/tda998x.txt
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@ -21,8 +21,19 @@ Optional properties:
- video-ports: 24 bits value which defines how the video controller
output is wired to the TDA998x input - default: <0x230145>
- audio-ports: array of 8-bit values, 2 values per one DAI[1].
The first value defines the DAI type: TDA998x_SPDIF or TDA998x_I2S[2].
The second value defines the tda998x AP_ENA reg content when the DAI
in question is used. The implementation allows one or two DAIs. If two
DAIs are defined, they must be of different type.
[1] Documentation/sound/alsa/soc/DAI.txt
[2] include/dt-bindings/display/tda998x.h
Example:
#include <dt-bindings/display/tda998x.h>
tda998x: hdmi-encoder {
compatible = "nxp,tda998x";
reg = <0x70>;
@ -30,4 +41,11 @@ Example:
interrupts = <27 2>; /* falling edge */
pinctrl-0 = <&pmx_camera>;
pinctrl-names = "default";
video-ports = <0x230145>;
#sound-dai-cells = <2>;
/* DAI-format AP_ENA reg value */
audio-ports = < TDA998x_SPDIF 0x04
TDA998x_I2S 0x03>;
};

4
dts/Bindings/display/exynos/exynos_hdmi.txt
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@ -9,7 +9,7 @@ Required properties:
- reg: physical base address of the hdmi and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
- hpd-gpio: following information about the hotplug gpio pin.
- hpd-gpios: following information about the hotplug gpio pin.
a) phandle of the gpio controller node.
b) pin number within the gpio controller.
c) optional flags and pull up/down.
@ -56,7 +56,7 @@ Example:
compatible = "samsung,exynos4212-hdmi";
reg = <0x14530000 0x100000>;
interrupts = <0 95 0>;
hpd-gpio = <&gpx3 7 1>;
hpd-gpios = <&gpx3 7 1>;
ddc = <&hdmi_ddc_node>;
phy = <&hdmi_phy_node>;
samsung,syscon-phandle = <&pmu_system_controller>;

9
dts/Bindings/display/msm/hdmi.txt
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@ -14,17 +14,16 @@ Required properties:
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: device clocks
See ../clocks/clock-bindings.txt for details.
- qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin
- qcom,hdmi-tx-ddc-data-gpio: ddc data pin
- qcom,hdmi-tx-hpd-gpio: hpd pin
- core-vdda-supply: phandle to supply regulator
- hdmi-mux-supply: phandle to mux regulator
- phys: the phandle for the HDMI PHY device
- phy-names: the name of the corresponding PHY device
Optional properties:
- qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin
- qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin
- hpd-gpios: hpd pin
- qcom,hdmi-tx-mux-en-gpios: hdmi mux enable pin
- qcom,hdmi-tx-mux-sel-gpios: hdmi mux select pin
- qcom,hdmi-tx-mux-lpm-gpios: hdmi mux lpm pin
- power-domains: reference to the power domain(s), if available.
- pinctrl-names: the pin control state names; should contain "default"
- pinctrl-0: the default pinctrl state (active)

7
dts/Bindings/display/panel/innolux,g101ice-l01.txt Normal file
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@ -0,0 +1,7 @@
Innolux Corporation 10.1" G101ICE-L01 WXGA (1280x800) LVDS panel
Required properties:
- compatible: should be "innolux,g101ice-l01"
This binding is compatible with the simple-panel binding, which is specified
in simple-panel.txt in this directory.

31
dts/Bindings/display/panel/jdi,lt070me05000.txt Normal file
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@ -0,0 +1,31 @@
JDI model LT070ME05000 1200x1920 7" DSI Panel
Required properties:
- compatible: should be "jdi,lt070me05000"
- vddp-supply: phandle of the regulator that provides the supply voltage
Power IC supply (3-5V)
- iovcc-supply: phandle of the regulator that provides the supply voltage
IOVCC , power supply for LCM (1.8V)
- enable-gpios: phandle of gpio for enable line
LED_EN, LED backlight enable, High active
- reset-gpios: phandle of gpio for reset line
This should be 8mA, gpio can be configured using mux, pinctrl, pinctrl-names
XRES, Reset, Low active
- dcdc-en-gpios: phandle of the gpio for power ic line
Power IC supply enable, High active
Example:
dsi0: qcom,mdss_dsi@4700000 {
panel@0 {
compatible = "jdi,lt070me05000";
reg = <0>;
vddp-supply = <&pm8921_l17>;
iovcc-supply = <&pm8921_lvs7>;
enable-gpios = <&pm8921_gpio 36 GPIO_ACTIVE_HIGH>;
reset-gpios = <&tlmm_pinmux 54 GPIO_ACTIVE_LOW>;
dcdc-en-gpios = <&pm8921_gpio 23 GPIO_ACTIVE_HIGH>;
};
};

47
dts/Bindings/display/panel/tpo,tpg110.txt Normal file
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@ -0,0 +1,47 @@
TPO TPG110 Panel
================
This binding builds on the DPI bindings, adding a few properties
as a superset of a DPI. See panel-dpi.txt for the required DPI
bindings.
Required properties:
- compatible : "tpo,tpg110"
- grestb-gpios : panel reset GPIO
- scen-gpios : serial control enable GPIO
- scl-gpios : serial control clock line GPIO
- sda-gpios : serial control data line GPIO
Required nodes:
- Video port for DPI input, see panel-dpi.txt
- Panel timing for DPI setup, see panel-dpi.txt
Example
-------
panel {
compatible = "tpo,tpg110", "panel-dpi";
grestb-gpios = <&stmpe_gpio44 5 GPIO_ACTIVE_LOW>;
scen-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
scl-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
backlight = <&bl>;
port {
nomadik_clcd_panel: endpoint {
remote-endpoint = <&nomadik_clcd_pads>;
};
};
panel-timing {
clock-frequency = <33200000>;
hactive = <800>;
hback-porch = <216>;
hfront-porch = <40>;
hsync-len = <1>;
vactive = <480>;
vback-porch = <35>;
vfront-porch = <10>;
vsync-len = <1>;
};
};

4
dts/Bindings/display/rockchip/rockchip-vop.txt
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@ -6,8 +6,10 @@ buffer to an external LCD interface.
Required properties:
- compatible: value should be one of the following
"rockchip,rk3288-vop";
"rockchip,rk3036-vop";
"rockchip,rk3288-vop";
"rockchip,rk3399-vop-big";
"rockchip,rk3399-vop-lit";
- interrupts: should contain a list of all VOP IP block interrupts in the
order: VSYNC, LCD_SYSTEM. The interrupt specifier

43
dts/Bindings/display/sunxi/sun4i-drm.txt
View File

@ -26,13 +26,14 @@ TCON
The TCON acts as a timing controller for RGB, LVDS and TV interfaces.
Required properties:
- compatible: value should be "allwinner,sun5i-a13-tcon".
- compatible: value must be either:
* allwinner,sun5i-a13-tcon
* allwinner,sun8i-a33-tcon
- reg: base address and size of memory-mapped region
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the TCON. Three are needed:
- 'ahb': the interface clocks
- 'tcon-ch0': The clock driving the TCON channel 0
- 'tcon-ch1': The clock driving the TCON channel 1
- resets: phandles to the reset controllers driving the encoder
- "lcd": the reset line for the TCON channel 0
@ -49,6 +50,33 @@ Required properties:
second the block connected to the TCON channel 1 (usually the TV
encoder)
On the A13, there is one more clock required:
- 'tcon-ch1': The clock driving the TCON channel 1
DRC
---
The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs
(A31, A23, A33), allows to dynamically adjust pixel
brightness/contrast based on histogram measurements for LCD content
adaptive backlight control.
Required properties:
- compatible: value must be one of:
* allwinner,sun8i-a33-drc
- reg: base address and size of the memory-mapped region.
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the DRC
* ahb: the DRC interface clock
* mod: the DRC module clock
* ram: the DRC DRAM clock
- clock-names: the clock names mentioned above
- resets: phandles to the reset line driving the DRC
- ports: A ports node with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt. The
first port should be the input endpoints, the second one the outputs
Display Engine Backend
----------------------
@ -59,6 +87,7 @@ system.
Required properties:
- compatible: value must be one of:
* allwinner,sun5i-a13-display-backend
* allwinner,sun8i-a33-display-backend
- reg: base address and size of the memory-mapped region.
- clocks: phandles to the clocks feeding the frontend and backend
* ahb: the backend interface clock
@ -71,6 +100,14 @@ Required properties:
Documentation/devicetree/bindings/media/video-interfaces.txt. The
first port should be the input endpoints, the second one the output
On the A33, some additional properties are required:
- reg needs to have an additional region corresponding to the SAT
- reg-names need to be set, with "be" and "sat"
- clocks and clock-names need to have a phandle to the SAT bus
clocks, whose name will be "sat"
- resets and reset-names need to have a phandle to the SAT bus
resets, whose name will be "sat"
Display Engine Frontend
-----------------------
@ -80,6 +117,7 @@ deinterlacing and color space conversion.
Required properties:
- compatible: value must be one of:
* allwinner,sun5i-a13-display-frontend
* allwinner,sun8i-a33-display-frontend
- reg: base address and size of the memory-mapped region.
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the frontend and backend
@ -104,6 +142,7 @@ extra node.
Required properties:
- compatible: value must be one of:
* allwinner,sun5i-a13-display-engine
* allwinner,sun8i-a33-display-engine
- allwinner,pipelines: list of phandle to the display engine
frontends available.

26
dts/Bindings/display/tilcdc/tilcdc.txt
View File

@ -17,6 +17,18 @@ Optional properties:
the lcd controller.
- max-pixelclock: The maximum pixel clock that can be supported
by the lcd controller in KHz.
- blue-and-red-wiring: Recognized values "straight" or "crossed".
This property deals with the LCDC revision 2 (found on AM335x)
color errata [1].
- "straight" indicates normal wiring that supports RGB565,
BGR888, and XBGR8888 color formats.
- "crossed" indicates wiring that has blue and red wires
crossed. This setup supports BGR565, RGB888 and XRGB8888
formats.
- If the property is not present or its value is not recognized
the legacy mode is assumed. This configuration supports RGB565,
RGB888 and XRGB8888 formats. However, depending on wiring, the red
and blue colors are swapped in either 16 or 24-bit color modes.
Optional nodes:
@ -24,6 +36,18 @@ Optional nodes:
binding follows Documentation/devicetree/bindings/graph.txt and
suppors a single port with a single endpoint.
- See also Documentation/devicetree/bindings/display/tilcdc/panel.txt and
Documentation/devicetree/bindings/display/tilcdc/tfp410.txt for connecting
tfp410 DVI encoder or lcd panel to lcdc
[1] There is an errata about AM335x color wiring. For 16-bit color mode
the wires work as they should (LCD_DATA[0:4] is for Blue[3:7]),
but for 24 bit color modes the wiring of blue and red components is
crossed and LCD_DATA[0:4] is for Red[3:7] and LCD_DATA[11:15] is
for Blue[3-7]. For more details see section 3.1.1 in AM335x
Silicon Errata:
http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360
Example:
fb: fb@4830e000 {
@ -33,6 +57,8 @@ Example:
interrupts = <36>;
ti,hwmods = "lcdc";
blue-and-red-wiring = "crossed";
port {
lcdc_0: endpoint@0 {
remote-endpoint = <&hdmi_0>;

1
dts/Bindings/dma/fsl-imx-sdma.txt
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@ -8,6 +8,7 @@ Required properties:
"fsl,imx51-sdma"
"fsl,imx53-sdma"
"fsl,imx6q-sdma"
"fsl,imx7d-sdma"
The -to variants should be preferred since they allow to determine the
correct ROM script addresses needed for the driver to work without additional
firmware.

4
dts/Bindings/dma/renesas,rcar-dmac.txt
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@ -1,4 +1,4 @@
* Renesas R-Car DMA Controller Device Tree bindings
* Renesas R-Car (RZ/G) DMA Controller Device Tree bindings
Renesas R-Car Generation 2 SoCs have multiple multi-channel DMA
controller instances named DMAC capable of serving multiple clients. Channels
@ -16,6 +16,8 @@ Required Properties:
- compatible: "renesas,dmac-<soctype>", "renesas,rcar-dmac" as fallback.
Examples with soctypes are:
- "renesas,dmac-r8a7743" (RZ/G1M)
- "renesas,dmac-r8a7745" (RZ/G1E)
- "renesas,dmac-r8a7790" (R-Car H2)
- "renesas,dmac-r8a7791" (R-Car M2-W)
- "renesas,dmac-r8a7792" (R-Car V2H)

1
dts/Bindings/dma/sun6i-dma.txt
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@ -7,6 +7,7 @@ Required properties:
- compatible: Must be one of
"allwinner,sun6i-a31-dma"
"allwinner,sun8i-a23-dma"
"allwinner,sun8i-a83t-dma"
"allwinner,sun8i-h3-dma"
- reg: Should contain the registers base address and length
- interrupts: Should contain a reference to the interrupt used by this device

41
dts/Bindings/extcon/qcom,pm8941-misc.txt Normal file
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@ -0,0 +1,41 @@
Qualcomm's PM8941 USB ID Extcon device
Some Qualcomm PMICs have a "misc" module that can be used to detect when
the USB ID pin has been pulled low or high.
PROPERTIES
- compatible:
Usage: required
Value type: <string>
Definition: Should contain "qcom,pm8941-misc";
- reg:
Usage: required
Value type: <u32>
Definition: Should contain the offset to the misc address space
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: Should contain the usb id interrupt
- interrupt-names:
Usage: required
Value type: <stringlist>
Definition: Should contain the string "usb_id" for the usb id interrupt
Example:
pmic {
usb_id: misc@900 {
compatible = "qcom,pm8941-misc";
reg = <0x900>;
interrupts = <0x0 0x9 0 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "usb_id";
};
}
usb-controller {
extcon = <&usb_id>;
};

15
dts/Bindings/firmware/meson/meson_sm.txt Normal file
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@ -0,0 +1,15 @@
* Amlogic Secure Monitor
In the Amlogic SoCs the Secure Monitor code is used to provide access to the
NVMEM, enable JTAG, set USB boot, etc...
Required properties for the secure monitor node:
- compatible: Should be "amlogic,meson-gxbb-sm"
Example:
firmware {
sm: secure-monitor {
compatible = "amlogic,meson-gxbb-sm";
};
};

46
dts/Bindings/gpio/brcm,bcm6345-gpio.txt Normal file
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@ -0,0 +1,46 @@
Bindings for the Broadcom's brcm,bcm6345-gpio memory-mapped GPIO controllers.
These bindings can be used on any BCM63xx SoC. However, BCM6338 and BCM6345
are the only ones which don't need a pinctrl driver.
BCM6338 have 8-bit data and dirout registers, where GPIO state can be read
and/or written, and the direction changed from input to output.
BCM6345 have 16-bit data and dirout registers, where GPIO state can be read
and/or written, and the direction changed from input to output.
Required properties:
- compatible: should be "brcm,bcm6345-gpio"
- reg-names: must contain
"dat" - data register
"dirout" - direction (output) register
- reg: address + size pairs describing the GPIO register sets;
order must correspond with the order of entries in reg-names
- #gpio-cells: must be set to 2. The first cell is the pin number and
the second cell is used to specify the gpio polarity:
0 = active high
1 = active low
- gpio-controller: Marks the device node as a gpio controller.
Optional properties:
- native-endian: use native endian memory.
Examples:
- BCM6338:
gpio: gpio-controller@fffe0407 {
compatible = "brcm,bcm6345-gpio";
reg-names = "dirout", "dat";
reg = <0xfffe0407 1>, <0xfffe040f 1>;
#gpio-cells = <2>;
gpio-controller;
};
- BCM6345:
gpio: gpio-controller@fffe0406 {
compatible = "brcm,bcm6345-gpio";
reg-names = "dirout", "dat";
reg = <0xfffe0406 2>, <0xfffe040a 2>;
native-endian;
#gpio-cells = <2>;
gpio-controller;
};

36
dts/Bindings/gpio/gpio-aspeed.txt Normal file
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@ -0,0 +1,36 @@
Aspeed GPIO controller Device Tree Bindings
-------------------------------------------
Required properties:
- compatible : Either "aspeed,ast2400-gpio" or "aspeed,ast2500-gpio"
- #gpio-cells : Should be two
- First cell is the GPIO line number
- Second cell is used to specify optional
parameters (unused)
- reg : Address and length of the register set for the device
- gpio-controller : Marks the device node as a GPIO controller.
- interrupts : Interrupt specifier (see interrupt bindings for
details)
- interrupt-controller : Mark the GPIO controller as an interrupt-controller
Optional properties:
- interrupt-parent : The parent interrupt controller, optional if inherited
The gpio and interrupt properties are further described in their respective
bindings documentation:
- Documentation/devicetree/bindings/gpio/gpio.txt
- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
Example:
gpio@1e780000 {
#gpio-cells = <2>;
compatible = "aspeed,ast2400-gpio";
gpio-controller;
interrupts = <20>;
reg = <0x1e780000 0x1000>;
interrupt-controller;
};

30
dts/Bindings/gpio/gpio-axp209.txt Normal file
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@ -0,0 +1,30 @@
AXP209 GPIO controller
This driver follows the usual GPIO bindings found in
Documentation/devicetree/bindings/gpio/gpio.txt
Required properties:
- compatible: Should be "x-powers,axp209-gpio"
- #gpio-cells: Should be two. The first cell is the pin number and the
second is the GPIO flags.
- gpio-controller: Marks the device node as a GPIO controller.
This node must be a subnode of the axp20x PMIC, documented in
Documentation/devicetree/bindings/mfd/axp20x.txt
Example:
axp209: pmic@34 {
compatible = "x-powers,axp209";
reg = <0x34>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
axp_gpio: gpio {
compatible = "x-powers,axp209-gpio";
gpio-controller;
#gpio-cells = <2>;
};
};

16
dts/Bindings/gpio/gpio-tpic2810.txt Normal file
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@ -0,0 +1,16 @@
TPIC2810 GPIO controller bindings
Required properties:
- compatible : Should be "ti,tpic2810".
- reg : The I2C address of the device
- gpio-controller : Marks the device node as a GPIO controller.
- #gpio-cells : Should be two. For consumer use see gpio.txt.
Example:
gpio@60 {
compatible = "ti,tpic2810";
reg = <0x60>;
gpio-controller;
#gpio-cells = <2>;
};

16
dts/Bindings/gpio/gpio-tps65086.txt
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@ -1,16 +0,0 @@
* TPS65086 GPO Controller bindings
Required properties:
- compatible : Should be "ti,tps65086-gpio".
- gpio-controller : Marks the device node as a GPIO Controller.
- #gpio-cells : Should be two. The first cell is the pin number
and the second cell is used to specify flags.
See ../gpio/gpio.txt for possible values.
Example:
gpio4: gpio {
compatible = "ti,tps65086-gpio";
gpio-controller;
#gpio-cells = <2>;
};

30
dts/Bindings/gpio/gpio-ts4900.txt Normal file
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@ -0,0 +1,30 @@
* Technologic Systems I2C-FPGA's GPIO controller bindings
This bindings describes the GPIO controller for Technologic's FPGA core.
TS-4900's FPGA encodes the GPIO state on 3 bits, whereas the TS-7970's FPGA
uses 2 bits: it doesn't use a dedicated input bit.
Required properties:
- compatible: Should be one of the following
"technologic,ts4900-gpio"
"technologic,ts7970-gpio"
- reg: Physical base address of the controller and length
of memory mapped region.
- #gpio-cells: Should be two. The first cell is the pin number.
- gpio-controller: Marks the device node as a gpio controller.
Optional property:
- ngpios: Number of GPIOs this controller is instantiated with,
the default is 32. See gpio.txt for more details.
Example:
&i2c2 {
gpio8: gpio@28 {
compatible = "technologic,ts4900-gpio";
reg = <0x28>;
#gpio-cells = <2>;
gpio-controller;
ngpios = <32>;
};
};

23
dts/Bindings/gpio/mrvl-gpio.txt
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@ -44,26 +44,3 @@ Example for a PXA3xx platform:
interrupt-controller;
#interrupt-cells = <0x2>;
};
* Marvell Orion GPIO Controller
Required properties:
- compatible : Should be "marvell,orion-gpio"
- reg : Address and length of the register set for controller.
- gpio-controller : So we know this is a gpio controller.
- ngpio : How many gpios this controller has.
- interrupts : Up to 4 Interrupts for the controller.
Optional properties:
- mask-offset : For SMP Orions, offset for Nth CPU
Example:
gpio0: gpio@10100 {
compatible = "marvell,orion-gpio";
#gpio-cells = <2>;
gpio-controller;
reg = <0x10100 0x40>;
ngpio = <32>;
interrupts = <35>, <36>, <37>, <38>;
};

1
dts/Bindings/gpio/renesas,gpio-rcar.txt
View File

@ -11,6 +11,7 @@ Required Properties:
- "renesas,gpio-r8a7793": for R8A7793 (R-Car M2-N) compatible GPIO controller.
- "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller.
- "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller.
- "renesas,gpio-r8a7796": for R8A7796 (R-Car M3-W) compatible GPIO controller.
- "renesas,gpio-rcar": for generic R-Car GPIO controller.
- reg: Base address and length of each memory resource used by the GPIO

18
dts/Bindings/hwmon/ltc4151.txt Normal file
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@ -0,0 +1,18 @@
LTC4151 High Voltage I2C Current and Voltage Monitor
Required properties:
- compatible: Must be "lltc,ltc4151"
- reg: I2C address
Optional properties:
- shunt-resistor-micro-ohms
Shunt resistor value in micro-Ohms
Defaults to <1000> if unset.
Example:
ltc4151@6e {
compatible = "lltc,ltc4151";
reg = <0x6e>;
shunt-resistor-micro-ohms = <1500>;
};

28
dts/Bindings/hwmon/max6650.txt Normal file
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@ -0,0 +1,28 @@
Bindings for MAX6651 and MAX6650 I2C fan controllers
Reference:
[1] https://datasheets.maximintegrated.com/en/ds/MAX6650-MAX6651.pdf
Required properties:
- compatible : One of "maxim,max6650" or "maxim,max6651"
- reg : I2C address, one of 0x1b, 0x1f, 0x4b, 0x48.
Optional properties, default is to retain the chip's current setting:
- maxim,fan-microvolt : The supply voltage of the fan, either 5000000 uV or
12000000 uV.
- maxim,fan-prescale : Pre-scaling value, as per datasheet [1]. Lower values
allow more fine-grained control of slower fans.
Valid: 1, 2, 4, 8, 16.
- maxim,fan-target-rpm: Initial requested fan rotation speed. If specified, the
driver selects closed-loop mode and the requested speed.
This ensures the fan is already running before userspace
takes over.
Example:
fan-max6650: max6650@1b {
reg = <0x1b>;
compatible = "maxim,max6650";
maxim,fan-microvolt = <12000000>;
maxim,fan-prescale = <4>;
maxim,fan-target-rpm = <1200>;
};

8
dts/Bindings/i2c/i2c-arb-gpio-challenge.txt
View File

@ -44,8 +44,7 @@ Required properties:
- our-claim-gpio: The GPIO that we use to claim the bus.
- their-claim-gpios: The GPIOs that the other sides use to claim the bus.
Note that some implementations may only support a single other master.
- Standard I2C mux properties. See i2c-mux.txt in this directory.
- Single I2C child bus node at reg 0. See i2c-mux.txt in this directory.
- I2C arbitration bus node. See i2c-arb.txt in this directory.
Optional properties:
- slew-delay-us: microseconds to wait for a GPIO to go high. Default is 10 us.
@ -63,8 +62,6 @@ Example:
i2c-arbitrator {
compatible = "i2c-arb-gpio-challenge";
#address-cells = <1>;
#size-cells = <0>;
i2c-parent = <&{/i2c@12CA0000}>;
@ -74,8 +71,7 @@ Example:
wait-retry-us = <3000>;
wait-free-us = <50000>;
i2c@0 {
reg = <0>;
i2c-arb {
#address-cells = <1>;
#size-cells = <0>;

35
dts/Bindings/i2c/i2c-arb.txt Normal file
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@ -0,0 +1,35 @@
Common i2c arbitration bus properties.
- i2c-arb child node
Required properties for the i2c-arb child node:
- #address-cells = <1>;
- #size-cells = <0>;
Optional properties for i2c-arb child node:
- Child nodes conforming to i2c bus binding
Example :
/*
An NXP pca9541 I2C bus master selector at address 0x74
with a NXP pca8574 GPIO expander attached.
*/
arb@74 {
compatible = "nxp,pca9541";
reg = <0x74>;
i2c-arb {
#address-cells = <1>;
#size-cells = <0>;
gpio@38 {
compatible = "nxp,pca8574";
reg = <0x38>;
#gpio-cells = <2>;
gpio-controller;
};
};
};

41
dts/Bindings/i2c/i2c-gate.txt Normal file
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@ -0,0 +1,41 @@
An i2c gate is useful to e.g. reduce the digital noise for RF tuners connected
to the i2c bus. Gates are similar to arbitrators in that you need to perform
some kind of operation to access the i2c bus past the arbitrator/gate, but
there are no competing masters to consider for gates and therefore there is
no arbitration happening for gates.
Common i2c gate properties.
- i2c-gate child node
Required properties for the i2c-gate child node:
- #address-cells = <1>;
- #size-cells = <0>;
Optional properties for i2c-gate child node:
- Child nodes conforming to i2c bus binding
Example :
/*
An Invensense mpu9150 at address 0x68 featuring an on-chip Asahi
Kasei ak8975 compass behind a gate.
*/
mpu9150@68 {
compatible = "invensense,mpu9150";
reg = <0x68>;
interrupt-parent = <&gpio1>;
interrupts = <18 1>;
i2c-gate {
#address-cells = <1>;
#size-cells = <0>;
ax8975@c {
compatible = "ak,ak8975";
reg = <0x0c>;
};
};
};

2
dts/Bindings/i2c/i2c-meson.txt
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@ -1,7 +1,7 @@
Amlogic Meson I2C controller
Required properties:
- compatible: must be "amlogic,meson6-i2c"
- compatible: must be "amlogic,meson6-i2c" or "amlogic,meson-gxbb-i2c"
- reg: physical address and length of the device registers
- interrupts: a single interrupt specifier
- clocks: clock for the device

23
dts/Bindings/i2c/i2c-mux.txt
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@ -2,19 +2,32 @@ Common i2c bus multiplexer/switch properties.
An i2c bus multiplexer/switch will have several child busses that are
numbered uniquely in a device dependent manner. The nodes for an i2c bus
multiplexer/switch will have one child node for each child
bus.
multiplexer/switch will have one child node for each child bus.
Required properties:
Optional properties:
- #address-cells = <1>;
This property is required is the i2c-mux child node does not exist.
- #size-cells = <0>;
This property is required is the i2c-mux child node does not exist.
- i2c-mux
For i2c multiplexers/switches that have child nodes that are a mixture
of both i2c child busses and other child nodes, the 'i2c-mux' subnode
can be used for populating the i2c child busses. If an 'i2c-mux'
subnode is present, only subnodes of this will be considered as i2c
child busses.
Required properties for the i2c-mux child node:
- #address-cells = <1>;
- #size-cells = <0>;
Required properties for child nodes:
Required properties for i2c child bus nodes:
- #address-cells = <1>;
- #size-cells = <0>;
- reg : The sub-bus number.
Optional properties for child nodes:
Optional properties for i2c child bus nodes:
- Other properties specific to the multiplexer/switch hardware.
- Child nodes conforming to i2c bus binding

1
dts/Bindings/i2c/i2c-rcar.txt
View File

@ -11,6 +11,7 @@ Required properties:
"renesas,i2c-r8a7793"
"renesas,i2c-r8a7794"
"renesas,i2c-r8a7795"
"renesas,i2c-r8a7796"
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt specifier.

8
dts/Bindings/i2c/i2c.txt
View File

@ -32,6 +32,14 @@ wants to support one of the below features, it should adapt the bindings below.
- clock-frequency
frequency of bus clock in Hz.
- i2c-bus
For I2C adapters that have child nodes that are a mixture of both I2C
devices and non-I2C devices, the 'i2c-bus' subnode can be used for
populating I2C devices. If the 'i2c-bus' subnode is present, only
subnodes of this will be considered as I2C slaves. The properties,
'#address-cells' and '#size-cells' must be defined under this subnode
if present.
- i2c-scl-falling-time-ns
Number of nanoseconds the SCL signal takes to fall; t(f) in the I2C
specification.

29
dts/Bindings/i2c/nxp,pca9541.txt Normal file
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@ -0,0 +1,29 @@
* NXP PCA9541 I2C bus master selector
Required Properties:
- compatible: Must be "nxp,pca9541"
- reg: The I2C address of the device.
The following required properties are defined externally:
- I2C arbitration bus node. See i2c-arb.txt in this directory.
Example:
i2c-arbitrator@74 {
compatible = "nxp,pca9541";
reg = <0x74>;
i2c-arb {
#address-cells = <1>;
#size-cells = <0>;
eeprom@54 {
compatible = "at,24c08";
reg = <0x54>;
};
};
};

3
dts/Bindings/i2c/trivial-devices.txt
View File

@ -38,6 +38,7 @@ dallas,ds4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O
dallas,ds75 Digital Thermometer and Thermostat
dlg,da9053 DA9053: flexible system level PMIC with multicore support
dlg,da9063 DA9063: system PMIC for quad-core application processors
domintech,dmard09 DMARD09: 3-axis Accelerometer
epson,rx8010 I2C-BUS INTERFACE REAL TIME CLOCK MODULE
epson,rx8025 High-Stability. I2C-Bus INTERFACE REAL TIME CLOCK MODULE
epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE
@ -50,12 +51,12 @@ fsl,sgtl5000 SGTL5000: Ultra Low-Power Audio Codec
gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface
infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz)
infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz)
isil,isl12057 Intersil ISL12057 I2C RTC Chip
isil,isl29028 Intersil ISL29028 Ambient Light and Proximity Sensor
maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator
maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface
mc,rv3029c2 Real Time Clock Module with I2C-Bus
mcube,mc3230 mCube 3-axis 8-bit digital accelerometer
microchip,mcp4531-502 Microchip 7-bit Single I2C Digital Potentiometer (5k)
microchip,mcp4531-103 Microchip 7-bit Single I2C Digital Potentiometer (10k)
microchip,mcp4531-503 Microchip 7-bit Single I2C Digital Potentiometer (50k)

19
dts/Bindings/iio/accel/dmard06.txt Normal file
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@ -0,0 +1,19 @@
Device tree bindings for Domintech DMARD05, DMARD06, DMARD07 accelerometers
Required properties:
- compatible : Should be "domintech,dmard05"
or "domintech,dmard06"
or "domintech,dmard07"
- reg : I2C address of the chip. Should be 0x1c
Example:
&i2c1 {
/* ... */
accelerometer@1c {
compatible = "domintech,dmard06";
reg = <0x1c>;
};
/* ... */
};

22
dts/Bindings/iio/accel/kionix,kxsd9.txt Normal file
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@ -0,0 +1,22 @@
Kionix KXSD9 Accelerometer device tree bindings
Required properties:
- compatible: should be set to "kionix,kxsd9"
- reg: i2c slave address
Optional properties:
- vdd-supply: The input supply for VDD
- iovdd-supply: The input supply for IOVDD
- interrupts: The movement detection interrupt
- mount-matrix: See mount-matrix.txt
Example:
kxsd9@18 {
compatible = "kionix,kxsd9";
reg = <0x18>;
interrupt-parent = <&foo>;
interrupts = <57 IRQ_TYPE_EDGE_FALLING>;
iovdd-supply = <&bar>;
vdd-supply = <&baz>;
};

29
dts/Bindings/iio/adc/mt6577_auxadc.txt Normal file
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@ -0,0 +1,29 @@
* Mediatek AUXADC - Analog to Digital Converter on Mediatek mobile soc (mt65xx/mt81xx/mt27xx)
===============
The Auxiliary Analog/Digital Converter (AUXADC) is an ADC found
in some Mediatek SoCs which among other things measures the temperatures
in the SoC. It can be used directly with register accesses, but it is also
used by thermal controller which reads the temperatures from the AUXADC
directly via its own bus interface. See
Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
for the Thermal Controller which holds a phandle to the AUXADC.
Required properties:
- compatible: Should be one of:
- "mediatek,mt2701-auxadc": For MT2701 family of SoCs
- "mediatek,mt8173-auxadc": For MT8173 family of SoCs
- reg: Address range of the AUXADC unit.
- clocks: Should contain a clock specifier for each entry in clock-names
- clock-names: Should contain "main".
- #io-channel-cells: Should be 1, see ../iio-bindings.txt
Example:
auxadc: adc@11001000 {
compatible = "mediatek,mt2701-auxadc";
reg = <0 0x11001000 0 0x1000>;
clocks = <&pericfg CLK_PERI_AUXADC>;
clock-names = "main";
#io-channel-cells = <1>;
};

37
dts/Bindings/iio/adc/ti-adc12138.txt Normal file
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@ -0,0 +1,37 @@
* Texas Instruments' ADC12130/ADC12132/ADC12138
Required properties:
- compatible: Should be one of
* "ti,adc12130"
* "ti,adc12132"
* "ti,adc12138"
- reg: SPI chip select number for the device
- interrupts: Should contain interrupt for EOC (end of conversion)
- clocks: phandle to conversion clock input
- spi-max-frequency: Definision as per
Documentation/devicetree/bindings/spi/spi-bus.txt
- vref-p-supply: The regulator supply for positive analog voltage reference
Optional properties:
- vref-n-supply: The regulator supply for negative analog voltage reference
(Note that this must not go below GND or exceed vref-p)
If not specified, this is assumed to be analog ground.
- ti,acquisition-time: The number of conversion clock periods for the S/H's
acquisition time. Should be one of 6, 10, 18, 34. If not specified,
default value of 10 is used.
For high source impedances, this value can be increased to 18 or 34.
For less ADC accuracy and/or slower CCLK frequencies this value may be
decreased to 6. See section 6.0 INPUT SOURCE RESISTANCE in the
datasheet for details.
Example:
adc@0 {
compatible = "ti,adc12138";
reg = <0>;
interrupts = <28 IRQ_TYPE_EDGE_RISING>;
interrupt-parent = <&gpio1>;
clocks = <&cclk>;
vref-p-supply = <&ldo4_reg>;
spi-max-frequency = <5000000>;
ti,acquisition-time = <6>;
};

16
dts/Bindings/iio/adc/ti-adc161s626.txt Normal file
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@ -0,0 +1,16 @@
* Texas Instruments ADC141S626 and ADC161S626 chips
Required properties:
- compatible: Should be "ti,adc141s626" or "ti,adc161s626"
- reg: spi chip select number for the device
Recommended properties:
- spi-max-frequency: Definition as per
Documentation/devicetree/bindings/spi/spi-bus.txt
Example:
adc@0 {
compatible = "ti,adc161s626";
reg = <0>;
spi-max-frequency = <4300000>;
};

22
dts/Bindings/iio/chemical/atlas,orp-sm.txt Normal file
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@ -0,0 +1,22 @@
* Atlas Scientific ORP-SM OEM sensor
https://www.atlas-scientific.com/_files/_datasheets/_oem/ORP_oem_datasheet.pdf
Required properties:
- compatible: must be "atlas,orp-sm"
- reg: the I2C address of the sensor
- interrupt-parent: should be the phandle for the interrupt controller
- interrupts: the sole interrupt generated by the device
Refer to interrupt-controller/interrupts.txt for generic interrupt client
node bindings.
Example:
atlas@66 {
compatible = "atlas,orp-sm";
reg = <0x66>;
interrupt-parent = <&gpio1>;
interrupts = <16 2>;
};

29
dts/Bindings/iio/magnetometer/ak8974.txt Normal file
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@ -0,0 +1,29 @@
* Asahi Kasei AK8974 magnetometer sensor
Required properties:
- compatible : should be "asahi-kasei,ak8974"
- reg : the I2C address of the magnetometer
Optional properties:
- avdd-supply: regulator supply for the analog voltage
(see regulator/regulator.txt)
- dvdd-supply: regulator supply for the digital voltage
(see regulator/regulator.txt)
- interrupts: data ready (DRDY) and interrupt (INT1) lines
from the chip, the DRDY interrupt must be placed first.
The interrupts can be triggered on rising or falling
edges alike.
- mount-matrix: an optional 3x3 mounting rotation matrix
Example:
ak8974@0f {
compatible = "asahi-kasei,ak8974";
reg = <0x0f>;
avdd-supply = <&foo_reg>;
dvdd-supply = <&bar_reg>;
interrupts = <0 IRQ_TYPE_EDGE_RISING>,
<1 IRQ_TYPE_EDGE_RISING>;
};

31
dts/Bindings/iio/pressure/zpa2326.txt Normal file
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@ -0,0 +1,31 @@
Murata ZPA2326 pressure sensor
Pressure sensor from Murata with SPI and I2C bus interfaces.
Required properties:
- compatible: "murata,zpa2326"
- reg: the I2C address or SPI chip select the device will respond to
Recommended properties for SPI bus usage:
- spi-max-frequency: maximum SPI bus frequency as documented in
Documentation/devicetree/bindings/spi/spi-bus.txt
Optional properties:
- vref-supply: an optional regulator that needs to be on to provide VREF
power to the sensor
- vdd-supply: an optional regulator that needs to be on to provide VDD
power to the sensor
- interrupt-parent: phandle to the parent interrupt controller as documented in
Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
- interrupts: interrupt mapping for IRQ as documented in
Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
Example:
zpa2326@5c {
compatible = "murata,zpa2326";
reg = <0x5c>;
interrupt-parent = <&gpio>;
interrupts = <12>;
vdd-supply = <&ldo_1v8_gnss>;
};

24
dts/Bindings/iio/proximity/sx9500.txt Normal file
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@ -0,0 +1,24 @@
Semtech's SX9500 capacitive proximity button device driver
Required properties:
- compatible: must be "semtech,sx9500"
- reg: i2c address where to find the device
- interrupt-parent : should be the phandle for the interrupt controller
- interrupts : the sole interrupt generated by the device
Refer to interrupt-controller/interrupts.txt for generic
interrupt client node bindings.
Optional properties:
- reset-gpios: Reference to the GPIO connected to the device's active
low reset pin.
Example:
sx9500@28 {
compatible = "semtech,sx9500";
reg = <0x28>;
interrupt-parent = <&gpio2>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
};

21
dts/Bindings/iio/temperature/maxim_thermocouple.txt Normal file
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@ -0,0 +1,21 @@
Maxim thermocouple support
* https://datasheets.maximintegrated.com/en/ds/MAX6675.pdf
* https://datasheets.maximintegrated.com/en/ds/MAX31855.pdf
Required properties:
- compatible: must be "maxim,max31855" or "maxim,max6675"
- reg: SPI chip select number for the device
- spi-max-frequency: must be 4300000
- spi-cpha: must be defined for max6675 to enable SPI mode 1
Refer to spi/spi-bus.txt for generic SPI slave bindings.
Example:
max31855@0 {
compatible = "maxim,max31855";
reg = <0>;
spi-max-frequency = <4300000>;
};

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