AM33xx: Make OSC frequency board depended
The oscillator frequency varies on different AM33xx boards. Pass the osc frequency from lowlevel board code to set the correct one on every board. Signed-off-by: Teresa Gámez <t.gamez@phytec.de> Reviewed-by: Jan Luebbe <jlu@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -198,7 +198,7 @@ void beaglebone_sram_init(void)
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u32 regVal, uart_base;
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/* Setup the PLLs and the clocks for the peripherals */
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pll_init(MPUPLL_M_500);
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pll_init(MPUPLL_M_500, 24);
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beaglebone_config_ddr();
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@ -159,7 +159,7 @@ void pcm051_sram_init(void)
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u32 regVal, uart_base;
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/* Setup the PLLs and the clocks for the peripherals */
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pll_init(MPUPLL_M_600);
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pll_init(MPUPLL_M_600, 25);
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pcm051_config_ddr();
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@ -156,7 +156,7 @@ static void per_clocks_enable(void)
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while (__raw_readl(CM_PER_SPI1_CLKCTRL) != PRCM_MOD_EN);
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}
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static void mpu_pll_config(int mpupll_M)
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static void mpu_pll_config(int mpupll_M, int osc)
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{
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u32 clkmode, clksel, div_m2;
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@ -170,7 +170,7 @@ static void mpu_pll_config(int mpupll_M)
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while(__raw_readl(CM_IDLEST_DPLL_MPU) != 0x00000100);
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clksel = clksel & (~0x7ffff);
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clksel = clksel | ((mpupll_M << 0x8) | MPUPLL_N);
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clksel = clksel | ((mpupll_M << 0x8) | (osc - 1));
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__raw_writel(clksel, CM_CLKSEL_DPLL_MPU);
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div_m2 = div_m2 & ~0x1f;
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@ -183,7 +183,7 @@ static void mpu_pll_config(int mpupll_M)
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while(__raw_readl(CM_IDLEST_DPLL_MPU) != 0x1);
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}
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static void core_pll_config(void)
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static void core_pll_config(int osc)
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{
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u32 clkmode, clksel, div_m4, div_m5, div_m6;
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@ -199,7 +199,7 @@ static void core_pll_config(void)
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while(__raw_readl(CM_IDLEST_DPLL_CORE) != 0x00000100);
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clksel = clksel & (~0x7ffff);
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clksel = clksel | ((COREPLL_M << 0x8) | COREPLL_N);
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clksel = clksel | ((COREPLL_M << 0x8) | (osc - 1));
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__raw_writel(clksel, CM_CLKSEL_DPLL_CORE);
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div_m4 = div_m4 & ~0x1f;
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@ -221,7 +221,7 @@ static void core_pll_config(void)
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while(__raw_readl(CM_IDLEST_DPLL_CORE) != 0x1);
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}
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static void per_pll_config(void)
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static void per_pll_config(int osc)
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{
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u32 clkmode, clksel, div_m2;
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@ -235,7 +235,7 @@ static void per_pll_config(void)
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while(__raw_readl(CM_IDLEST_DPLL_PER) != 0x00000100);
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clksel = clksel & (~0x7ffff);
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clksel = clksel | ((PERPLL_M << 0x8) | PERPLL_N);
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clksel = clksel | ((PERPLL_M << 0x8) | (osc - 1));
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__raw_writel(clksel, CM_CLKSEL_DPLL_PER);
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div_m2 = div_m2 & ~0x7f;
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@ -248,7 +248,7 @@ static void per_pll_config(void)
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while(__raw_readl(CM_IDLEST_DPLL_PER) != 0x1);
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}
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static void ddr_pll_config(void)
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static void ddr_pll_config(int osc)
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{
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u32 clkmode, clksel, div_m2;
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@ -263,7 +263,7 @@ static void ddr_pll_config(void)
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while ((__raw_readl(CM_IDLEST_DPLL_DDR) & 0x00000100) != 0x00000100);
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clksel = clksel & (~0x7ffff);
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clksel = clksel | ((DDRPLL_M << 0x8) | DDRPLL_N);
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clksel = clksel | ((DDRPLL_M << 0x8) | (osc - 1));
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__raw_writel(clksel, CM_CLKSEL_DPLL_DDR);
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div_m2 = div_m2 & 0xFFFFFFE0;
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@ -294,12 +294,12 @@ void enable_ddr_clocks(void)
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/*
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* Configure the PLL/PRCM for necessary peripherals
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*/
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void pll_init(int mpupll_M)
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void pll_init(int mpupll_M, int osc)
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{
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mpu_pll_config(mpupll_M);
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core_pll_config();
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per_pll_config();
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ddr_pll_config();
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mpu_pll_config(mpupll_M, osc);
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core_pll_config(osc);
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per_pll_config(osc);
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ddr_pll_config(osc);
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/* Enable the required interconnect clocks */
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interface_clocks_enable();
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/* Enable power domain transition */
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@ -23,20 +23,16 @@
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/* Put the pll config values over here */
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#define OSC 24
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/* MAIN PLL Fdll = 1 GHZ, */
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#define MPUPLL_M_500 500 /* 125 * n */
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#define MPUPLL_M_550 550 /* 125 * n */
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#define MPUPLL_M_600 600 /* 125 * n */
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#define MPUPLL_M_720 720 /* 125 * n */
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#define MPUPLL_N (OSC - 1)
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#define MPUPLL_M2 1
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/* Core PLL Fdll = 1 GHZ, */
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#define COREPLL_M 1000 /* 125 * n */
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#define COREPLL_N (OSC - 1)
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#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
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#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
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@ -48,13 +44,11 @@
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* For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
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*/
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#define PERPLL_M 960
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#define PERPLL_N (OSC - 1)
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#define PERPLL_M2 5
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/* DDR Freq is 266 MHZ for now*/
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/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
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#define DDRPLL_M 266
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#define DDRPLL_N (OSC - 1)
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#define DDRPLL_M2 1
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/* PRCM */
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@ -187,7 +181,7 @@
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#define CM_ALWON_GPMC_CLKCTRL CM_PER_GPMC_CLKCTRL
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extern void pll_init(int mpupll_M);
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extern void pll_init(int mpupll_M, int osc);
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extern void enable_ddr_clocks(void);
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#endif /* endif _AM33XX_CLOCKS_H_ */
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