svn_rev_577
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/*
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* linux/mii.h: definitions for MII-compatible transceivers
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* Originally drivers/net/sunhme.h.
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*
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* Copyright (C) 1996, 1999, 2001 David S. Miller (davem@redhat.com)
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*/
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#ifndef _MII_PHY_H_
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#define _MII_PHY_H_
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#define MIIPHY_FORCE_10 1
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#define MII_BMCR 0x00 /* Basic mode control register */
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#define MII_BMSR 0x01 /* Basic mode status register */
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#define MII_PHYSID1 0x02 /* PHYS ID 1 */
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#define MII_PHYSID2 0x03 /* PHYS ID 2 */
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#define MII_ADVERTISE 0x04 /* Advertisement control reg */
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#define MII_LPA 0x05 /* Link partner ability reg */
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#define MII_EXPANSION 0x06 /* Expansion register */
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#define MII_CTRL1000 0x09 /* 1000BASE-T control */
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#define MII_STAT1000 0x0a /* 1000BASE-T status */
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#define MII_ESTATUS 0x0f /* Extended Status */
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#define MII_DCOUNTER 0x12 /* Disconnect counter */
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#define MII_FCSCOUNTER 0x13 /* False carrier counter */
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#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
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#define MII_RERRCOUNTER 0x15 /* Receive error counter */
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#define MII_SREVISION 0x16 /* Silicon revision */
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#define MII_RESV1 0x17 /* Reserved... */
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#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
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#define MII_PHYADDR 0x19 /* PHY address */
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#define MII_RESV2 0x1a /* Reserved... */
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#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
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#define MII_NCONFIG 0x1c /* Network interface config */
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/* Basic mode control register. */
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#define BMCR_RESV 0x003f /* Unused... */
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#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
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#define BMCR_CTST 0x0080 /* Collision test */
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#define BMCR_FULLDPLX 0x0100 /* Full duplex */
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#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
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#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
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#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
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#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
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#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
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#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
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#define BMCR_RESET 0x8000 /* Reset the DP83840 */
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/* Basic mode status register. */
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#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
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#define BMSR_JCD 0x0002 /* Jabber detected */
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#define BMSR_LSTATUS 0x0004 /* Link status */
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#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
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#define BMSR_RFAULT 0x0010 /* Remote fault detected */
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#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
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#define BMSR_RESV 0x00c0 /* Unused... */
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#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
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#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
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#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
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#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
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#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
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#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
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#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
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#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
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/* Advertisement control register. */
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#define ADVERTISE_SLCT 0x001f /* Selector bits */
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#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
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#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
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#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
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#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
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#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
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#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
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#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
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#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
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#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
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#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
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#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
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#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
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#define ADVERTISE_RESV 0x1000 /* Unused... */
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#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
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#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
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#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
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#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
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ADVERTISE_CSMA)
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#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
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ADVERTISE_100HALF | ADVERTISE_100FULL)
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/* Link partner ability register. */
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#define LPA_SLCT 0x001f /* Same as advertise selector */
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#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
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#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
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#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
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#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
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#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
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#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
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#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
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#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/
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#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
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#define LPA_PAUSE_CAP 0x0400 /* Can pause */
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#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
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#define LPA_RESV 0x1000 /* Unused... */
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#define LPA_RFAULT 0x2000 /* Link partner faulted */
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#define LPA_LPACK 0x4000 /* Link partner acked us */
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#define LPA_NPAGE 0x8000 /* Next page bit */
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#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
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#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
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/* Expansion register for auto-negotiation. */
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#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
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#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
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#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
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#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
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#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
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#define EXPANSION_RESV 0xffe0 /* Unused... */
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#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
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#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
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/* N-way test register. */
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#define NWAYTEST_RESV1 0x00ff /* Unused... */
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#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
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#define NWAYTEST_RESV2 0xfe00 /* Unused... */
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/* 1000BASE-T Control register */
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#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
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#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
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/* 1000BASE-T Status register */
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#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
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#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
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#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
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#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
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struct miiphy_device {
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struct device_d dev;
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@ -20,80 +150,4 @@ int miiphy_restart_aneg(struct miiphy_device *mdev);
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int miiphy_wait_aneg(struct miiphy_device *mdev);
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int miiphy_print_status(struct miiphy_device *mdev);
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/* phy register offsets */
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#define PHY_BMCR 0x00
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#define PHY_BMSR 0x01
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#define PHY_PHYIDR1 0x02
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#define PHY_PHYIDR2 0x03
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#define PHY_ANAR 0x04
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#define PHY_ANLPAR 0x05
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#define PHY_ANER 0x06
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#define PHY_ANNPTR 0x07
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#define PHY_ANLPNP 0x08
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#define PHY_1000BTCR 0x09
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#define PHY_1000BTSR 0x0A
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#define PHY_PHYSTS 0x10
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#define PHY_MIPSCR 0x11
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#define PHY_MIPGSR 0x12
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#define PHY_DCR 0x13
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#define PHY_FCSCR 0x14
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#define PHY_RECR 0x15
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#define PHY_PCSR 0x16
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#define PHY_LBR 0x17
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#define PHY_10BTSCR 0x18
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#define PHY_PHYCTRL 0x19
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/* PHY BMCR */
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#define PHY_BMCR_RESET 0x8000
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#define PHY_BMCR_LOOP 0x4000
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#define PHY_BMCR_100MB 0x2000
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#define PHY_BMCR_AUTON 0x1000
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#define PHY_BMCR_POWD 0x0800
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#define PHY_BMCR_ISO 0x0400
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#define PHY_BMCR_RST_NEG 0x0200
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#define PHY_BMCR_DPLX 0x0100
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#define PHY_BMCR_COL_TST 0x0080
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#define PHY_BMCR_SPEED_MASK 0x2040
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#define PHY_BMCR_1000_MBPS 0x0040
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#define PHY_BMCR_100_MBPS 0x2000
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#define PHY_BMCR_10_MBPS 0x0000
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/* phy BMSR */
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#define PHY_BMSR_100T4 0x8000
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#define PHY_BMSR_100TXF 0x4000
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#define PHY_BMSR_100TXH 0x2000
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#define PHY_BMSR_10TF 0x1000
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#define PHY_BMSR_10TH 0x0800
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#define PHY_BMSR_PRE_SUP 0x0040
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#define PHY_BMSR_AUTN_COMP 0x0020
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#define PHY_BMSR_RF 0x0010
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#define PHY_BMSR_AUTN_ABLE 0x0008
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#define PHY_BMSR_LS 0x0004
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#define PHY_BMSR_JD 0x0002
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#define PHY_BMSR_EXT 0x0001
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/*phy ANLPAR */
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#define PHY_ANLPAR_NP 0x8000
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#define PHY_ANLPAR_ACK 0x4000
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#define PHY_ANLPAR_RF 0x2000
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#define PHY_ANLPAR_T4 0x0200
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#define PHY_ANLPAR_TXFD 0x0100
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#define PHY_ANLPAR_TX 0x0080
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#define PHY_ANLPAR_10FD 0x0040
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#define PHY_ANLPAR_10 0x0020
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#define PHY_ANLPAR_100 0x0380 /* we can run at 100 */
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#define PHY_ANLPAR_PSB_MASK 0x001f
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#define PHY_ANLPAR_PSB_802_3 0x0001
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#define PHY_ANLPAR_PSB_802_9 0x0002
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/* PHY_1000BTSR */
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#define PHY_1000BTSR_MSCF 0x8000
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#define PHY_1000BTSR_MSCR 0x4000
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#define PHY_1000BTSR_LRS 0x2000
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#define PHY_1000BTSR_RRS 0x1000
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#define PHY_1000BTSR_1000FD 0x0800
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#define PHY_1000BTSR_1000HD 0x0400
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#endif
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